From nobody Wed Dec 17 23:32:07 2025 Received: from mail-pl1-f177.google.com (mail-pl1-f177.google.com [209.85.214.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 934BE85C66 for ; Wed, 1 May 2024 12:18:12 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.214.177 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1714565894; cv=none; b=gUthKIiYi19d/fz6IoyhoujYMw92sQlKcXfM6ho2EEFnq3fk7Xni+SF1GCd3Stg/iM9+VIHDUJDEwFSvpUAEZRl8KPYuezmCy5zLzICDCD1RfiuTkobH4521u4bmPP2y0oSfzFTz4bj0TOVswdPKE3m+9lVAZadN/+eubaWLaJo= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1714565894; c=relaxed/simple; bh=Kpg2Dak2Sn/bLhHCJoIkdyJgXdEy9G8+cj88d9DTE1A=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=eeRaWcgowdXX46i102wDmbUc+KADwB0H85y3AAnw3cME8PeRZz4VJlriXqsYS6yhXiwpEFv+1GDa+pcHNlAZq+g9OP+Vk0fqY405BNwiSLaCAgvPj8aLOwClko8UuiD/Znrm9r481ZcKAztsj2Bid76a0y22NEzlhEsShlpiqoY= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=ventanamicro.com; spf=pass smtp.mailfrom=ventanamicro.com; dkim=pass (2048-bit key) header.d=ventanamicro.com header.i=@ventanamicro.com header.b=a8FNhmBr; arc=none smtp.client-ip=209.85.214.177 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=ventanamicro.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=ventanamicro.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=ventanamicro.com header.i=@ventanamicro.com header.b="a8FNhmBr" Received: by mail-pl1-f177.google.com with SMTP id d9443c01a7336-1e3ff14f249so5762675ad.1 for ; Wed, 01 May 2024 05:18:12 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1714565892; x=1715170692; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=TBFCNaiZG8SDhd9Avy2NjVgbIzDcy1byPrgimW8Jnrg=; b=a8FNhmBrj9rjKo0IZFUGsoe3E9xpfymjk3nZhZmeuqmlTL001CYguiU03v7oOsu6iS KWoBIM+swBSJHVWzHfo8BU5xiYby8aIhxyWzbPuUxUjJfzf71nsczxK45i4v7TzLywBc AXwXiuDJgc7XHM7UD0NGB89H8hpba+Cg5N26nRwerktBF4hSVix2LRvAsUS1iTPYrSNc D64pBdyzWtbgQBI/BQCA6OePXB2AO8qB7jkUHOyNJJPvWiXeKbpKyeJaL2toq1yQ3js2 x7ARNMsLYQAQxz40S4hniyTvNRmKFACuFeSDD9eosfIRLqv+Eoi11cIMmcpByrDpu1QZ QgEQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1714565892; x=1715170692; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=TBFCNaiZG8SDhd9Avy2NjVgbIzDcy1byPrgimW8Jnrg=; b=AyvRshMs0ZZPN7W/z9Efu5Q7EFmkptDfe1zMfZt4WzJNx0KqA51ZRePJG5vYn2hxP9 Ud5zIesFsZEJbYh+XiLcB6B/wb21/tK6ZtGdlnR9S7WWxsOrY+2QQi4omA9rgtl8MPHG Sa8YX3qGqMEvSnoklogEG5jE4oYEH+yJQfLwfz6JgYp7ooC1J12DGImN2hizuDzWmIqe eYPWMZRluLj3o5LWfHz8B4Qi3rqBaMWDgrA0QaRW8a261HG5hP71PIMhxBt2L/H44nTG CAgJX+ftkYHyfST/wS7tLoaGYEuoOGbEXk2M582RgAB5pJREbalRNd/xBLyBecHDpT5e gVSQ== X-Forwarded-Encrypted: i=1; AJvYcCVcCcQXFe3bE8g0PlNEk7KDyc3RVSj3QNOqmSkZcCorb686JFviEuKrvT9cfTXYaKcJpg3yRFFHSnvyjVUpmEZmgu5pXk7kXOxxsCam X-Gm-Message-State: AOJu0Yzf5BB8Z/uD1hf3h3a8PutTa77KObVVsAv+fFTVxSLGdQS4uNFG 2oZgLE6kK2KZADEFAwu9I+HougHGUL6AtXxa4p0P0vRCDcjhCSMozJ66ASuLBAI= X-Google-Smtp-Source: AGHT+IFCz+8u/X89VsHYsAyI7LAYB37fwi80edU6U2OxBpGy7t88sQSAo0aUQcHa3ElV/kemBD1B7A== X-Received: by 2002:a17:902:c40e:b0:1eb:527e:a89e with SMTP id k14-20020a170902c40e00b001eb527ea89emr8243829plk.26.1714565891753; Wed, 01 May 2024 05:18:11 -0700 (PDT) Received: from sunil-pc.Dlink ([106.51.188.106]) by smtp.gmail.com with ESMTPSA id im15-20020a170902bb0f00b001ec8888b22esm1336900plb.65.2024.05.01.05.18.04 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 01 May 2024 05:18:11 -0700 (PDT) From: Sunil V L To: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, linux-acpi@vger.kernel.org, linux-pci@vger.kernel.org, linux-serial@vger.kernel.org, acpica-devel@lists.linux.dev Cc: Catalin Marinas , Will Deacon , Paul Walmsley , Albert Ou , "Rafael J . Wysocki" , Len Brown , Bjorn Helgaas , Anup Patel , Thomas Gleixner , Samuel Holland , Greg Kroah-Hartman , Jiri Slaby , Robert Moore , Conor Dooley , Andrew Jones , Andy Shevchenko , Marc Zyngier , Atish Kumar Patra , Andrei Warkentin , Haibo1 Xu , =?UTF-8?q?Bj=C3=B6rn=20T=C3=B6pel?= , Sunil V L Subject: [PATCH v5 01/17] arm64: PCI: Migrate ACPI related functions to pci-acpi.c Date: Wed, 1 May 2024 17:47:26 +0530 Message-Id: <20240501121742.1215792-2-sunilvl@ventanamicro.com> X-Mailer: git-send-email 2.40.1 In-Reply-To: <20240501121742.1215792-1-sunilvl@ventanamicro.com> References: <20240501121742.1215792-1-sunilvl@ventanamicro.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The functions defined in arm64 for ACPI support are required for RISC-V also. To avoid duplication, move these functions to common location. Signed-off-by: Sunil V L Acked-by: Bjorn Helgaas Acked-by: Will Deacon --- arch/arm64/kernel/pci.c | 191 ---------------------------------------- drivers/pci/pci-acpi.c | 182 ++++++++++++++++++++++++++++++++++++++ 2 files changed, 182 insertions(+), 191 deletions(-) diff --git a/arch/arm64/kernel/pci.c b/arch/arm64/kernel/pci.c index f872c57e9909..fd9a7bed83ce 100644 --- a/arch/arm64/kernel/pci.c +++ b/arch/arm64/kernel/pci.c @@ -6,28 +6,7 @@ * Copyright (C) 2014 ARM Ltd. */ =20 -#include -#include -#include -#include -#include #include -#include -#include -#include - -#ifdef CONFIG_ACPI -/* - * Try to assign the IRQ number when probing a new device - */ -int pcibios_alloc_irq(struct pci_dev *dev) -{ - if (!acpi_disabled) - acpi_pci_irq_enable(dev); - - return 0; -} -#endif =20 /* * raw_pci_read/write - Platform-specific PCI config space access. @@ -61,173 +40,3 @@ int pcibus_to_node(struct pci_bus *bus) EXPORT_SYMBOL(pcibus_to_node); =20 #endif - -#ifdef CONFIG_ACPI - -struct acpi_pci_generic_root_info { - struct acpi_pci_root_info common; - struct pci_config_window *cfg; /* config space mapping */ -}; - -int acpi_pci_bus_find_domain_nr(struct pci_bus *bus) -{ - struct pci_config_window *cfg =3D bus->sysdata; - struct acpi_device *adev =3D to_acpi_device(cfg->parent); - struct acpi_pci_root *root =3D acpi_driver_data(adev); - - return root->segment; -} - -int pcibios_root_bridge_prepare(struct pci_host_bridge *bridge) -{ - struct pci_config_window *cfg; - struct acpi_device *adev; - struct device *bus_dev; - - if (acpi_disabled) - return 0; - - cfg =3D bridge->bus->sysdata; - - /* - * On Hyper-V there is no corresponding ACPI device for a root bridge, - * therefore ->parent is set as NULL by the driver. And set 'adev' as - * NULL in this case because there is no proper ACPI device. - */ - if (!cfg->parent) - adev =3D NULL; - else - adev =3D to_acpi_device(cfg->parent); - - bus_dev =3D &bridge->bus->dev; - - ACPI_COMPANION_SET(&bridge->dev, adev); - set_dev_node(bus_dev, acpi_get_node(acpi_device_handle(adev))); - - return 0; -} - -static int pci_acpi_root_prepare_resources(struct acpi_pci_root_info *ci) -{ - struct resource_entry *entry, *tmp; - int status; - - status =3D acpi_pci_probe_root_resources(ci); - resource_list_for_each_entry_safe(entry, tmp, &ci->resources) { - if (!(entry->res->flags & IORESOURCE_WINDOW)) - resource_list_destroy_entry(entry); - } - return status; -} - -/* - * Lookup the bus range for the domain in MCFG, and set up config space - * mapping. - */ -static struct pci_config_window * -pci_acpi_setup_ecam_mapping(struct acpi_pci_root *root) -{ - struct device *dev =3D &root->device->dev; - struct resource *bus_res =3D &root->secondary; - u16 seg =3D root->segment; - const struct pci_ecam_ops *ecam_ops; - struct resource cfgres; - struct acpi_device *adev; - struct pci_config_window *cfg; - int ret; - - ret =3D pci_mcfg_lookup(root, &cfgres, &ecam_ops); - if (ret) { - dev_err(dev, "%04x:%pR ECAM region not found\n", seg, bus_res); - return NULL; - } - - adev =3D acpi_resource_consumer(&cfgres); - if (adev) - dev_info(dev, "ECAM area %pR reserved by %s\n", &cfgres, - dev_name(&adev->dev)); - else - dev_warn(dev, FW_BUG "ECAM area %pR not reserved in ACPI namespace\n", - &cfgres); - - cfg =3D pci_ecam_create(dev, &cfgres, bus_res, ecam_ops); - if (IS_ERR(cfg)) { - dev_err(dev, "%04x:%pR error %ld mapping ECAM\n", seg, bus_res, - PTR_ERR(cfg)); - return NULL; - } - - return cfg; -} - -/* release_info: free resources allocated by init_info */ -static void pci_acpi_generic_release_info(struct acpi_pci_root_info *ci) -{ - struct acpi_pci_generic_root_info *ri; - - ri =3D container_of(ci, struct acpi_pci_generic_root_info, common); - pci_ecam_free(ri->cfg); - kfree(ci->ops); - kfree(ri); -} - -/* Interface called from ACPI code to setup PCI host controller */ -struct pci_bus *pci_acpi_scan_root(struct acpi_pci_root *root) -{ - struct acpi_pci_generic_root_info *ri; - struct pci_bus *bus, *child; - struct acpi_pci_root_ops *root_ops; - struct pci_host_bridge *host; - - ri =3D kzalloc(sizeof(*ri), GFP_KERNEL); - if (!ri) - return NULL; - - root_ops =3D kzalloc(sizeof(*root_ops), GFP_KERNEL); - if (!root_ops) { - kfree(ri); - return NULL; - } - - ri->cfg =3D pci_acpi_setup_ecam_mapping(root); - if (!ri->cfg) { - kfree(ri); - kfree(root_ops); - return NULL; - } - - root_ops->release_info =3D pci_acpi_generic_release_info; - root_ops->prepare_resources =3D pci_acpi_root_prepare_resources; - root_ops->pci_ops =3D (struct pci_ops *)&ri->cfg->ops->pci_ops; - bus =3D acpi_pci_root_create(root, root_ops, &ri->common, ri->cfg); - if (!bus) - return NULL; - - /* If we must preserve the resource configuration, claim now */ - host =3D pci_find_host_bridge(bus); - if (host->preserve_config) - pci_bus_claim_resources(bus); - - /* - * Assign whatever was left unassigned. If we didn't claim above, - * this will reassign everything. - */ - pci_assign_unassigned_root_bus_resources(bus); - - list_for_each_entry(child, &bus->children, node) - pcie_bus_configure_settings(child); - - return bus; -} - -void pcibios_add_bus(struct pci_bus *bus) -{ - acpi_pci_add_bus(bus); -} - -void pcibios_remove_bus(struct pci_bus *bus) -{ - acpi_pci_remove_bus(bus); -} - -#endif diff --git a/drivers/pci/pci-acpi.c b/drivers/pci/pci-acpi.c index 004575091596..e8d84fa435da 100644 --- a/drivers/pci/pci-acpi.c +++ b/drivers/pci/pci-acpi.c @@ -15,6 +15,7 @@ #include #include #include +#include #include #include #include @@ -1519,3 +1520,184 @@ static int __init acpi_pci_init(void) return 0; } arch_initcall(acpi_pci_init); + +#if defined(CONFIG_ARM64) + +/* + * Try to assign the IRQ number when probing a new device + */ +int pcibios_alloc_irq(struct pci_dev *dev) +{ + if (!acpi_disabled) + acpi_pci_irq_enable(dev); + + return 0; +} + +struct acpi_pci_generic_root_info { + struct acpi_pci_root_info common; + struct pci_config_window *cfg; /* config space mapping */ +}; + +int acpi_pci_bus_find_domain_nr(struct pci_bus *bus) +{ + struct pci_config_window *cfg =3D bus->sysdata; + struct acpi_device *adev =3D to_acpi_device(cfg->parent); + struct acpi_pci_root *root =3D acpi_driver_data(adev); + + return root->segment; +} + +int pcibios_root_bridge_prepare(struct pci_host_bridge *bridge) +{ + struct pci_config_window *cfg; + struct acpi_device *adev; + struct device *bus_dev; + + if (acpi_disabled) + return 0; + + cfg =3D bridge->bus->sysdata; + + /* + * On Hyper-V there is no corresponding ACPI device for a root bridge, + * therefore ->parent is set as NULL by the driver. And set 'adev' as + * NULL in this case because there is no proper ACPI device. + */ + if (!cfg->parent) + adev =3D NULL; + else + adev =3D to_acpi_device(cfg->parent); + + bus_dev =3D &bridge->bus->dev; + + ACPI_COMPANION_SET(&bridge->dev, adev); + set_dev_node(bus_dev, acpi_get_node(acpi_device_handle(adev))); + + return 0; +} + +static int pci_acpi_root_prepare_resources(struct acpi_pci_root_info *ci) +{ + struct resource_entry *entry, *tmp; + int status; + + status =3D acpi_pci_probe_root_resources(ci); + resource_list_for_each_entry_safe(entry, tmp, &ci->resources) { + if (!(entry->res->flags & IORESOURCE_WINDOW)) + resource_list_destroy_entry(entry); + } + return status; +} + +/* + * Lookup the bus range for the domain in MCFG, and set up config space + * mapping. + */ +static struct pci_config_window * +pci_acpi_setup_ecam_mapping(struct acpi_pci_root *root) +{ + struct device *dev =3D &root->device->dev; + struct resource *bus_res =3D &root->secondary; + u16 seg =3D root->segment; + const struct pci_ecam_ops *ecam_ops; + struct resource cfgres; + struct acpi_device *adev; + struct pci_config_window *cfg; + int ret; + + ret =3D pci_mcfg_lookup(root, &cfgres, &ecam_ops); + if (ret) { + dev_err(dev, "%04x:%pR ECAM region not found\n", seg, bus_res); + return NULL; + } + + adev =3D acpi_resource_consumer(&cfgres); + if (adev) + dev_info(dev, "ECAM area %pR reserved by %s\n", &cfgres, + dev_name(&adev->dev)); + else + dev_warn(dev, FW_BUG "ECAM area %pR not reserved in ACPI namespace\n", + &cfgres); + + cfg =3D pci_ecam_create(dev, &cfgres, bus_res, ecam_ops); + if (IS_ERR(cfg)) { + dev_err(dev, "%04x:%pR error %ld mapping ECAM\n", seg, bus_res, + PTR_ERR(cfg)); + return NULL; + } + + return cfg; +} + +/* release_info: free resources allocated by init_info */ +static void pci_acpi_generic_release_info(struct acpi_pci_root_info *ci) +{ + struct acpi_pci_generic_root_info *ri; + + ri =3D container_of(ci, struct acpi_pci_generic_root_info, common); + pci_ecam_free(ri->cfg); + kfree(ci->ops); + kfree(ri); +} + +/* Interface called from ACPI code to setup PCI host controller */ +struct pci_bus *pci_acpi_scan_root(struct acpi_pci_root *root) +{ + struct acpi_pci_generic_root_info *ri; + struct pci_bus *bus, *child; + struct acpi_pci_root_ops *root_ops; + struct pci_host_bridge *host; + + ri =3D kzalloc(sizeof(*ri), GFP_KERNEL); + if (!ri) + return NULL; + + root_ops =3D kzalloc(sizeof(*root_ops), GFP_KERNEL); + if (!root_ops) { + kfree(ri); + return NULL; + } + + ri->cfg =3D pci_acpi_setup_ecam_mapping(root); + if (!ri->cfg) { + kfree(ri); + kfree(root_ops); + return NULL; + } + + root_ops->release_info =3D pci_acpi_generic_release_info; + root_ops->prepare_resources =3D pci_acpi_root_prepare_resources; + root_ops->pci_ops =3D (struct pci_ops *)&ri->cfg->ops->pci_ops; + bus =3D acpi_pci_root_create(root, root_ops, &ri->common, ri->cfg); + if (!bus) + return NULL; + + /* If we must preserve the resource configuration, claim now */ + host =3D pci_find_host_bridge(bus); + if (host->preserve_config) + pci_bus_claim_resources(bus); + + /* + * Assign whatever was left unassigned. If we didn't claim above, + * this will reassign everything. + */ + pci_assign_unassigned_root_bus_resources(bus); + + list_for_each_entry(child, &bus->children, node) + pcie_bus_configure_settings(child); + + return bus; +} + +void pcibios_add_bus(struct pci_bus *bus) +{ + acpi_pci_add_bus(bus); +} + +void pcibios_remove_bus(struct pci_bus *bus) +{ + acpi_pci_remove_bus(bus); +} + +#endif --=20 2.40.1 From nobody Wed Dec 17 23:32:07 2025 Received: from mail-pl1-f173.google.com (mail-pl1-f173.google.com [209.85.214.173]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 2AAF885C66 for ; Wed, 1 May 2024 12:18:20 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.214.173 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1714565901; cv=none; b=MLT/s9sR6zzkb1onWETt7sSD2JwW5VvdpDFrjeVznY6AaMFsV2oV3mgcYXrVvzEOIRMQgRJqaMUHA582d4TCb222UzsRSLh1826eJAVTZN/NO6+v095uxGLUtJI3ccaxpscQLi45KOIbYoM0NDBAlv2oS34gHJJtfP+4Ji6FzAk= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1714565901; c=relaxed/simple; bh=F85RREqd/8SNFxuf3cR7FkJMyzMuMjsdvVkhYC6pOzM=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=JJqXx8joh8YSai7bnN1sGF9257fpjOYmSlhhJtaP4I+fj6wONPZINwiTn69YanFPZ9F6aLkd6qmEXIGCnvMOhy7Wcsig6G1VHQWTv/zrdc4d2BAsQoVWGBQdiasvU6X1uxZ5lFvDif4PzoB4pf4x31YaXLWFUYlllezIgPeh6Ps= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=ventanamicro.com; spf=pass smtp.mailfrom=ventanamicro.com; dkim=pass (2048-bit key) header.d=ventanamicro.com header.i=@ventanamicro.com header.b=GWlyB4A9; arc=none smtp.client-ip=209.85.214.173 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=ventanamicro.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=ventanamicro.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=ventanamicro.com header.i=@ventanamicro.com header.b="GWlyB4A9" Received: by mail-pl1-f173.google.com with SMTP id d9443c01a7336-1ec5387aed9so13688045ad.3 for ; Wed, 01 May 2024 05:18:20 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1714565900; x=1715170700; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=2U21IbVpVYWuDXnfpPitFjz/aLJhntW1ExhoP7hEzCc=; b=GWlyB4A9bLsb6rh2Gj7G5mzR0v60ja8rXP8r43Dt68LGK8ai4wflafr/et/fAMsj8s j8aPs5i1lvwGXByEm9nfjk3nNHigdvF+ZHhYMrh2E48tkVTEK8RUvARNG+rO0t0JH0VC YkoaTwczjYqNPHLseCiGJjCEM1hmV9pVW0ZPiwj5QIue56MgGB6B/CPgc1auj3mqWDdC rSUK1qm27Y4EdWRZwY7ZjaIZJj+vL0GBQ37u4ESkCy7s0R9SChuYmBgfqulCzW9GfclS ErFlNq8kZQoJJ/+87O2M1Hib2R+pE82Lw3AEd4MrCX5GctpZFR/9F/x2ZX7+AWqC2FGW s/rA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1714565900; x=1715170700; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=2U21IbVpVYWuDXnfpPitFjz/aLJhntW1ExhoP7hEzCc=; b=EHNaHmPg0pJkNR7FBiWIiOIYf1IpCR88T7/Qh2O+6fklooZaBko6SuSMGbjfTED9zP ef9lNUJXeL0F/GIpZIFX22KmXO16MnW1Fwsodz56aWCTtpfSGbfX/O0W07u6NjNK7epC umVHZPc4vyQv89n5qZriLxy8TmV9XNgXoOFsyOWR0VwE98srxUPMe7sEm+sXrOkfOrPw kIhsWbQa8ZOqG6AcECB++0HK1DBghiDcwgN7xWcQK7W78QIrdAvU+2HMCwhm1kxaeg2i 2B3qaAhx5aKu86iOzz6FD6bc87q6UMdXK4vZ8+JC565OMID4zFgGVfBLb7vUkF3NvNWs B4Jg== X-Forwarded-Encrypted: i=1; AJvYcCWkZdKBDIpiOphhOmbk2oYEUgrGSEuUymn45apuUmtkpOeO7hA+C74m/aF5tjIZFRPvs1wPhvnlUQme1YrCenf+BOX2HHPfdV2KtUDJ X-Gm-Message-State: AOJu0Yw5dKEEW8kvRaqcau24AF8qouC4iysSFsCeY15vAgLT7mMjWTRx F7yjmDEPLl2TmCfqC/Z1PkL5xC4qQ/RzgoYhwfJYAlrCydkLtg/BE26b4uaU0jE= X-Google-Smtp-Source: AGHT+IEhKN1Gue1zmrkCOUBSqcJjzhxCt/OVWXcOEWxant109xhmvof+8Br6KhAL2UNxeD7n9gvBjw== X-Received: by 2002:a17:903:11ce:b0:1e4:9c2f:d343 with SMTP id q14-20020a17090311ce00b001e49c2fd343mr2700552plh.7.1714565899631; Wed, 01 May 2024 05:18:19 -0700 (PDT) Received: from sunil-pc.Dlink ([106.51.188.106]) by smtp.gmail.com with ESMTPSA id im15-20020a170902bb0f00b001ec8888b22esm1336900plb.65.2024.05.01.05.18.12 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 01 May 2024 05:18:19 -0700 (PDT) From: Sunil V L To: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, linux-acpi@vger.kernel.org, linux-pci@vger.kernel.org, linux-serial@vger.kernel.org, acpica-devel@lists.linux.dev Cc: Catalin Marinas , Will Deacon , Paul Walmsley , Albert Ou , "Rafael J . Wysocki" , Len Brown , Bjorn Helgaas , Anup Patel , Thomas Gleixner , Samuel Holland , Greg Kroah-Hartman , Jiri Slaby , Robert Moore , Conor Dooley , Andrew Jones , Andy Shevchenko , Marc Zyngier , Atish Kumar Patra , Andrei Warkentin , Haibo1 Xu , =?UTF-8?q?Bj=C3=B6rn=20T=C3=B6pel?= , Sunil V L Subject: [PATCH v5 02/17] ACPI: scan: Add a weak function to reorder the IRQCHIP probe Date: Wed, 1 May 2024 17:47:27 +0530 Message-Id: <20240501121742.1215792-3-sunilvl@ventanamicro.com> X-Mailer: git-send-email 2.40.1 In-Reply-To: <20240501121742.1215792-1-sunilvl@ventanamicro.com> References: <20240501121742.1215792-1-sunilvl@ventanamicro.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Unlike OF framework, the irqchip probe using IRQCHIP_ACPI_DECLARE has no order defined. Depending on the Makefile is not a good idea. So, usually it is worked around by mandating only root interrupt controller probed using IRQCHIP_ACPI_DECLARE and other interrupt controllers are probed via cascade mechanism. However, this is also not a clean solution because if there are multiple root controllers (ex: RINTC in RISC-V which is per CPU) which need to be probed first, then the cascade will happen for every root controller. So, introduce a architecture specific weak function to order the probing of the interrupt controllers which can be implemented by different architectures as per their interrupt controller hierarchy. Signed-off-by: Sunil V L --- drivers/acpi/scan.c | 3 +++ include/linux/acpi.h | 2 ++ 2 files changed, 5 insertions(+) diff --git a/drivers/acpi/scan.c b/drivers/acpi/scan.c index 4804a2ad1578..837b8fc89dfb 100644 --- a/drivers/acpi/scan.c +++ b/drivers/acpi/scan.c @@ -2744,6 +2744,8 @@ static int __init acpi_match_madt(union acpi_subtable= _headers *header, return 0; } =20 +void __weak arch_sort_irqchip_probe(struct acpi_probe_entry *ap_head, int = nr) { } + int __init __acpi_probe_device_table(struct acpi_probe_entry *ap_head, int= nr) { int count =3D 0; @@ -2752,6 +2754,7 @@ int __init __acpi_probe_device_table(struct acpi_prob= e_entry *ap_head, int nr) return 0; =20 mutex_lock(&acpi_probe_mutex); + arch_sort_irqchip_probe(ap_head, nr); for (ape =3D ap_head; nr; ape++, nr--) { if (ACPI_COMPARE_NAMESEG(ACPI_SIG_MADT, ape->id)) { acpi_probe_count =3D 0; diff --git a/include/linux/acpi.h b/include/linux/acpi.h index c2ae33b8dbb6..1afa289f1f4e 100644 --- a/include/linux/acpi.h +++ b/include/linux/acpi.h @@ -1339,6 +1339,8 @@ struct acpi_probe_entry { kernel_ulong_t driver_data; }; =20 +void arch_sort_irqchip_probe(struct acpi_probe_entry *ap_head, int nr); + #define ACPI_DECLARE_PROBE_ENTRY(table, name, table_id, subtable, \ valid, data, fn) \ static const struct acpi_probe_entry __acpi_probe_##name \ --=20 2.40.1 From nobody Wed Dec 17 23:32:07 2025 Received: from mail-pl1-f169.google.com (mail-pl1-f169.google.com [209.85.214.169]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 1DF6F85C66 for ; Wed, 1 May 2024 12:18:27 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.214.169 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1714565909; cv=none; b=LedNiAcSGtXnk2XSga9AGlOlMJtT6R5FWeXbekkDitDGRTz0/xLrgq7WKWsgyWGunO94U9J7CWFvQgHiu+pNee/qni7AUju4jJxONjAvhfWUN0nU2YOko2zhlBa9tu8pe6Lxhx8/ZIEgfOyNVXsFdCScf3QQS6qLsnkhYrpfANg= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1714565909; c=relaxed/simple; bh=I/lQ3VyE5XbmB+cjOeRhBGW304XFfO2eyWXw80G6ZKQ=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=Fo2FOcCNRs/8D9gzlQsPCQ9fX+IT2QYb3hvTlHg99GWLsjXlMGsTbB5IwCBnWR29yWKFmsGRdcIrTtZHy7A6kGfYPLRPUvCeSuOONCvcSSu3M2prddrHMxLtrUttA0+QrJ4gyjR8wqNtibFB1PwVoDrokmzVGJGT1nlEqwPtU80= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=ventanamicro.com; spf=pass smtp.mailfrom=ventanamicro.com; dkim=pass (2048-bit key) header.d=ventanamicro.com header.i=@ventanamicro.com header.b=UMnHiSPd; arc=none smtp.client-ip=209.85.214.169 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=ventanamicro.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=ventanamicro.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=ventanamicro.com header.i=@ventanamicro.com header.b="UMnHiSPd" Received: by mail-pl1-f169.google.com with SMTP id d9443c01a7336-1eca195a7c8so2776875ad.2 for ; Wed, 01 May 2024 05:18:27 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1714565907; x=1715170707; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=pcwxR1GQk9U2hRbWPBz3q9MYCED3shcxZKp1VHv0hAo=; b=UMnHiSPddU2owumg6IwimKUfOMydVMc7sAL++gsGJXTjBb2/jWMAjnltM/BYYb4ZQJ tj0Xi41zKgMhQCxaHB/duAWyy81R1VziCquT9uf6U1c6kLTPbajx1sgt76pfrvA47+IC RK6/90N3aO1grpeZPyo8fezv84nq42rp1OshI4aMy2MS1a2ofQBJbwqcm7TxLJJbXTIQ Fj4+ImBMtjsh8ZJ6Um3o8h03HmpW3yGCIGnpEEYUVcfxq5zDJOv5fa0lzYh2u+tQmEMF aa6rANC5VPd8wUw3vqzAqn2nYQpfK90Y8WKUSri5HJQTU2m9Z8VS1nBQcW6gmyzmCAks kaEw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1714565907; x=1715170707; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=pcwxR1GQk9U2hRbWPBz3q9MYCED3shcxZKp1VHv0hAo=; b=u1Z0QWLr+Tv8Jl/fMVynMxoTPtDsPfWuseLkiZvjKLMvwe78RLPtgv7eF0ndxfaP8x 5qXa6v0AZDZFJWIWN9YQee5HbA3BQFgglc1Z7ZCNr9IXFLI4UUc+FtCxKq9OyFvgKnUj jT4lrHwWiOH7mstcQ7vteaUEAzVuaWFoGcFREYNqfNQNRO/6+oMgWWMQcl16oEK4IY8v nk8Up8tHKwKLPNnf5KJ4yuFlvy6NHETKHHtD/10znNn/mimaohWQl0XPkPkrW+WK0D6s wyQZ6Ti2zX0VFXkzFlrQAcrzGukzZqPCfKvgGGskcCk4XwqNBSzFAR0xwEODPPKfRX4o dvGw== X-Forwarded-Encrypted: i=1; AJvYcCVrwH7MjdDS9eB6vnAFiQwN1390VZ8BgbRJuccTe3BH4tApDQxj0z0Ux9Dr724LPnFjrEbxjXkPnWs0fxH/jnB+14e9NKv58mTWHdj+ X-Gm-Message-State: AOJu0YwkhejzeXLgu5W8y8icui7nVDYKws2FZtBTP6VrqVSIyj2sKmbL +CX1j/7VJ5XnK9nXln9DCvsAZtAG79I5pizaJSIEeAfta1H6Ifbyu8bLwDt2auw= X-Google-Smtp-Source: AGHT+IEeK1bdY+NiF6yJem6nH8XOZPBP0PcZb/eHB80G50De8R+NdOj9l68iFqCiSXYmU0FqhQ9LGA== X-Received: by 2002:a17:903:188:b0:1e5:5bd7:87a4 with SMTP id z8-20020a170903018800b001e55bd787a4mr2316455plg.16.1714565907491; Wed, 01 May 2024 05:18:27 -0700 (PDT) Received: from sunil-pc.Dlink ([106.51.188.106]) by smtp.gmail.com with ESMTPSA id im15-20020a170902bb0f00b001ec8888b22esm1336900plb.65.2024.05.01.05.18.20 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 01 May 2024 05:18:26 -0700 (PDT) From: Sunil V L To: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, linux-acpi@vger.kernel.org, linux-pci@vger.kernel.org, linux-serial@vger.kernel.org, acpica-devel@lists.linux.dev Cc: Catalin Marinas , Will Deacon , Paul Walmsley , Albert Ou , "Rafael J . Wysocki" , Len Brown , Bjorn Helgaas , Anup Patel , Thomas Gleixner , Samuel Holland , Greg Kroah-Hartman , Jiri Slaby , Robert Moore , Conor Dooley , Andrew Jones , Andy Shevchenko , Marc Zyngier , Atish Kumar Patra , Andrei Warkentin , Haibo1 Xu , =?UTF-8?q?Bj=C3=B6rn=20T=C3=B6pel?= , Sunil V L Subject: [PATCH v5 03/17] ACPI: bus: Add acpi_riscv_init function Date: Wed, 1 May 2024 17:47:28 +0530 Message-Id: <20240501121742.1215792-4-sunilvl@ventanamicro.com> X-Mailer: git-send-email 2.40.1 In-Reply-To: <20240501121742.1215792-1-sunilvl@ventanamicro.com> References: <20240501121742.1215792-1-sunilvl@ventanamicro.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add a new function for RISC-V to do any architecture specific initialization. This function will be used to create platform devices like APLIC, PLIC, RISC-V IOMMU etc. This is similar to acpi_arm_init(). Signed-off-by: Sunil V L --- drivers/acpi/bus.c | 1 + drivers/acpi/riscv/Makefile | 2 +- drivers/acpi/riscv/init.c | 12 ++++++++++++ include/linux/acpi.h | 6 ++++++ 4 files changed, 20 insertions(+), 1 deletion(-) create mode 100644 drivers/acpi/riscv/init.c diff --git a/drivers/acpi/bus.c b/drivers/acpi/bus.c index 844c46447914..17ee483c3bf4 100644 --- a/drivers/acpi/bus.c +++ b/drivers/acpi/bus.c @@ -1446,6 +1446,7 @@ static int __init acpi_init(void) acpi_hest_init(); acpi_ghes_init(); acpi_arm_init(); + acpi_riscv_init(); acpi_scan_init(); acpi_ec_init(); acpi_debugfs_init(); diff --git a/drivers/acpi/riscv/Makefile b/drivers/acpi/riscv/Makefile index 86b0925f612d..877de00d1b50 100644 --- a/drivers/acpi/riscv/Makefile +++ b/drivers/acpi/riscv/Makefile @@ -1,4 +1,4 @@ # SPDX-License-Identifier: GPL-2.0-only -obj-y +=3D rhct.o +obj-y +=3D rhct.o init.o obj-$(CONFIG_ACPI_PROCESSOR_IDLE) +=3D cpuidle.o obj-$(CONFIG_ACPI_CPPC_LIB) +=3D cppc.o diff --git a/drivers/acpi/riscv/init.c b/drivers/acpi/riscv/init.c new file mode 100644 index 000000000000..5f7571143245 --- /dev/null +++ b/drivers/acpi/riscv/init.c @@ -0,0 +1,12 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (C) 2023-2024, Ventana Micro Systems Inc + * Author: Sunil V L + * + */ + +#include + +void __init acpi_riscv_init(void) +{ +} diff --git a/include/linux/acpi.h b/include/linux/acpi.h index 1afa289f1f4e..846a4001b5e0 100644 --- a/include/linux/acpi.h +++ b/include/linux/acpi.h @@ -1527,6 +1527,12 @@ void acpi_arm_init(void); static inline void acpi_arm_init(void) { } #endif =20 +#ifdef CONFIG_RISCV +void acpi_riscv_init(void); +#else +static inline void acpi_riscv_init(void) { } +#endif + #ifdef CONFIG_ACPI_PCC void acpi_init_pcc(void); #else --=20 2.40.1 From nobody Wed Dec 17 23:32:07 2025 Received: from mail-pl1-f177.google.com (mail-pl1-f177.google.com [209.85.214.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 0D11885C66 for ; Wed, 1 May 2024 12:18:35 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.214.177 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1714565917; cv=none; b=NAMEzoa7Vdj2gLoWSrY+8vFEckCbMLXRQyzibX8PCzBOX3Kjp/NR5M8Ed+3MZhL3d9wq5Pb3iupTWTft2JfHeJsfaEwHlp1ncS7V9SjTcoeb90tsYN+3+Z6wJnNkGZVeyiywMHf62Vmrw9mnruALX+ryT+GDTA64D8p2I8pRRKI= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1714565917; c=relaxed/simple; bh=40G7efalCDrGiaKldSdMEYPAzuXFlQlo+Lbo7W3hChc=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=VV+/tL1IIBEopYOkAiaaMhcTIBJB+htQOhSYTi9lJnji5chKzerFshb27EEdb39/4MQeVy1Fj0JHo8IJ+wjylZn/CaSF6fdY+uEan4p+Q1z1dtRxz0Z1eiWG7EGX4gRBMUAzLCslWolOKYHQKRT5fwbS0qKr51UTuqShq0dDKwc= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=ventanamicro.com; spf=pass smtp.mailfrom=ventanamicro.com; dkim=pass (2048-bit key) header.d=ventanamicro.com header.i=@ventanamicro.com header.b=h4HZBs0B; arc=none smtp.client-ip=209.85.214.177 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=ventanamicro.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=ventanamicro.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=ventanamicro.com header.i=@ventanamicro.com header.b="h4HZBs0B" Received: by mail-pl1-f177.google.com with SMTP id d9443c01a7336-1e65a1370b7so62843425ad.3 for ; Wed, 01 May 2024 05:18:35 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1714565915; x=1715170715; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=lRvT/oDJzrljnZE8hh4Mfx8UjypBfU2BU36kOdk78lo=; b=h4HZBs0Bn73Rm4fNaVr3pul7ugd1BbfuHkILtLV0f8tkse95SrlILOungqpfHgKkrB m+NCLQ7JDz1EW/W0yFGhiCvWUBQvg7VGYI7zIGhmx5flfOzHH0dbIeSfoB8pj4IxBvk9 hjW3FgJo0NEFgTE4siK/J57Fdh4DU6gtAS90zF11b1KPW8n7gzZD//V48eCLAep4WIj5 jYwKKt4QQ0+TacKZajz1hMh4iTmvTOrP5BXo45l3MNIMx4I9dwOUxif2skIctkQcGmvg OrlWzsWPgiuQyuKrUfbZz3o/a5D+iqBjfY1g8v9hd5XU2CudQUBq3PDNTmw8Qmrf6SMH rLaQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1714565915; x=1715170715; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=lRvT/oDJzrljnZE8hh4Mfx8UjypBfU2BU36kOdk78lo=; b=LjCHzTn4O5311cFvR1+6MJ7dQR9In3wYF9OdIDZ2T6RXEjGRUL4XI6RLNHnwV1WD4T DWxHORGPJOZR3QtgqzUOQ9THT79SA+pa0BNR5EmK2cYjPU4xvS5Zb0YfUNEtULfU/Rpx dHZo9oz3ZiMNjcsYTaHHreYyB7zXgXDgrgcdmMRbcPzRNV3L0cKnCa/laooq6qwxOH6f +O11eeKsfPVEkiobWk8BFUwms9mbhQyRIViNaELcmzfBpuXEv4PRtuUUkSBhxpB4GVOy GkN9VmFWvE4MV4WroRPdwJaiCHL4K8raAVoHB5661LjFzu1tRcPe3YgfLZljVVV8O5Gp BKBA== X-Forwarded-Encrypted: i=1; AJvYcCVbsxL9MVaBV7FpMEQ2ZCpltQX6Y7wlWG4sJZ9p9ujMpZZgXCtLVv6J60AA49OstIfrnOxfM8JRRAMEYKooMAdupNnnNbp64WFDIGxK X-Gm-Message-State: AOJu0YxR2g7xRI5CLPUPG7LEHQBWKd9MGhyb34M+fuoSN9FGviODMVEo CSrm55DYmBth0g1Byq9AjxPi+xEGAzxuudVXL3FJyXVD2bsI8tPi/DbDeO0+kts= X-Google-Smtp-Source: AGHT+IFj7UjbvAZWh+cyRVOuEeVGC8mPfC0AaziB0MuMPmALOJzUu9Sq7LhvOrdMq5PmFj31+IKF9Q== X-Received: by 2002:a17:902:e5c4:b0:1eb:4a72:91ff with SMTP id u4-20020a170902e5c400b001eb4a7291ffmr3011610plf.49.1714565915161; Wed, 01 May 2024 05:18:35 -0700 (PDT) Received: from sunil-pc.Dlink ([106.51.188.106]) by smtp.gmail.com with ESMTPSA id im15-20020a170902bb0f00b001ec8888b22esm1336900plb.65.2024.05.01.05.18.27 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 01 May 2024 05:18:34 -0700 (PDT) From: Sunil V L To: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, linux-acpi@vger.kernel.org, linux-pci@vger.kernel.org, linux-serial@vger.kernel.org, acpica-devel@lists.linux.dev Cc: Catalin Marinas , Will Deacon , Paul Walmsley , Albert Ou , "Rafael J . Wysocki" , Len Brown , Bjorn Helgaas , Anup Patel , Thomas Gleixner , Samuel Holland , Greg Kroah-Hartman , Jiri Slaby , Robert Moore , Conor Dooley , Andrew Jones , Andy Shevchenko , Marc Zyngier , Atish Kumar Patra , Andrei Warkentin , Haibo1 Xu , =?UTF-8?q?Bj=C3=B6rn=20T=C3=B6pel?= , Sunil V L Subject: [PATCH v5 04/17] ACPI: scan: Refactor dependency creation Date: Wed, 1 May 2024 17:47:29 +0530 Message-Id: <20240501121742.1215792-5-sunilvl@ventanamicro.com> X-Mailer: git-send-email 2.40.1 In-Reply-To: <20240501121742.1215792-1-sunilvl@ventanamicro.com> References: <20240501121742.1215792-1-sunilvl@ventanamicro.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Some architectures like RISC-V will use implicit dependencies like GSI map to create dependencies between interrupt controller and devices. To support doing that, the function which creates the dependency, is refactored bit and made public so that dependency can be added from outside of scan.c as well. Signed-off-by: Sunil V L --- drivers/acpi/scan.c | 48 ++++++++++++++++++++++++----------------- include/acpi/acpi_bus.h | 1 + 2 files changed, 29 insertions(+), 20 deletions(-) diff --git a/drivers/acpi/scan.c b/drivers/acpi/scan.c index 837b8fc89dfb..3e3320ddb3da 100644 --- a/drivers/acpi/scan.c +++ b/drivers/acpi/scan.c @@ -2023,33 +2023,18 @@ static void acpi_scan_init_hotplug(struct acpi_devi= ce *adev) } } =20 -static u32 acpi_scan_check_dep(acpi_handle handle) +int acpi_scan_add_dep(acpi_handle handle, struct acpi_handle_list *dep_dev= ices) { - struct acpi_handle_list dep_devices; u32 count; int i; =20 - /* - * Check for _HID here to avoid deferring the enumeration of: - * 1. PCI devices. - * 2. ACPI nodes describing USB ports. - * Still, checking for _HID catches more then just these cases ... - */ - if (!acpi_has_method(handle, "_DEP") || !acpi_has_method(handle, "_HID")) - return 0; - - if (!acpi_evaluate_reference(handle, "_DEP", NULL, &dep_devices)) { - acpi_handle_debug(handle, "Failed to evaluate _DEP.\n"); - return 0; - } - - for (count =3D 0, i =3D 0; i < dep_devices.count; i++) { + for (count =3D 0, i =3D 0; i < dep_devices->count; i++) { struct acpi_device_info *info; struct acpi_dep_data *dep; bool skip, honor_dep; acpi_status status; =20 - status =3D acpi_get_object_info(dep_devices.handles[i], &info); + status =3D acpi_get_object_info(dep_devices->handles[i], &info); if (ACPI_FAILURE(status)) { acpi_handle_debug(handle, "Error reading _DEP device info\n"); continue; @@ -2068,7 +2053,7 @@ static u32 acpi_scan_check_dep(acpi_handle handle) =20 count++; =20 - dep->supplier =3D dep_devices.handles[i]; + dep->supplier =3D dep_devices->handles[i]; dep->consumer =3D handle; dep->honor_dep =3D honor_dep; =20 @@ -2077,7 +2062,30 @@ static u32 acpi_scan_check_dep(acpi_handle handle) mutex_unlock(&acpi_dep_list_lock); } =20 - acpi_handle_list_free(&dep_devices); + acpi_handle_list_free(dep_devices); + return count; +} + +static u32 acpi_scan_check_dep(acpi_handle handle) +{ + struct acpi_handle_list dep_devices; + u32 count =3D 0; + + /* + * Check for _HID here to avoid deferring the enumeration of: + * 1. PCI devices. + * 2. ACPI nodes describing USB ports. + * Still, checking for _HID catches more then just these cases ... + */ + if (!acpi_has_method(handle, "_DEP") || !acpi_has_method(handle, "_HID")) + return count; + + if (!acpi_evaluate_reference(handle, "_DEP", NULL, &dep_devices)) { + acpi_handle_debug(handle, "Failed to evaluate _DEP.\n"); + return count; + } + + count +=3D acpi_scan_add_dep(handle, &dep_devices); return count; } =20 diff --git a/include/acpi/acpi_bus.h b/include/acpi/acpi_bus.h index 1a4dfd7a1c4a..28a9b87c23fa 100644 --- a/include/acpi/acpi_bus.h +++ b/include/acpi/acpi_bus.h @@ -993,6 +993,7 @@ static inline void acpi_put_acpi_dev(struct acpi_device= *adev) =20 int acpi_wait_for_acpi_ipmi(void); =20 +int acpi_scan_add_dep(acpi_handle handle, struct acpi_handle_list *dep_dev= ices); #else /* CONFIG_ACPI */ =20 static inline int register_acpi_bus_type(void *bus) { return 0; } --=20 2.40.1 From nobody Wed Dec 17 23:32:07 2025 Received: from mail-pl1-f180.google.com (mail-pl1-f180.google.com [209.85.214.180]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 4B84A85C66 for ; Wed, 1 May 2024 12:18:43 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.214.180 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1714565925; cv=none; b=ZZM9U0BCRaAaCeM5ajyxv2/15pmpxEUYuWUCpLQNZR/2fL8Qo8EjmqCn/j7PgcrYIq/Gw+hK7N4TxaQZ+Vnzxt3zBnKT377Odh5cVutH9ahbX3KiOo9AAmaF7o1DAqwS576lBFUgVUbvLhrBxqjxN3Gc0USwqlGcjNy4+EcoqqE= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1714565925; c=relaxed/simple; bh=8Sfu8Z9vX1s+/fsrTVCUwOEPkW2bmWazbW7JyHI1Yzc=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=G9f33VhVp9+kSB9Bo9clKir8b73lsqIykh9UEvu9A1jys14eP63lgW6phC2ogZaAzISolPX29tHqwtYISjbtk1gPqary71+/WnT9mnOTtB7oQbQQ0RrQ54Ndfzz2h7KzrHh58wGqW7mbnKO5eQxWweJJMbIiIn94QmQsgIeNWNI= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=ventanamicro.com; spf=pass smtp.mailfrom=ventanamicro.com; dkim=pass (2048-bit key) header.d=ventanamicro.com header.i=@ventanamicro.com header.b=dQMgDEvd; arc=none smtp.client-ip=209.85.214.180 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=ventanamicro.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=ventanamicro.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=ventanamicro.com header.i=@ventanamicro.com header.b="dQMgDEvd" Received: by mail-pl1-f180.google.com with SMTP id d9443c01a7336-1ec41d82b8bso16634685ad.2 for ; Wed, 01 May 2024 05:18:43 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1714565923; x=1715170723; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=uNK+H7F1X6JmEpHoq/SVvyVT2dyL9n7lyqIUUwemfkM=; b=dQMgDEvdGDpkqffEqE0YIpbluC9isPcjHb1zOy6hv2Np2N/8nAVqGcGJRlwqvpUDY8 bnsB7zH723riXC83pII+dlLuSOPW1eOBGt++KkIbN5xvAmSq0UiDCO0zuz2vs4SKGWZy Tncrx+1FWLtyHRKzanmiqamw27DPSxEa84g15k0zJZDrK8muzvpaV+LfJ5bLoGJiSs/E ZGegZy9o7fQMonMn0YViScl3RPkZX1J5hry8+vrvxFb2zjqZWgbRjmY/jcv1yT4NslZg rtetA5YEBa6NGScgTCw+fArrKFiCSxWIxI11V5q8He7YHksYonh6/ciZed/jNjP4Nhmt CR2A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1714565923; x=1715170723; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=uNK+H7F1X6JmEpHoq/SVvyVT2dyL9n7lyqIUUwemfkM=; b=eWu3o1vZIapIsC2+ROatt4C1WT09F+uu4WQkQ05niEgcnsPZx4lUXA1d8y2ph6zIDB rCnwFJE2/ZiyQSGJdivtOImIqeCbhuVkx+vkqllN+oQa2EynXpEdEXU7wG9Qo5ytVEnU QNMmOjARhVDxU4yi9xV51o9r605mwyRnrenn8n3EhLh2uJY1AQx7WZZGb2s29kJeIRO4 Pm8scrfxZYRLlUSkHO8BicukRVDA3mJmDbGxtXhVxa/zTBTBl98njC17jslg9Pp5RUEc MMO6y1gzJEbvOgHGUBlZLre8FT68WvTP520jth8yyBH9BkF4rMSUeHfPzg5B/bij3CSA GzMA== X-Forwarded-Encrypted: i=1; AJvYcCVN5TB7h16213PY4FfwXiSJuEO9Sk5XSifAwHpRTT+jFTt5ol4ExewAXu64siGzofBWMM7EU8D0hjpt/vnpqx5OWAWBO04/qAKVDR7c X-Gm-Message-State: AOJu0YwPs3EoWG8gFQw87XcgGuuQEcU1AsTTjP9R+Au3pyZrnpdtzcnG D/DRHICh3rQ6uub+5kzZS2RssWNBzzKy/8hxtAjAxlMjP/IPi56HhG9eaJe50AU= X-Google-Smtp-Source: AGHT+IGI5pV9TYR10/cfbIQ9JMek+r7tBzzTGhtdRl1CfIULDyfaZRTCxXSzFPv/bTagC0SBwcv3pQ== X-Received: by 2002:a17:902:db09:b0:1ea:cc:e123 with SMTP id m9-20020a170902db0900b001ea00cce123mr2687556plx.46.1714565922763; Wed, 01 May 2024 05:18:42 -0700 (PDT) Received: from sunil-pc.Dlink ([106.51.188.106]) by smtp.gmail.com with ESMTPSA id im15-20020a170902bb0f00b001ec8888b22esm1336900plb.65.2024.05.01.05.18.35 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 01 May 2024 05:18:42 -0700 (PDT) From: Sunil V L To: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, linux-acpi@vger.kernel.org, linux-pci@vger.kernel.org, linux-serial@vger.kernel.org, acpica-devel@lists.linux.dev Cc: Catalin Marinas , Will Deacon , Paul Walmsley , Albert Ou , "Rafael J . Wysocki" , Len Brown , Bjorn Helgaas , Anup Patel , Thomas Gleixner , Samuel Holland , Greg Kroah-Hartman , Jiri Slaby , Robert Moore , Conor Dooley , Andrew Jones , Andy Shevchenko , Marc Zyngier , Atish Kumar Patra , Andrei Warkentin , Haibo1 Xu , =?UTF-8?q?Bj=C3=B6rn=20T=C3=B6pel?= , Sunil V L Subject: [PATCH v5 05/17] ACPI: scan: Add RISC-V interrupt controllers to honor list Date: Wed, 1 May 2024 17:47:30 +0530 Message-Id: <20240501121742.1215792-6-sunilvl@ventanamicro.com> X-Mailer: git-send-email 2.40.1 In-Reply-To: <20240501121742.1215792-1-sunilvl@ventanamicro.com> References: <20240501121742.1215792-1-sunilvl@ventanamicro.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" RISC-V PLIC and APLIC will have dependency from devices using GSI. So, add these devices to the honor list. Signed-off-by: Sunil V L --- drivers/acpi/scan.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/acpi/scan.c b/drivers/acpi/scan.c index 3e3320ddb3da..beded069cb0a 100644 --- a/drivers/acpi/scan.c +++ b/drivers/acpi/scan.c @@ -832,6 +832,8 @@ static const char * const acpi_honor_dep_ids[] =3D { "INTC1095", /* IVSC (ADL) driver must be loaded to allow i2c access to ca= mera sensors */ "INTC100A", /* IVSC (RPL) driver must be loaded to allow i2c access to ca= mera sensors */ "INTC10CF", /* IVSC (MTL) driver must be loaded to allow i2c access to ca= mera sensors */ + "RSCV0001", /* RISC-V PLIC */ + "RSCV0002", /* RISC-V APLIC */ NULL }; =20 --=20 2.40.1 From nobody Wed Dec 17 23:32:07 2025 Received: from mail-pl1-f174.google.com (mail-pl1-f174.google.com [209.85.214.174]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 4E2F5127B45 for ; Wed, 1 May 2024 12:18:51 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.214.174 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1714565932; cv=none; b=GMSN842J8Y8m79ZnggMCbF+5uc7jcZlKivniNzMr+s+6OUymwPkJLAJddgTEOttUZkWDx8ktcs3VMN85ietSj9i6acQ3MCemLdScLNBaYSwMdfsMWUhtnt564iJe9IbbALy/L+dWC460tyhQX6dHshQ+ffpn6d+Tgb3iumnblPw= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1714565932; c=relaxed/simple; bh=p3PlpHNinxzAsGkdtYqlBifL18TCbYSIHjqjLs8QrEI=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=IzYtvxqfdwdMsZUdM3bzzMGkxvxX0pL645E/e4mG8stLYKv+6YKTXX9nGchLN9NSAP7sllpAJf10g225953iohzdSecq609WV6vJ+P7bZHtoX/LD1oAH2wxq7EoWao8Hi52KgdfEJoc2iowV5L8lSRe3xyeWpOoQP6yy7oc7C6Q= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=ventanamicro.com; spf=pass smtp.mailfrom=ventanamicro.com; dkim=pass (2048-bit key) header.d=ventanamicro.com header.i=@ventanamicro.com header.b=Z9lae5WB; arc=none smtp.client-ip=209.85.214.174 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=ventanamicro.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=ventanamicro.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=ventanamicro.com header.i=@ventanamicro.com header.b="Z9lae5WB" Received: by mail-pl1-f174.google.com with SMTP id d9443c01a7336-1e3c3aa8938so44173905ad.1 for ; Wed, 01 May 2024 05:18:51 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1714565931; x=1715170731; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=NJK7HUkOtgooa4XBRIgNv++I9VXVR1Nc/x5AlB9DEr4=; b=Z9lae5WB3xIDPGD4UJhZYx7Qa/W0uxMoyHxCTitfqGzsHl2aJUGf3YvceYTTv2YjG4 kY8HlmtlOO+jywWivI8kbB3H/WJxg6LqKzl/YRzxE6+V9B4lz1alJyBwdlosPiEPr7o+ i7U3BW8h8CeKjERd2hVcY8imTPpFNzLftu1faBTkTEjlXLWX2ULgDa9jtmXCS8h8A0ON Tzyvl9P7NHf/0F0ASvNoODm84DCosmG1pkbS+WYB2qzw1jhLhjmeEFdClKKrXwDnsJGP F9Vqy46FGobUcgLQK4QffJB4mqIABnx6LUU04HtMJBJj7zPF1dalE44NApU2CXV6Dp6O uZVA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1714565931; x=1715170731; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=NJK7HUkOtgooa4XBRIgNv++I9VXVR1Nc/x5AlB9DEr4=; b=Bm7E6xBRSQFINcN1z9vhG/8/UBAalqFLzZNF2YDma46LvUAqBdcPXaic5RlaTSw6Ix J3MRYtXUyI0+fFp9XqOpPx8WzQ0KuqhAWCoeZEwV+tMn3vcvwRH9Mhrj+Iydlr/nx+2i jC0kgBlwYURJNg7Xd3eZaVaEQyrtq5im8UQSimJXzg70Vy3wOVaeHhSV9U1kVvj63qAC 5yKgIAeq4JePuDWqX7OnS+l9ixd+7+upIFkLcd9XbJ37PyanDujHZFNosWj3bFoEPROa Nw/0XP1dp1Ivx6TYJ66YStbPWArhazmv03VOFYEXIzjbGO3QiiwLAfqOrDOZdSLt44YX oMww== X-Forwarded-Encrypted: i=1; AJvYcCXLVmIu9uDKkoP57Bem0GW0k9EbdOJcOa6n8NQplYNF4IGlbJRFg+2MdRkXdWkDKitmJoBPMqIxUiv8qAI7iddcgeTznvc9WzqBt2vJ X-Gm-Message-State: AOJu0YxpbFhLtE1nuIIYJKiDcxMDQE8kh/2kyy+v+1adWTRy3hM6xBeH 90hQd5urUbWdUiS6CKMG3S/XDbh8CvGiP2osRTs04Y8Z+GbT8GMCUCv0G++BURs= X-Google-Smtp-Source: AGHT+IHqQHwdtyucv9ZMhP/dVbiOcapAJDdX24SUfAiXrmEd3YjBfB6sjT+VYhoitv18fuYmxMjC0Q== X-Received: by 2002:a17:902:eb4a:b0:1e9:470:87e6 with SMTP id i10-20020a170902eb4a00b001e9047087e6mr2178199pli.23.1714565930746; Wed, 01 May 2024 05:18:50 -0700 (PDT) Received: from sunil-pc.Dlink ([106.51.188.106]) by smtp.gmail.com with ESMTPSA id im15-20020a170902bb0f00b001ec8888b22esm1336900plb.65.2024.05.01.05.18.43 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 01 May 2024 05:18:50 -0700 (PDT) From: Sunil V L To: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, linux-acpi@vger.kernel.org, linux-pci@vger.kernel.org, linux-serial@vger.kernel.org, acpica-devel@lists.linux.dev Cc: Catalin Marinas , Will Deacon , Paul Walmsley , Albert Ou , "Rafael J . Wysocki" , Len Brown , Bjorn Helgaas , Anup Patel , Thomas Gleixner , Samuel Holland , Greg Kroah-Hartman , Jiri Slaby , Robert Moore , Conor Dooley , Andrew Jones , Andy Shevchenko , Marc Zyngier , Atish Kumar Patra , Andrei Warkentin , Haibo1 Xu , =?UTF-8?q?Bj=C3=B6rn=20T=C3=B6pel?= , Sunil V L Subject: [PATCH v5 06/17] ACPI: scan: Define weak function to populate dependencies Date: Wed, 1 May 2024 17:47:31 +0530 Message-Id: <20240501121742.1215792-7-sunilvl@ventanamicro.com> X-Mailer: git-send-email 2.40.1 In-Reply-To: <20240501121742.1215792-1-sunilvl@ventanamicro.com> References: <20240501121742.1215792-1-sunilvl@ventanamicro.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Some architectures like RISC-V need to add dependencies without explicit _DEP. Define a weak function which can be implemented by the architecture. Signed-off-by: Sunil V L --- drivers/acpi/scan.c | 11 +++++++++++ include/acpi/acpi_bus.h | 1 + 2 files changed, 12 insertions(+) diff --git a/drivers/acpi/scan.c b/drivers/acpi/scan.c index beded069cb0a..3eeb4ce39fcc 100644 --- a/drivers/acpi/scan.c +++ b/drivers/acpi/scan.c @@ -2068,11 +2068,22 @@ int acpi_scan_add_dep(acpi_handle handle, struct ac= pi_handle_list *dep_devices) return count; } =20 +u32 __weak arch_acpi_add_auto_dep(acpi_handle handle) { return 0; } + static u32 acpi_scan_check_dep(acpi_handle handle) { struct acpi_handle_list dep_devices; u32 count =3D 0; =20 + /* + * Some architectures like RISC-V need to add dependencies for + * all devices which use GSI to the interrupt controller so that + * interrupt controller is probed before any of those devices. + * Instead of mandating _DEP on all the devices, detect the + * dependency and add automatically. + */ + count +=3D arch_acpi_add_auto_dep(handle); + /* * Check for _HID here to avoid deferring the enumeration of: * 1. PCI devices. diff --git a/include/acpi/acpi_bus.h b/include/acpi/acpi_bus.h index 28a9b87c23fa..5fba4075d764 100644 --- a/include/acpi/acpi_bus.h +++ b/include/acpi/acpi_bus.h @@ -994,6 +994,7 @@ static inline void acpi_put_acpi_dev(struct acpi_device= *adev) int acpi_wait_for_acpi_ipmi(void); =20 int acpi_scan_add_dep(acpi_handle handle, struct acpi_handle_list *dep_dev= ices); +u32 arch_acpi_add_auto_dep(acpi_handle handle); #else /* CONFIG_ACPI */ =20 static inline int register_acpi_bus_type(void *bus) { return 0; } --=20 2.40.1 From nobody Wed Dec 17 23:32:07 2025 Received: from mail-pl1-f178.google.com (mail-pl1-f178.google.com [209.85.214.178]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E216185643 for ; Wed, 1 May 2024 12:18:58 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.214.178 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1714565941; cv=none; b=oBCObK3t9ZQGbEzV9d2FeFuPOnc4RIUNkVQDgmjm2YeJKT3OmbGpYonJQ9A+2lBbdeQ2P/PL/og7Dzd/01T4jofTkPfJMgGipsGCJdTW89vufTspuRlxNalw9m0GPUaebucOqkPK+Ql4i+p4Jb0M5HID18Vf7wMFZf1FKCs0pog= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1714565941; c=relaxed/simple; bh=CPhKTM+fujR2wlemEJtEAE/LXnd3DpxMM4jZCEYDYXE=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=LuDhZv+yLMCMKMxcM6jNdDvmkFJuUln8t1/cZUNM/lfRl7suU5oDu0uC3RLbv9JunR9kSMKpEbNwzLJDGTtOGrl0tBqdW2ufGlSpFykXroC/IM6e6QAqit9fsYSiDtwB3in/D/7NmsyFj1ANtl7khaAzjNML7LmCxAg6ckbhblM= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=ventanamicro.com; spf=pass smtp.mailfrom=ventanamicro.com; dkim=pass (2048-bit key) header.d=ventanamicro.com header.i=@ventanamicro.com header.b=Ep2IluZq; arc=none smtp.client-ip=209.85.214.178 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=ventanamicro.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=ventanamicro.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=ventanamicro.com header.i=@ventanamicro.com header.b="Ep2IluZq" Received: by mail-pl1-f178.google.com with SMTP id d9443c01a7336-1e3c9300c65so57039925ad.0 for ; Wed, 01 May 2024 05:18:58 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1714565938; x=1715170738; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=WOIqEzOMfBRaM7n+Lh1Tvfg7gL7m541laQZW313gOHY=; b=Ep2IluZqBWfF3BzeFXa/f/A9+iP9LRzreQnDkKcSUEhE1tRgAWDYrb7wpgBpbOf/Ys na9nxuIx36POxcd0YlqXg+ws4QHedX2RCHNtDcnn8XSyC0ii8ATVXMIPN0VQoYo2bNvS pewZCZdGDLBHsf3zuoAAbNbSuWHr+jhXLkBgaF+uwvDjSpl5n8aLZj5a6bnklsFqyNQQ lSrKgb2hZZsrwEv46XN27AFYm3swxqu+/r6812UhBzcQS+8Np/EoRWG1BrSoXV10po+l 3X4BqNRQXtHqAua97x7ziVE+f/bzTbT3ViSk8beV86OGB34NaLYHnvKPFS1pXlZ/feNv Mggg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1714565938; x=1715170738; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=WOIqEzOMfBRaM7n+Lh1Tvfg7gL7m541laQZW313gOHY=; b=TgZanlJhIKvFbLWMia9LJ2KrtULWu59eRPMKnBW1TvrwKHvs7h0g1qF1KMhe0skUnh ZeR1rkaX8vFpo6x1YHWbRLvkScWus61vJlqoWC2txGjYnhDOCDlaMpUnA2XwYWnj1HAX +H1cGE/KAH2freFhAtdtN1Wd8bBT6S1wfI6yuc95kn2Ukb8UEnowdmJ9Vo5jCAzQaBQl vAWai8wjAXmQKtLUpIViIiIU6rNa/ZTOaHCUGtSkwL1TBVDpdfbUBDfS7mluGuVvZm+X 6D3JuXu7J7aP5Qz4vMtcfALJ0s6Pzn0a5QkIOgEp/smgrstIcDKYf9I6qE1InlPHkVT4 sccg== X-Forwarded-Encrypted: i=1; AJvYcCWSgGY1JJ6S2ELqqnQsbplu5tEDcmLsV9H/GUnrq86bx5gam0EaKx/F5yxKA2Qgy+yHt1B+kW6Fhks1r0HV58R+FgN0z3r5QwLmvZtM X-Gm-Message-State: AOJu0YzrIZdBhxrnNLUixgvq5V9ppCNt6bKFQyzr/p0b2QsLaaYWhklB nWqgnadWecWitV03WeTHtRGjFnca/tpk2NgsIVNV7TbcAjUApyzuGXBX1/CW7CzClWy1+DLF6/G hhVQ= X-Google-Smtp-Source: AGHT+IGEfdWve8EtzQpflTL0dKP3MQxp+brvZfzYZ/NVGRzicQEMono2Ofsx4PyPFbkYzH1s9yqSdg== X-Received: by 2002:a17:903:496:b0:1e1:a54:1fe8 with SMTP id jj22-20020a170903049600b001e10a541fe8mr1877916plb.53.1714565938389; Wed, 01 May 2024 05:18:58 -0700 (PDT) Received: from sunil-pc.Dlink ([106.51.188.106]) by smtp.gmail.com with ESMTPSA id im15-20020a170902bb0f00b001ec8888b22esm1336900plb.65.2024.05.01.05.18.51 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 01 May 2024 05:18:57 -0700 (PDT) From: Sunil V L To: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, linux-acpi@vger.kernel.org, linux-pci@vger.kernel.org, linux-serial@vger.kernel.org, acpica-devel@lists.linux.dev Cc: Catalin Marinas , Will Deacon , Paul Walmsley , Albert Ou , "Rafael J . Wysocki" , Len Brown , Bjorn Helgaas , Anup Patel , Thomas Gleixner , Samuel Holland , Greg Kroah-Hartman , Jiri Slaby , Robert Moore , Conor Dooley , Andrew Jones , Andy Shevchenko , Marc Zyngier , Atish Kumar Patra , Andrei Warkentin , Haibo1 Xu , =?UTF-8?q?Bj=C3=B6rn=20T=C3=B6pel?= , Sunil V L Subject: [PATCH v5 07/17] ACPI: bus: Add RINTC IRQ model for RISC-V Date: Wed, 1 May 2024 17:47:32 +0530 Message-Id: <20240501121742.1215792-8-sunilvl@ventanamicro.com> X-Mailer: git-send-email 2.40.1 In-Reply-To: <20240501121742.1215792-1-sunilvl@ventanamicro.com> References: <20240501121742.1215792-1-sunilvl@ventanamicro.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add the IRQ model for RISC-V INTC so that acpi_set_irq_model can use this for RISC-V. Signed-off-by: Sunil V L --- drivers/acpi/bus.c | 3 +++ include/linux/acpi.h | 1 + 2 files changed, 4 insertions(+) diff --git a/drivers/acpi/bus.c b/drivers/acpi/bus.c index 17ee483c3bf4..6739db258a95 100644 --- a/drivers/acpi/bus.c +++ b/drivers/acpi/bus.c @@ -1190,6 +1190,9 @@ static int __init acpi_bus_init_irq(void) case ACPI_IRQ_MODEL_LPIC: message =3D "LPIC"; break; + case ACPI_IRQ_MODEL_RINTC: + message =3D "RINTC"; + break; default: pr_info("Unknown interrupt routing model\n"); return -ENODEV; diff --git a/include/linux/acpi.h b/include/linux/acpi.h index 846a4001b5e0..c1a01fd02873 100644 --- a/include/linux/acpi.h +++ b/include/linux/acpi.h @@ -107,6 +107,7 @@ enum acpi_irq_model_id { ACPI_IRQ_MODEL_PLATFORM, ACPI_IRQ_MODEL_GIC, ACPI_IRQ_MODEL_LPIC, + ACPI_IRQ_MODEL_RINTC, ACPI_IRQ_MODEL_COUNT }; =20 --=20 2.40.1 From nobody Wed Dec 17 23:32:07 2025 Received: from mail-pg1-f179.google.com (mail-pg1-f179.google.com [209.85.215.179]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C26C58565B for ; Wed, 1 May 2024 12:19:06 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.215.179 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1714565948; cv=none; b=GE9fnv8Ni69Ers+vVple61iw19o8c3Zv1wXxQVxmfrNFMyMeZWXFrgTvRvHLh4f3TeS/ciQ+8GemNfVVXY2HEo0qjRPj6fmd7vICLCK3wIr9jt4umJ9VSloMhpz2MqV4pFRVXrDJHzh7+bvu57KhOwIUY32GOsSyx0ruAFJJVXM= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1714565948; c=relaxed/simple; bh=nLWDIfQeIOjbntOKuF1sgqsUGviHan2c0T12uuyd8vE=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=XCaUJwKiSldGr3+nxqZOpEjGTcBA4aiehYjHEvuqi5pVsAhtRXj6HetpNGETV/qsltr1HLsXqwf8sv0ErxgOKFQ7LlljC2nk2rwJ/HWo0D8jRwQVZSBYhltyaz0GswukaPmuoVSErESFzMqt1gtgdJ+B0cczZZ31Y5b/YYoZ4eM= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=ventanamicro.com; spf=pass smtp.mailfrom=ventanamicro.com; dkim=pass (2048-bit key) header.d=ventanamicro.com header.i=@ventanamicro.com header.b=ShWYyazf; arc=none smtp.client-ip=209.85.215.179 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=ventanamicro.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=ventanamicro.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=ventanamicro.com header.i=@ventanamicro.com header.b="ShWYyazf" Received: by mail-pg1-f179.google.com with SMTP id 41be03b00d2f7-6174735c444so202265a12.1 for ; Wed, 01 May 2024 05:19:06 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1714565946; x=1715170746; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=38bWUcD6VJHgu2OT2TKY+rPPpBYSs9fss+ITqZ/SBFM=; b=ShWYyazf9u62scetDjspdRKnK+3QCXpS3eOR1JhA3IH9CQ+Abdh9Ahm8+tUAsytsjr +q73oJ+qCq+rjPPo7eV+DjDzmHHXT7EnzNG6OYPAmyGdU8Oz1ZWgiZkizvAfxseDRWto yhX2U4bxpmX6AAljJ5JcYFIoP2a/BYr5NI3R42/KXdXS0V2OmnMasDJ+5ft1+x1O3wNr ZmeQUeUrNWv5labCDfACCwpqCpdV322tS/zSVUcLGBcRq/RJa7qb9aTfmw0YJ6Uq5ntg 2upKtczKCgAABdZRA2q3CjmLfxVB6veBo/1bXLQXL8BYBdqFpwpeJwIeOiuET8jteMEW cILQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1714565946; x=1715170746; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=38bWUcD6VJHgu2OT2TKY+rPPpBYSs9fss+ITqZ/SBFM=; b=IS0CQSHRDIB0hylKojWiT0hUXVUpVXkJFKkc/W6ORA24nSoJ43vrVK/utJ7A9lHR7V lvpDZmaysiM3CiEkWRjMlTaG0KA/Cu8yT+sWQQSPCetFPmMMcHI+tPw85kZHIvH0gGaH CnskoUEl6ZnCWXmV6VQSnBaQOu1m7M32VM0WEK4sT0F74bfl38wa5RgxI5mAPO4Rz8gm IoCnya3uoksPgf4dG8m3bDyQJCPhNKPOZggE1olUKfoBadsMi6klmQE7VUbdV8ZvNmjE u/2Auxx149nvVfAsaNuiSVlPfetL+idor6azv6nA1PYhEVSz6tsL2Wd0Pye95kJbdJpJ Iycg== X-Forwarded-Encrypted: i=1; AJvYcCWbBuOOHE71vbOoYwdAL/bLUuvfnQEkC5zaaXTHJnDHugjY8SbBLX++RP7Dt0hyR4YO4EWiJCC2BAKHbLubdZlE/ZZBn7NtC22r5mny X-Gm-Message-State: AOJu0YwhMTtKm/fG6webSvCYS3cX3yH4fHsnd+3yopw1dO1lSpJ9Vcpz N7LSa8xo8e0rNfFpYP5NQuWE+5jrMjnDQPML03A8sETHrzCPuVsxI71YGfJmbcY= X-Google-Smtp-Source: AGHT+IGXC7NkAjACd9P5pWtq+Fm60ySdE8zHPZMKCP8HvEhNdRXNAHHqpbDgXk2ZkzDTp6OP1jYRcw== X-Received: by 2002:a17:903:2591:b0:1de:f93f:4410 with SMTP id jb17-20020a170903259100b001def93f4410mr1645679plb.8.1714565945995; Wed, 01 May 2024 05:19:05 -0700 (PDT) Received: from sunil-pc.Dlink ([106.51.188.106]) by smtp.gmail.com with ESMTPSA id im15-20020a170902bb0f00b001ec8888b22esm1336900plb.65.2024.05.01.05.18.58 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 01 May 2024 05:19:05 -0700 (PDT) From: Sunil V L To: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, linux-acpi@vger.kernel.org, linux-pci@vger.kernel.org, linux-serial@vger.kernel.org, acpica-devel@lists.linux.dev Cc: Catalin Marinas , Will Deacon , Paul Walmsley , Albert Ou , "Rafael J . Wysocki" , Len Brown , Bjorn Helgaas , Anup Patel , Thomas Gleixner , Samuel Holland , Greg Kroah-Hartman , Jiri Slaby , Robert Moore , Conor Dooley , Andrew Jones , Andy Shevchenko , Marc Zyngier , Atish Kumar Patra , Andrei Warkentin , Haibo1 Xu , =?UTF-8?q?Bj=C3=B6rn=20T=C3=B6pel?= , Sunil V L Subject: [PATCH v5 08/17] ACPI: pci_link: Clear the dependencies after probe Date: Wed, 1 May 2024 17:47:33 +0530 Message-Id: <20240501121742.1215792-9-sunilvl@ventanamicro.com> X-Mailer: git-send-email 2.40.1 In-Reply-To: <20240501121742.1215792-1-sunilvl@ventanamicro.com> References: <20240501121742.1215792-1-sunilvl@ventanamicro.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" RISC-V platforms need to use dependencies between PCI host bridge, Link devices and the interrupt controllers to ensure probe order. The dependency is like below. Interrupt controller <-- Link Device <-- PCI Host bridge. If there is no dependency added between Link device and PCI Host Bridge, then the PCI end points can get probed prior to link device, unable to get mapping for INTx. So, add the link device's HID to dependency honor list and also clear it after its probe. Since this is required only for architectures like RISC-V, enable this code under a new config option and set this only in RISC-V. Signed-off-by: Sunil V L --- arch/riscv/Kconfig | 1 + drivers/acpi/Kconfig | 3 +++ drivers/acpi/pci_link.c | 3 +++ drivers/acpi/scan.c | 1 + 4 files changed, 8 insertions(+) diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig index f961449ca077..f7a36d79ff1a 100644 --- a/arch/riscv/Kconfig +++ b/arch/riscv/Kconfig @@ -14,6 +14,7 @@ config RISCV def_bool y select ACPI_GENERIC_GSI if ACPI select ACPI_REDUCED_HARDWARE_ONLY if ACPI + select ARCH_ACPI_DEFERRED_GSI if ACPI select ARCH_DMA_DEFAULT_COHERENT select ARCH_ENABLE_HUGEPAGE_MIGRATION if HUGETLB_PAGE && MIGRATION select ARCH_ENABLE_SPLIT_PMD_PTLOCK if PGTABLE_LEVELS > 2 diff --git a/drivers/acpi/Kconfig b/drivers/acpi/Kconfig index e3a7c2aedd5f..ebec1707f662 100644 --- a/drivers/acpi/Kconfig +++ b/drivers/acpi/Kconfig @@ -587,6 +587,9 @@ config ACPI_PRMT substantially increase computational overhead related to the initialization of some server systems. =20 +config ARCH_ACPI_DEFERRED_GSI + bool + endif # ACPI =20 config X86_PM_TIMER diff --git a/drivers/acpi/pci_link.c b/drivers/acpi/pci_link.c index aa1038b8aec4..48cdcedafad6 100644 --- a/drivers/acpi/pci_link.c +++ b/drivers/acpi/pci_link.c @@ -748,6 +748,9 @@ static int acpi_pci_link_add(struct acpi_device *device, if (result) kfree(link); =20 + if (IS_ENABLED(CONFIG_ARCH_ACPI_DEFERRED_GSI)) + acpi_dev_clear_dependencies(device); + return result < 0 ? result : 1; } =20 diff --git a/drivers/acpi/scan.c b/drivers/acpi/scan.c index 3eeb4ce39fcc..67677a6ff8e3 100644 --- a/drivers/acpi/scan.c +++ b/drivers/acpi/scan.c @@ -834,6 +834,7 @@ static const char * const acpi_honor_dep_ids[] =3D { "INTC10CF", /* IVSC (MTL) driver must be loaded to allow i2c access to ca= mera sensors */ "RSCV0001", /* RISC-V PLIC */ "RSCV0002", /* RISC-V APLIC */ + "PNP0C0F", /* PCI Link Device */ NULL }; =20 --=20 2.40.1 From nobody Wed Dec 17 23:32:07 2025 Received: from mail-pl1-f181.google.com (mail-pl1-f181.google.com [209.85.214.181]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 872F28565E for ; Wed, 1 May 2024 12:19:14 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.214.181 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1714565955; cv=none; b=WO1ihsHVZxE80LwbUGWUAhAIa6PGFo2auMQLGo89S2Rg+fR08sSGqqSwH5sBE589OTT5nBx3k0291QhHYXYt0sP1Uv5Z8DMD8hvNmL2EW4KTQ8c1KfmagtT95S+Nq/GIhmBLSAwTuKQ7iq/no7LMEnXVPYIl5Zoz+AmYZEH0yUg= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1714565955; c=relaxed/simple; bh=cL7Je5RYE4qBGSwgVsumxbhFwtVnDhVheuCzr81f6SQ=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=iWu5zkxiSPsNJgoGhg5tdHeIpK/j5Jws7NfelycC5NBMJ38fU3YAha7pf639ejS5BiH2b8RQdk4fNirG3YJpccTkGJtFwGOiuQw/ao54p3VQhrljSS0nNXG7khKjVZcUZo4s2bhIyRLRXDXv5bVCKRHA56pUNj9BKeQ+5eV9fbU= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=ventanamicro.com; spf=pass smtp.mailfrom=ventanamicro.com; dkim=pass (2048-bit key) header.d=ventanamicro.com header.i=@ventanamicro.com header.b=YznQalVy; arc=none smtp.client-ip=209.85.214.181 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=ventanamicro.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=ventanamicro.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=ventanamicro.com header.i=@ventanamicro.com header.b="YznQalVy" Received: by mail-pl1-f181.google.com with SMTP id d9443c01a7336-1e4266673bbso60766355ad.2 for ; Wed, 01 May 2024 05:19:14 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1714565954; x=1715170754; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=ycPsvBm29e5SjcL+mnP2CfCAXKwmh5unfT08m5gLAm0=; b=YznQalVy0FKQq+MPsBAIVV8bpistELZgB8fC1TL1AeU046p3yMlGF8MxxF43KuthM6 BJZL2B+T5vrlTpj1lx21GjV2UvjfBJvm1i8HqLSz16Nn516/qZ844UIEBuD0o/D8t8MM sCWfyZdysdWyRMv0M602QV+8IiU5YA3Zhhrzwsqbb5VGM8Hav63i8iAfd8ihAR12tHQV 5/nZtEU4f0sjJZxD9mkWzCXcwxE63IaeINZONg0dV3NvBt0c9C6eTtmQck+CeV8S0uBc BE/0kYLPjGyLvSqyjBU3O0fsZyry3jsdILYmZ3NIdmiDEx98eWiOS1jRaj79i6LthH0C bd5Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1714565954; x=1715170754; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=ycPsvBm29e5SjcL+mnP2CfCAXKwmh5unfT08m5gLAm0=; b=Yvxc8ge6NPzf5LEI9w0HNUIlIKd0GxuqymU4Gp4ZFW7M/+PibmJuJh2p9cg8qHLzbJ 35yNYT1c7VwanAnNf1cKX57SP9EtCXauS5H0ZvcsHS6WI31TxkDZ5o+R5F+hXsWkU/E8 ZkhjPvWPPUtWFW1yh1cppR/DmOkM4qXvyPQFHDxikc1yzsMpRtG/axRptBoQkQQV4yDb I9Yks7W1jnrYM7RLZRNdjVhDb663p+8NipMPoD7Dxw9R/PWN8jyQd9hvnlSZtdVRrUdu G87hHt7jBnmnsHfu+A/RiabGbwJjegu+508+s2ND1+ObQELyFGAs0qrYxdXccPpQRZ/M NujA== X-Forwarded-Encrypted: i=1; AJvYcCUk3QCR9VVcQQnuuwPTzj7RVcsnz6zNVrVpawf4bkeNUnTGiIIt5rv/gr4xEaUiIx0sQ8RNYvHGZ/QkROUezuR6+5mozs4e/9A5WNaV X-Gm-Message-State: AOJu0Yy8ZM5PJNc31FXmYNfVOJQIUB1GUK7gv8MexAhMxnbXjmpqOulK XNaozGgyRheP6KbuguhxJPzwGPTQkKI7lSosQaNBksaeSMebBzdoukCXCLh45u0= X-Google-Smtp-Source: AGHT+IEDg6A+K3iip7ZStHi7uQnpL11UU8DLGuIplAfF1OsmX8JbUJctZLyYRcjpa+LuwJ/5zvxvdQ== X-Received: by 2002:a17:902:864a:b0:1ea:5ac0:ce46 with SMTP id y10-20020a170902864a00b001ea5ac0ce46mr1772335plt.66.1714565953984; Wed, 01 May 2024 05:19:13 -0700 (PDT) Received: from sunil-pc.Dlink ([106.51.188.106]) by smtp.gmail.com with ESMTPSA id im15-20020a170902bb0f00b001ec8888b22esm1336900plb.65.2024.05.01.05.19.06 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 01 May 2024 05:19:13 -0700 (PDT) From: Sunil V L To: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, linux-acpi@vger.kernel.org, linux-pci@vger.kernel.org, linux-serial@vger.kernel.org, acpica-devel@lists.linux.dev Cc: Catalin Marinas , Will Deacon , Paul Walmsley , Albert Ou , "Rafael J . Wysocki" , Len Brown , Bjorn Helgaas , Anup Patel , Thomas Gleixner , Samuel Holland , Greg Kroah-Hartman , Jiri Slaby , Robert Moore , Conor Dooley , Andrew Jones , Andy Shevchenko , Marc Zyngier , Atish Kumar Patra , Andrei Warkentin , Haibo1 Xu , =?UTF-8?q?Bj=C3=B6rn=20T=C3=B6pel?= , Sunil V L Subject: [PATCH v5 09/17] ACPI: RISC-V: Implement PCI related functionality Date: Wed, 1 May 2024 17:47:34 +0530 Message-Id: <20240501121742.1215792-10-sunilvl@ventanamicro.com> X-Mailer: git-send-email 2.40.1 In-Reply-To: <20240501121742.1215792-1-sunilvl@ventanamicro.com> References: <20240501121742.1215792-1-sunilvl@ventanamicro.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Replace the dummy implementation for PCI related functions with actual implementation. This needs ECAM and MCFG CONFIG options to be enabled for RISC-V. Signed-off-by: Sunil V L --- arch/riscv/Kconfig | 2 ++ arch/riscv/kernel/acpi.c | 31 ++++++++++++++----------------- drivers/pci/pci-acpi.c | 2 +- 3 files changed, 17 insertions(+), 18 deletions(-) diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig index f7a36d79ff1a..09a86256ddfa 100644 --- a/arch/riscv/Kconfig +++ b/arch/riscv/Kconfig @@ -13,6 +13,7 @@ config 32BIT config RISCV def_bool y select ACPI_GENERIC_GSI if ACPI + select ACPI_MCFG if (ACPI && PCI) select ACPI_REDUCED_HARDWARE_ONLY if ACPI select ARCH_ACPI_DEFERRED_GSI if ACPI select ARCH_DMA_DEFAULT_COHERENT @@ -176,6 +177,7 @@ config RISCV select OF_EARLY_FLATTREE select OF_IRQ select PCI_DOMAINS_GENERIC if PCI + select PCI_ECAM if (ACPI && PCI) select PCI_MSI if PCI select RISCV_ALTERNATIVE if !XIP_KERNEL select RISCV_APLIC diff --git a/arch/riscv/kernel/acpi.c b/arch/riscv/kernel/acpi.c index e619edc8b0cc..41aa77c8484b 100644 --- a/arch/riscv/kernel/acpi.c +++ b/arch/riscv/kernel/acpi.c @@ -306,29 +306,26 @@ void __iomem *acpi_os_ioremap(acpi_physical_address p= hys, acpi_size size) #ifdef CONFIG_PCI =20 /* - * These interfaces are defined just to enable building ACPI core. - * TODO: Update it with actual implementation when external interrupt - * controller support is added in RISC-V ACPI. + * raw_pci_read/write - Platform-specific PCI config space access. */ -int raw_pci_read(unsigned int domain, unsigned int bus, unsigned int devfn, - int reg, int len, u32 *val) +int raw_pci_read(unsigned int domain, unsigned int bus, + unsigned int devfn, int reg, int len, u32 *val) { - return PCIBIOS_DEVICE_NOT_FOUND; -} + struct pci_bus *b =3D pci_find_bus(domain, bus); =20 -int raw_pci_write(unsigned int domain, unsigned int bus, unsigned int devf= n, - int reg, int len, u32 val) -{ - return PCIBIOS_DEVICE_NOT_FOUND; + if (!b) + return PCIBIOS_DEVICE_NOT_FOUND; + return b->ops->read(b, devfn, reg, len, val); } =20 -int acpi_pci_bus_find_domain_nr(struct pci_bus *bus) +int raw_pci_write(unsigned int domain, unsigned int bus, + unsigned int devfn, int reg, int len, u32 val) { - return -1; -} + struct pci_bus *b =3D pci_find_bus(domain, bus); =20 -struct pci_bus *pci_acpi_scan_root(struct acpi_pci_root *root) -{ - return NULL; + if (!b) + return PCIBIOS_DEVICE_NOT_FOUND; + return b->ops->write(b, devfn, reg, len, val); } + #endif /* CONFIG_PCI */ diff --git a/drivers/pci/pci-acpi.c b/drivers/pci/pci-acpi.c index e8d84fa435da..b5892d0fa68c 100644 --- a/drivers/pci/pci-acpi.c +++ b/drivers/pci/pci-acpi.c @@ -1521,7 +1521,7 @@ static int __init acpi_pci_init(void) } arch_initcall(acpi_pci_init); =20 -#if defined(CONFIG_ARM64) +#if defined(CONFIG_ARM64) || defined(CONFIG_RISCV) =20 /* * Try to assign the IRQ number when probing a new device --=20 2.40.1 From nobody Wed Dec 17 23:32:07 2025 Received: from mail-pl1-f180.google.com (mail-pl1-f180.google.com [209.85.214.180]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 3EEFA85927 for ; Wed, 1 May 2024 12:19:22 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.214.180 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1714565964; cv=none; b=t7ZURgwnHv79VmYAQSAb3XbEx4h+wK/IA8z6X9qLUcRwsHGP3PsCBH/TTQiQo3rKnbiUpemZgBnafiBhEE0+ApVwQbnUvlbtr271YaVBj5CXSPGyxGIqbXyxS2I+3CWA/Al819NuZT47XNaR8dD5va02uMW3kK8YIdBtyYVgRiM= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1714565964; c=relaxed/simple; bh=WZ0YdhfhgqeeWdtO9JpwOCiBLPkx/74G9wavBJNzooo=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=i9kgS9ARV6uXPYpGmvB25nF4J3CY707JH1H5sYxj8URSWdQ6h1l2yVftE3vTh+ek7Jqii/Zuta8tN771Ook3juDxkQYZxXcmY+L5w91RfzFRznDDKVkqwOT+UZV2KFLtSKhWvaeu++yCX4+EQi3kJJcA7giNthOfYFbYst62uFs= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=ventanamicro.com; spf=pass smtp.mailfrom=ventanamicro.com; dkim=pass (2048-bit key) header.d=ventanamicro.com header.i=@ventanamicro.com header.b=aN0Xx3IG; arc=none smtp.client-ip=209.85.214.180 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=ventanamicro.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=ventanamicro.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=ventanamicro.com header.i=@ventanamicro.com header.b="aN0Xx3IG" Received: by mail-pl1-f180.google.com with SMTP id d9443c01a7336-1e651a9f3ffso33946185ad.1 for ; Wed, 01 May 2024 05:19:22 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1714565962; x=1715170762; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=Xxd/snqLqM7e5ONTmxzheAfPAEAmi9DZ2uBd4oJ/FYs=; b=aN0Xx3IGl0tGFPARP4HvbBlvg035recZ1vbtgJAMMydOTJdKVq3Pj8RVST6l/Oxypk HL4vThjVTqhwfL/CaaFtQxDtRWiRXIAK+NQSSsCt4o3oiYXSpou5whCSZS79bpdFguDX PW/VdOO1I9YOoyDCLqAUAAf5BkOZtAm6YMbgISSwhQV7B1HSkfZj5BGaSIPh2jQpYseK VPBn38yu0cQbg00nqEdKHNGSeOCfy/eF8KkgaOku5rRgW3/9euX4hR5FCflZQITKiRnt wPjS0noAfvPuYRZeK1vQxIYlOtmNShJgpC9thxUtyAh4I2Ef2tfZs+WTfz8zLl+wayQU 3zwA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1714565962; x=1715170762; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=Xxd/snqLqM7e5ONTmxzheAfPAEAmi9DZ2uBd4oJ/FYs=; b=aBkqnSYJV2BBkqvshPm5xM00EIF4YoFGA6aBOCEBDWHIdKLf+2nAlMyA1O48CN/ERk Xf9Hl10pzIv5ZvSSMwC6U9sEL/95vFPUloNwAn+6okif3e4rTnoO6OR9521VEQ+5FeI+ k9RKwaXPMS3j5MiXMKk/EN3anLKNnJW7SsTAHFhlETDWtNwvOn70ukNIEhRRHf/lYvp6 IFeb3aGac8rheEDXkFb+r7+NEtu4WOfPAOV2ajjYiYA28jfeyvTtx3oYT/hmaOqS06Oq vO5XffM533JNfVuSy5PVTeFAQFtXoUEi8zlpJeQJC3omo7rBmaLgGq/7LXHrMi/exXwW E7lA== X-Forwarded-Encrypted: i=1; AJvYcCX9mP8dyNzcE8nHM6RUxBwekAXVq4qDFRCrgP6mp3+CuyyCBww7ZLwW2HJG2x9Kbh5ZCt15Gpo/R5nJfu3I4HP8Cas54/1KSRerq3H1 X-Gm-Message-State: AOJu0YwN45Ks28zUnCQuLpWgI+Rv1oKKoXdnMbYSs4xlW3D3bPk8t3Qo fX/RXUWoQmCWMB2Fm2oYvr64HAOwDDBrCvavUKMIwhHMEU7bU1qnLgAyc2j8g6g= X-Google-Smtp-Source: AGHT+IGHJ7p4jwXpu3JYkUWYmOJNcHmWpwQOeQhUAAD/vtuVqVDXO7Ep5uVJu5jo4IP3B8sXFyhN1A== X-Received: by 2002:a17:902:f68e:b0:1e4:24cc:e021 with SMTP id l14-20020a170902f68e00b001e424cce021mr2637625plg.50.1714565961718; Wed, 01 May 2024 05:19:21 -0700 (PDT) Received: from sunil-pc.Dlink ([106.51.188.106]) by smtp.gmail.com with ESMTPSA id im15-20020a170902bb0f00b001ec8888b22esm1336900plb.65.2024.05.01.05.19.14 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 01 May 2024 05:19:21 -0700 (PDT) From: Sunil V L To: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, linux-acpi@vger.kernel.org, linux-pci@vger.kernel.org, linux-serial@vger.kernel.org, acpica-devel@lists.linux.dev Cc: Catalin Marinas , Will Deacon , Paul Walmsley , Albert Ou , "Rafael J . Wysocki" , Len Brown , Bjorn Helgaas , Anup Patel , Thomas Gleixner , Samuel Holland , Greg Kroah-Hartman , Jiri Slaby , Robert Moore , Conor Dooley , Andrew Jones , Andy Shevchenko , Marc Zyngier , Atish Kumar Patra , Andrei Warkentin , Haibo1 Xu , =?UTF-8?q?Bj=C3=B6rn=20T=C3=B6pel?= , Sunil V L Subject: [PATCH v5 10/17] ACPI: RISC-V: Implement function to reorder irqchip probe entries Date: Wed, 1 May 2024 17:47:35 +0530 Message-Id: <20240501121742.1215792-11-sunilvl@ventanamicro.com> X-Mailer: git-send-email 2.40.1 In-Reply-To: <20240501121742.1215792-1-sunilvl@ventanamicro.com> References: <20240501121742.1215792-1-sunilvl@ventanamicro.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" ACPI MADT entries for interrupt controllers don't have a way to describe the hierarchy. However, the hierarchy is known to the architecture and on RISC-V platforms, the MADT sub table types are ordered in the incremental order from the root controller which is RINTC. So, add architecture function for RISC-V to reorder the interrupt controller probing as per the hierarchy as below. Signed-off-by: Sunil V L --- drivers/acpi/riscv/Makefile | 2 +- drivers/acpi/riscv/irq.c | 32 ++++++++++++++++++++++++++++++++ 2 files changed, 33 insertions(+), 1 deletion(-) create mode 100644 drivers/acpi/riscv/irq.c diff --git a/drivers/acpi/riscv/Makefile b/drivers/acpi/riscv/Makefile index 877de00d1b50..a96fdf1e2cb8 100644 --- a/drivers/acpi/riscv/Makefile +++ b/drivers/acpi/riscv/Makefile @@ -1,4 +1,4 @@ # SPDX-License-Identifier: GPL-2.0-only -obj-y +=3D rhct.o init.o +obj-y +=3D rhct.o init.o irq.o obj-$(CONFIG_ACPI_PROCESSOR_IDLE) +=3D cpuidle.o obj-$(CONFIG_ACPI_CPPC_LIB) +=3D cppc.o diff --git a/drivers/acpi/riscv/irq.c b/drivers/acpi/riscv/irq.c new file mode 100644 index 000000000000..f56e103a501f --- /dev/null +++ b/drivers/acpi/riscv/irq.c @@ -0,0 +1,32 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (C) 2023-2024, Ventana Micro Systems Inc + * Author: Sunil V L + * + */ + +#include +#include + +static int irqchip_cmp_func(const void *in0, const void *in1) +{ + struct acpi_probe_entry *elem0 =3D (struct acpi_probe_entry *)in0; + struct acpi_probe_entry *elem1 =3D (struct acpi_probe_entry *)in1; + + return (elem0->type > elem1->type) - (elem0->type < elem1->type); +} + +/* + * RISC-V irqchips in MADT of ACPI spec are defined in the same order how + * they should be probed. Since IRQCHIP_ACPI_DECLARE doesn't define any + * order, this arch function will reorder the probe functions as per the + * required order for the architecture. + */ +void arch_sort_irqchip_probe(struct acpi_probe_entry *ap_head, int nr) +{ + struct acpi_probe_entry *ape =3D ap_head; + + if (nr =3D=3D 1 || !ACPI_COMPARE_NAMESEG(ACPI_SIG_MADT, ape->id)) + return; + sort(ape, nr, sizeof(*ape), irqchip_cmp_func, NULL); +} --=20 2.40.1 From nobody Wed Dec 17 23:32:07 2025 Received: from mail-pl1-f179.google.com (mail-pl1-f179.google.com [209.85.214.179]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id EE5B512EBEC for ; Wed, 1 May 2024 12:19:29 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.214.179 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1714565972; cv=none; b=W8Dki3ePAhNH6txgHl3gXrnVCLrw8/MJFVK2uR7MUK92g/LkT8PzkkEPWgkvOIic0jJrlLZkygYiHPeGalHSTpljoU05jKLYhQAf+gGAbgJmsw8+FHKmrh3LWcV1PiCxyHqrKQf1ao4kSqKFAseiH4ouQ0AkG2FfAJT6uS5jLpw= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1714565972; c=relaxed/simple; bh=cR3uveiGxGLJmRft6U2PQ0/OsQCFgHzkLGPMHFEaI+Q=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=HsFgJjdNzy5B8gbSLJNY8HnRyyPGE0Wpw+SSyYqoKHi6afyN/pDF7f3ECu6QUucvBL2J4wVhL9a/jBa0rOllVuVF8stFUEVmonLpIauDHWe6dwq5l1FCL9cNHilT3sbpwGZJywt7GP4KQqNAzeXMokMl6UQ3ybHG1Pj9jPudglg= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=ventanamicro.com; spf=pass smtp.mailfrom=ventanamicro.com; dkim=pass (2048-bit key) header.d=ventanamicro.com header.i=@ventanamicro.com header.b=Qgp6eE0T; arc=none smtp.client-ip=209.85.214.179 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=ventanamicro.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=ventanamicro.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=ventanamicro.com header.i=@ventanamicro.com header.b="Qgp6eE0T" Received: by mail-pl1-f179.google.com with SMTP id d9443c01a7336-1e83a2a4f2cso44241225ad.1 for ; Wed, 01 May 2024 05:19:29 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1714565969; x=1715170769; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=Dz2b5NSEn3co4GBYyIFhq4o1B5yNhLUdwhxGlUjO5R4=; b=Qgp6eE0Tu9P6gpYDpKsCPriIqlioqV7RWcmJLDtDayX5uyibX+dkppnZRbqOJrPuYh iKrXYEylIAcnOSOe0/qkApgMfjJiQUtd94fIqVeB00fYGdDFXJ/mK14bP/TIZeFTgfw4 +4WJ0c5Lfi0a74mxBh1eUt3NKHwUJLOEOJdBmU/BThVjIQBn6OIiMyAUGO5eYzEz+IK0 6LQe5Aw0gnpLxxgqz3O/NVBX/8kIdmU7+rv2vWCvQNivNzqBxJ9Xx7bzRnT5eypHVkfm wz8w+G34EtQIGl9TKw5VfNDqqCETS/fusLBvB8h9WTCFZVQSMb1H3vs4tFAJT1TJZMtE SMHQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1714565969; x=1715170769; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=Dz2b5NSEn3co4GBYyIFhq4o1B5yNhLUdwhxGlUjO5R4=; b=ovp2mS5R2G+f6Oebu+eZZbM4TRX5F3PMpb93AYReZtwYNC+H/hFmaq3ppfPu/y8vTp nK9KfY0kyhQb2yYGT673Rbab2DrC6UndP+5eTsKV2VXRDuEHxOHlYBxiFuBZPerV1ArC fbaL+wex3Bd+Y+NJk5mHXZ+WH3B4ujTqXcPHoKcDCc9QKtHcz9uDwfjPMil4oI7hqGOv A5aaJg8zxaOCyoZqMWQq2mcix+8YwoSLDXkzJ7PuLI/1K99TqFH13MXDHpLhc26qVwNW Xe9XD02yLApdGEAKstLVspVwvTTlUpLJfPZV3UHcIvTgVIqV8bAGUTUC+RcX7hfqZWlD iI7Q== X-Forwarded-Encrypted: i=1; AJvYcCVGMdZWjFi7xahUcegAZyFJAOH0yeU6riIPuGo6d+8Y7Dos2rBHHlx611vLB3lE+mtTxZhE6jkCbCmji+jmDCz3u9oeKTSi3BSuLWVb X-Gm-Message-State: AOJu0Yy76fe1quWh9UxYG4nEL5h57fdL2oj79pMYjpgmVwXVe1cNPhMc sOCbEbtBniPLkEy0tGW04rnlXUkVl8vlcz27NM/8P3Adks6GpYcq8b3SpE0xgfg= X-Google-Smtp-Source: AGHT+IGuRwan9lf3M8PVSXZJfG+1Q3Prn5rtC3kcGZRvNV0TM+LqWfnB21N8buGjJXUbpyfls7vG+g== X-Received: by 2002:a17:902:6506:b0:1e4:471f:2fa1 with SMTP id b6-20020a170902650600b001e4471f2fa1mr2381346plk.24.1714565969394; Wed, 01 May 2024 05:19:29 -0700 (PDT) Received: from sunil-pc.Dlink ([106.51.188.106]) by smtp.gmail.com with ESMTPSA id im15-20020a170902bb0f00b001ec8888b22esm1336900plb.65.2024.05.01.05.19.22 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 01 May 2024 05:19:28 -0700 (PDT) From: Sunil V L To: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, linux-acpi@vger.kernel.org, linux-pci@vger.kernel.org, linux-serial@vger.kernel.org, acpica-devel@lists.linux.dev Cc: Catalin Marinas , Will Deacon , Paul Walmsley , Albert Ou , "Rafael J . Wysocki" , Len Brown , Bjorn Helgaas , Anup Patel , Thomas Gleixner , Samuel Holland , Greg Kroah-Hartman , Jiri Slaby , Robert Moore , Conor Dooley , Andrew Jones , Andy Shevchenko , Marc Zyngier , Atish Kumar Patra , Andrei Warkentin , Haibo1 Xu , =?UTF-8?q?Bj=C3=B6rn=20T=C3=B6pel?= , Sunil V L Subject: [PATCH v5 11/17] ACPI: RISC-V: Initialize GSI mapping structures Date: Wed, 1 May 2024 17:47:36 +0530 Message-Id: <20240501121742.1215792-12-sunilvl@ventanamicro.com> X-Mailer: git-send-email 2.40.1 In-Reply-To: <20240501121742.1215792-1-sunilvl@ventanamicro.com> References: <20240501121742.1215792-1-sunilvl@ventanamicro.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" RISC-V has PLIC and APLIC in MADT as well as namespace devices. Initialize the list of those structures using MADT and namespace devices to create mapping between the ACPI handle and the GSI ranges. This will be used later to add dependencies. Signed-off-by: Sunil V L --- arch/riscv/include/asm/irq.h | 22 ++++++ drivers/acpi/riscv/init.c | 2 + drivers/acpi/riscv/init.h | 4 + drivers/acpi/riscv/irq.c | 142 +++++++++++++++++++++++++++++++++++ 4 files changed, 170 insertions(+) create mode 100644 drivers/acpi/riscv/init.h diff --git a/arch/riscv/include/asm/irq.h b/arch/riscv/include/asm/irq.h index 8e10a94430a2..44a0b128c602 100644 --- a/arch/riscv/include/asm/irq.h +++ b/arch/riscv/include/asm/irq.h @@ -16,4 +16,26 @@ void riscv_set_intc_hwnode_fn(struct fwnode_handle *(*fn= )(void)); =20 struct fwnode_handle *riscv_get_intc_hwnode(void); =20 +#ifdef CONFIG_ACPI + +enum riscv_irqchip_type { + ACPI_RISCV_IRQCHIP_INTC =3D 0x00, + ACPI_RISCV_IRQCHIP_IMSIC =3D 0x01, + ACPI_RISCV_IRQCHIP_PLIC =3D 0x02, + ACPI_RISCV_IRQCHIP_APLIC =3D 0x03, +}; + +int riscv_acpi_get_gsi_info(struct fwnode_handle *fwnode, u32 *gsi_base, + u32 *id, u32 *nr_irqs, u32 *nr_idcs); +struct fwnode_handle *riscv_acpi_get_gsi_domain_id(u32 gsi); + +#else +static inline int riscv_acpi_get_gsi_info(struct fwnode_handle *fwnode, u3= 2 *gsi_base, + u32 *id, u32 *nr_irqs, u32 *nr_idcs) +{ + return 0; +} + +#endif /* CONFIG_ACPI */ + #endif /* _ASM_RISCV_IRQ_H */ diff --git a/drivers/acpi/riscv/init.c b/drivers/acpi/riscv/init.c index 5f7571143245..22db97f7a772 100644 --- a/drivers/acpi/riscv/init.c +++ b/drivers/acpi/riscv/init.c @@ -6,7 +6,9 @@ */ =20 #include +#include "init.h" =20 void __init acpi_riscv_init(void) { + riscv_acpi_init_gsi_mapping(); } diff --git a/drivers/acpi/riscv/init.h b/drivers/acpi/riscv/init.h new file mode 100644 index 000000000000..0b9a07e4031f --- /dev/null +++ b/drivers/acpi/riscv/init.h @@ -0,0 +1,4 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +#include + +void __init riscv_acpi_init_gsi_mapping(void); diff --git a/drivers/acpi/riscv/irq.c b/drivers/acpi/riscv/irq.c index f56e103a501f..0473428e8d1e 100644 --- a/drivers/acpi/riscv/irq.c +++ b/drivers/acpi/riscv/irq.c @@ -7,6 +7,21 @@ =20 #include #include +#include + +#include "init.h" + +struct riscv_ext_intc_list { + acpi_handle handle; + u32 gsi_base; + u32 nr_irqs; + u32 nr_idcs; + u32 id; + u32 type; + struct list_head list; +}; + +LIST_HEAD(ext_intc_list); =20 static int irqchip_cmp_func(const void *in0, const void *in1) { @@ -30,3 +45,130 @@ void arch_sort_irqchip_probe(struct acpi_probe_entry *a= p_head, int nr) return; sort(ape, nr, sizeof(*ape), irqchip_cmp_func, NULL); } + +static void riscv_acpi_update_gsi_handle(u32 gsi_base, acpi_handle handle) +{ + struct riscv_ext_intc_list *ext_intc_element; + struct list_head *i, *tmp; + + list_for_each_safe(i, tmp, &ext_intc_list) { + ext_intc_element =3D list_entry(i, struct riscv_ext_intc_list, list); + if (gsi_base =3D=3D ext_intc_element->gsi_base) { + ext_intc_element->handle =3D handle; + return; + } + } + + acpi_handle_err(handle, "failed to find the GSI mapping entry\n"); +} + +int riscv_acpi_get_gsi_info(struct fwnode_handle *fwnode, u32 *gsi_base, + u32 *id, u32 *nr_irqs, u32 *nr_idcs) +{ + struct riscv_ext_intc_list *ext_intc_element; + struct list_head *i, *tmp; + + list_for_each_safe(i, tmp, &ext_intc_list) { + ext_intc_element =3D list_entry(i, struct riscv_ext_intc_list, list); + if (ext_intc_element->handle =3D=3D ACPI_HANDLE_FWNODE(fwnode)) { + *gsi_base =3D ext_intc_element->gsi_base; + *id =3D ext_intc_element->id; + *nr_irqs =3D ext_intc_element->nr_irqs; + if (nr_idcs) + *nr_idcs =3D ext_intc_element->nr_idcs; + + return 0; + } + } + + return -ENODEV; +} + +struct fwnode_handle *riscv_acpi_get_gsi_domain_id(u32 gsi) +{ + struct riscv_ext_intc_list *ext_intc_element; + struct acpi_device *adev; + struct list_head *i, *tmp; + + list_for_each_safe(i, tmp, &ext_intc_list) { + ext_intc_element =3D list_entry(i, struct riscv_ext_intc_list, list); + if (gsi >=3D ext_intc_element->gsi_base && + gsi < (ext_intc_element->gsi_base + ext_intc_element->nr_irqs)) { + adev =3D acpi_fetch_acpi_dev(ext_intc_element->handle); + if (!adev) + return NULL; + + return acpi_fwnode_handle(adev); + } + } + + return NULL; +} + +static int __init riscv_acpi_register_ext_intc(u32 gsi_base, u32 nr_irqs, = u32 nr_idcs, + u32 id, u32 type) +{ + struct riscv_ext_intc_list *ext_intc_element; + + ext_intc_element =3D kzalloc(sizeof(*ext_intc_element), GFP_KERNEL); + if (!ext_intc_element) + return -ENOMEM; + + ext_intc_element->gsi_base =3D gsi_base; + ext_intc_element->nr_irqs =3D nr_irqs; + ext_intc_element->nr_idcs =3D nr_idcs; + ext_intc_element->id =3D id; + list_add_tail(&ext_intc_element->list, &ext_intc_list); + return 0; +} + +static acpi_status __init riscv_acpi_create_gsi_map(acpi_handle handle, u3= 2 level, + void *context, void **return_value) +{ + acpi_status status; + u64 gbase; + + if (!acpi_has_method(handle, "_GSB")) { + acpi_handle_err(handle, "_GSB method not found\n"); + return AE_OK; + } + + status =3D acpi_evaluate_integer(handle, "_GSB", NULL, &gbase); + if (ACPI_FAILURE(status)) { + acpi_handle_err(handle, "failed to evaluate _GSB method\n"); + return AE_OK; + } + + riscv_acpi_update_gsi_handle((u32)gbase, handle); + return AE_OK; +} + +static int __init riscv_acpi_aplic_parse_madt(union acpi_subtable_headers = *header, + const unsigned long end) +{ + struct acpi_madt_aplic *aplic =3D (struct acpi_madt_aplic *)header; + + return riscv_acpi_register_ext_intc(aplic->gsi_base, aplic->num_sources, = aplic->num_idcs, + aplic->id, ACPI_RISCV_IRQCHIP_APLIC); +} + +static int __init riscv_acpi_plic_parse_madt(union acpi_subtable_headers *= header, + const unsigned long end) +{ + struct acpi_madt_plic *plic =3D (struct acpi_madt_plic *)header; + + return riscv_acpi_register_ext_intc(plic->gsi_base, plic->num_irqs, 0, + plic->id, ACPI_RISCV_IRQCHIP_PLIC); +} + +void __init riscv_acpi_init_gsi_mapping(void) +{ + /* There can be either PLIC or APLIC */ + if (acpi_table_parse_madt(ACPI_MADT_TYPE_PLIC, riscv_acpi_plic_parse_madt= , 0) > 0) { + acpi_get_devices("RSCV0001", riscv_acpi_create_gsi_map, NULL, NULL); + return; + } + + if (acpi_table_parse_madt(ACPI_MADT_TYPE_APLIC, riscv_acpi_aplic_parse_ma= dt, 0) > 0) + acpi_get_devices("RSCV0002", riscv_acpi_create_gsi_map, NULL, NULL); +} --=20 2.40.1 From nobody Wed Dec 17 23:32:07 2025 Received: from mail-pl1-f177.google.com (mail-pl1-f177.google.com [209.85.214.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id DD13412F385 for ; Wed, 1 May 2024 12:19:37 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.214.177 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1714565980; cv=none; b=MUjIGFS9S6r6esCvaKkaHW0Th9yWLW9ho31MgNO3K7I64VqYMfZSbxvnS3Dimh+53FdXaUywcohTRWbxo+OvlMozE7zNhfqXt7RxjUVVfOd7zrFimdDszUIwYypIsljUpL3KR4142DZyK1T9RNBkgR4CippnFQh64cNQVikBARk= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1714565980; c=relaxed/simple; bh=qhqCGi8o9IAINNxfLRxMEmmSPodYgvrNH462+zJ18l4=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=FNVQ5q62HgkYS7010ctgtoL21Uqti76EmE3OgfM8t1Z2xWf4oyB/J/Z+7ld9eL/Ydqte0NLgW11RhEIuEe0jN/Qcs9TNj4T1mJnk4gWYcHRiGuDGmPUjtCqF9YMjTHxDmRL7qbs9DOD4dZDiTOabWgyFpfDzFpSNJDXgZiM2LQM= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=ventanamicro.com; spf=pass smtp.mailfrom=ventanamicro.com; dkim=pass (2048-bit key) header.d=ventanamicro.com header.i=@ventanamicro.com header.b=F7p/5lvl; arc=none smtp.client-ip=209.85.214.177 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=ventanamicro.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=ventanamicro.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=ventanamicro.com header.i=@ventanamicro.com header.b="F7p/5lvl" Received: by mail-pl1-f177.google.com with SMTP id d9443c01a7336-1eab699fcddso52724455ad.0 for ; Wed, 01 May 2024 05:19:37 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1714565977; x=1715170777; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=BG93T+gcNC0mbkbP77au2VNz1Cnxnueu2TjA3uMrqLg=; b=F7p/5lvlKSw310BCiP2ZGUgCUqUi9/kUTkodwgNLpjUPAvLryvL0nn56uSeWJwqWOQ P/sMniwmSk5jxqcMMUm4UreyyKrbigKUDp8zt2opbXDU+0G/Em3Qd3RTUpZkVj++VPbs cQhStm8SnaRGYL6pBr3BjzuMMWB9clmlSujQ+duQl0M+rVDbNEUaQyid+15L44BULXTs jN8hgF5+nAWISyWIhyRLykzKgsOWBTLjcv40vZa072N6PCf0ajJp/jFqf/gMdpdPAJBl 5Br7BWdg8X02Ml1BXig43/0j4D4ld6YiFZ2GaHfdRFlY91gul0AN6nh8dodK4nVld3Mp zoYA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1714565977; x=1715170777; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=BG93T+gcNC0mbkbP77au2VNz1Cnxnueu2TjA3uMrqLg=; b=iQZPBm0OLIxHsVupPHmzni7wkC3i+9VXqsxjF2LKmaK+LnnX2pM91VkC7b7YYrmPG9 g/FoslgeD3ULyN2tM1+fBFmj/YBi2DKQZPrlMXbwP/F70cRJkYxFdF+JVvuCku9IsWEy uGRPOSMdkzU9/C7BfVyzwzoVEQ+EV8kR0DJhibDPRmBsZVn/KDqSHegS3Ia/jycea9oA Dvo0sRDFjA4zgy6uPKBpixBjka2m8VaSlUG3xPy+lPAyl9dwSud3zk6spnQNEy1qrgRo eMaa1MuhtqjvQqJEMAhG515WtavS39b1kByAZhcWzeb/Y5Ztjh0HCMdqGOr87rLAVVMe wFJQ== X-Forwarded-Encrypted: i=1; AJvYcCWOsb8N4fN9wqlNxRGvQwERZeFS2AJ9VSPQqJGiv3NtVuQDaa5x1YwQeb+DjhFjNSzwwu+cxFMunUiU++J0FuJ4YOSe7ZgiCgLqOwjN X-Gm-Message-State: AOJu0Yyt9F10+2faQbuABWN+4TXaDHuxdnS+Dz5OujN8No8nIE+SSQfv rYOUKzQowAZYMoWbp+Mh5X5X68HObTEAMexA0sKi0Tj4ic9tjK9L/8oBGtGY7dE= X-Google-Smtp-Source: AGHT+IGLOIZZtL2TIDSeb766WeGWfcN19Dx07RhHbWbDtJL/7Xyje2/Url/yzqxWmbrfaaNC2lVwOw== X-Received: by 2002:a17:902:eecc:b0:1eb:2988:549d with SMTP id h12-20020a170902eecc00b001eb2988549dmr2035967plb.40.1714565977219; Wed, 01 May 2024 05:19:37 -0700 (PDT) Received: from sunil-pc.Dlink ([106.51.188.106]) by smtp.gmail.com with ESMTPSA id im15-20020a170902bb0f00b001ec8888b22esm1336900plb.65.2024.05.01.05.19.29 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 01 May 2024 05:19:36 -0700 (PDT) From: Sunil V L To: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, linux-acpi@vger.kernel.org, linux-pci@vger.kernel.org, linux-serial@vger.kernel.org, acpica-devel@lists.linux.dev Cc: Catalin Marinas , Will Deacon , Paul Walmsley , Albert Ou , "Rafael J . Wysocki" , Len Brown , Bjorn Helgaas , Anup Patel , Thomas Gleixner , Samuel Holland , Greg Kroah-Hartman , Jiri Slaby , Robert Moore , Conor Dooley , Andrew Jones , Andy Shevchenko , Marc Zyngier , Atish Kumar Patra , Andrei Warkentin , Haibo1 Xu , =?UTF-8?q?Bj=C3=B6rn=20T=C3=B6pel?= , Sunil V L Subject: [PATCH v5 12/17] ACPI: RISC-V: Implement function to add implicit dependencies Date: Wed, 1 May 2024 17:47:37 +0530 Message-Id: <20240501121742.1215792-13-sunilvl@ventanamicro.com> X-Mailer: git-send-email 2.40.1 In-Reply-To: <20240501121742.1215792-1-sunilvl@ventanamicro.com> References: <20240501121742.1215792-1-sunilvl@ventanamicro.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" RISC-V interrupt controllers for wired interrupts are platform devices and hence their driver will be probed late. Also, APLIC which is one such interrupt controller can not be probed early since it needs MSI services. This needs a probing order between the interrupt controller driver and the device drivers. _DEP is typically used to indicate such dependencies. However, the dependency may be already available like GSI mapping. Hence, instead of an explicit _DEP, architecture can find the implicit dependencies and add to the dependency list. For RISC-V, add the dependencies for below use cases. 1) For devices which has IRQ resource, find out the interrupt controller using GSI number map and add the dependency. 2) For PCI host bridges: a) If _PRT indicate PCI link devices, add dependency on the link device. b) If _PRT indicates GSI, find out the interrupt controller using GSI number map and add the dependency. Signed-off-by: Sunil V L --- drivers/acpi/riscv/irq.c | 155 +++++++++++++++++++++++++++++++++++++++ 1 file changed, 155 insertions(+) diff --git a/drivers/acpi/riscv/irq.c b/drivers/acpi/riscv/irq.c index 0473428e8d1e..2878ae48131f 100644 --- a/drivers/acpi/riscv/irq.c +++ b/drivers/acpi/riscv/irq.c @@ -21,6 +21,12 @@ struct riscv_ext_intc_list { struct list_head list; }; =20 +struct acpi_irq_dep_ctx { + int rc; + unsigned int index; + acpi_handle handle; +}; + LIST_HEAD(ext_intc_list); =20 static int irqchip_cmp_func(const void *in0, const void *in1) @@ -62,6 +68,21 @@ static void riscv_acpi_update_gsi_handle(u32 gsi_base, a= cpi_handle handle) acpi_handle_err(handle, "failed to find the GSI mapping entry\n"); } =20 +static acpi_handle riscv_acpi_get_gsi_handle(u32 gsi) +{ + struct riscv_ext_intc_list *ext_intc_element; + struct list_head *i, *tmp; + + list_for_each_safe(i, tmp, &ext_intc_list) { + ext_intc_element =3D list_entry(i, struct riscv_ext_intc_list, list); + if (gsi >=3D ext_intc_element->gsi_base && + gsi < (ext_intc_element->gsi_base + ext_intc_element->nr_irqs)) + return ext_intc_element->handle; + } + + return NULL; +} + int riscv_acpi_get_gsi_info(struct fwnode_handle *fwnode, u32 *gsi_base, u32 *id, u32 *nr_irqs, u32 *nr_idcs) { @@ -172,3 +193,137 @@ void __init riscv_acpi_init_gsi_mapping(void) if (acpi_table_parse_madt(ACPI_MADT_TYPE_APLIC, riscv_acpi_aplic_parse_ma= dt, 0) > 0) acpi_get_devices("RSCV0002", riscv_acpi_create_gsi_map, NULL, NULL); } + +static acpi_status riscv_acpi_irq_get_parent(struct acpi_resource *ares, v= oid *context) +{ + struct acpi_irq_dep_ctx *ctx =3D context; + struct acpi_resource_irq *irq; + struct acpi_resource_extended_irq *eirq; + + switch (ares->type) { + case ACPI_RESOURCE_TYPE_IRQ: + irq =3D &ares->data.irq; + if (ctx->index >=3D irq->interrupt_count) { + ctx->index -=3D irq->interrupt_count; + return AE_OK; + } + ctx->handle =3D riscv_acpi_get_gsi_handle(irq->interrupts[ctx->index]); + return AE_CTRL_TERMINATE; + case ACPI_RESOURCE_TYPE_EXTENDED_IRQ: + eirq =3D &ares->data.extended_irq; + if (eirq->producer_consumer =3D=3D ACPI_PRODUCER) + return AE_OK; + + if (ctx->index >=3D eirq->interrupt_count) { + ctx->index -=3D eirq->interrupt_count; + return AE_OK; + } + + /* Support GSIs only */ + if (eirq->resource_source.string_length) + return AE_OK; + + ctx->handle =3D riscv_acpi_get_gsi_handle(eirq->interrupts[ctx->index]); + return AE_CTRL_TERMINATE; + } + + return AE_OK; +} + +static int riscv_acpi_irq_get_dep(acpi_handle handle, unsigned int index, = acpi_handle *gsi_handle) +{ + struct acpi_irq_dep_ctx ctx =3D {-EINVAL, index, NULL}; + + if (!gsi_handle) + return 0; + + acpi_walk_resources(handle, METHOD_NAME__CRS, riscv_acpi_irq_get_parent, = &ctx); + *gsi_handle =3D ctx.handle; + if (*gsi_handle) + return 1; + + return 0; +} + +static u32 riscv_acpi_add_prt_dep(acpi_handle handle) +{ + struct acpi_buffer buffer =3D { ACPI_ALLOCATE_BUFFER, NULL }; + struct acpi_pci_routing_table *entry; + struct acpi_handle_list dep_devices; + acpi_handle gsi_handle; + acpi_handle link_handle; + acpi_status status; + u32 count =3D 0; + + status =3D acpi_get_irq_routing_table(handle, &buffer); + if (ACPI_FAILURE(status)) { + acpi_handle_err(handle, "failed to get IRQ routing table\n"); + kfree(buffer.pointer); + return 0; + } + + entry =3D buffer.pointer; + while (entry && (entry->length > 0)) { + if (entry->source[0]) { + acpi_get_handle(handle, entry->source, &link_handle); + dep_devices.count =3D 1; + dep_devices.handles =3D kcalloc(1, sizeof(*dep_devices.handles), GFP_KE= RNEL); + if (!dep_devices.handles) { + acpi_handle_err(handle, "failed to allocate memory\n"); + continue; + } + + dep_devices.handles[0] =3D link_handle; + count +=3D acpi_scan_add_dep(handle, &dep_devices); + } else { + gsi_handle =3D riscv_acpi_get_gsi_handle(entry->source_index); + dep_devices.count =3D 1; + dep_devices.handles =3D kcalloc(1, sizeof(*dep_devices.handles), GFP_KE= RNEL); + if (!dep_devices.handles) { + acpi_handle_err(handle, "failed to allocate memory\n"); + continue; + } + + dep_devices.handles[0] =3D gsi_handle; + count +=3D acpi_scan_add_dep(handle, &dep_devices); + } + + entry =3D (struct acpi_pci_routing_table *) + ((unsigned long)entry + entry->length); + } + + kfree(buffer.pointer); + return count; +} + +static u32 riscv_acpi_add_irq_dep(acpi_handle handle) +{ + struct acpi_handle_list dep_devices; + acpi_handle gsi_handle; + u32 count =3D 0; + int i; + + for (i =3D 0; + riscv_acpi_irq_get_dep(handle, i, &gsi_handle); + i++) { + dep_devices.count =3D 1; + dep_devices.handles =3D kcalloc(1, sizeof(*dep_devices.handles), GFP_KER= NEL); + if (!dep_devices.handles) { + acpi_handle_err(handle, "failed to allocate memory\n"); + continue; + } + + dep_devices.handles[0] =3D gsi_handle; + count +=3D acpi_scan_add_dep(handle, &dep_devices); + } + + return count; +} + +u32 arch_acpi_add_auto_dep(acpi_handle handle) +{ + if (acpi_has_method(handle, "_PRT")) + return riscv_acpi_add_prt_dep(handle); + + return riscv_acpi_add_irq_dep(handle); +} --=20 2.40.1 From nobody Wed Dec 17 23:32:07 2025 Received: from mail-pl1-f182.google.com (mail-pl1-f182.google.com [209.85.214.182]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 777E712BEAB for ; Wed, 1 May 2024 12:19:45 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.214.182 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1714565986; cv=none; b=YVOsF08N/ERRKFwHV4iIN4tsPN+qVONjGPzogoJX+Y+74r7BQEFaSMgLJus4/RmqslhG9tDvo4C23bHxeSK2woaN1vXQvrygL3/Ff/6fP9T417rmqLWyTlvLi+gN2dadeATVFFCXvK83bjaIgl4iLV3PnOHW6xM3VkbJj3CIEvU= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1714565986; c=relaxed/simple; bh=ahgw0IfHPDtwuOAghidN1DUqYNQgZUOZv3r84r5UQZg=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=hlq81f6nMYayYS6u4n2lzRe/gGjAGTtr2fDcIfhQdhrWNLCwVhNOk7u9TR7t9q1ElmuFaMimSjonuKwcze1tPXlNmrAJjyXJva+OLVFipxv/bd+N4yuWzl9yHs/SOXDKKRN0DH7s/PgIL32HAlX69kj3+U4e6kwqqzYCvIBUVWY= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=ventanamicro.com; spf=pass smtp.mailfrom=ventanamicro.com; dkim=pass (2048-bit key) header.d=ventanamicro.com header.i=@ventanamicro.com header.b=IaFa2q+Z; arc=none smtp.client-ip=209.85.214.182 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=ventanamicro.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=ventanamicro.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=ventanamicro.com header.i=@ventanamicro.com header.b="IaFa2q+Z" Received: by mail-pl1-f182.google.com with SMTP id d9443c01a7336-1eb0e08bfd2so33076445ad.1 for ; Wed, 01 May 2024 05:19:45 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1714565985; x=1715170785; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=zCPPOR1ckSAJZ1Ubedg9t4QsI9vLkLXGoLfn+9ixWV8=; b=IaFa2q+ZhE7Q1d5K01vyR1jz9On9WXxrLwe1Bgu/VPyfM+IbnUyEwtET6hM0VB6JIp Mo1xe22WoyUCcsNELfXuVhnrvvaOJixMQvRNgaOyFW9jJTCpx9TqriZRHhwYkzZZL/HD iLnBbReDPeNZtyAYmw6YDel/zclSt4qMEcNLm5gDt7BWissE+2qIOppXIpHCg79t/q0P fHgO7G5vO/V/IEVzSAYNOnVNX6BA+qd4aReEER3xh1PQzXqVO14/lOkgwh41OhhZtH2K TPaMrrczEbtcO7NymPAt0TsqdG25/niKIyhf6qZttyEKQ8tmszWESpRqchDFs9vjetUH JL6g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1714565985; x=1715170785; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=zCPPOR1ckSAJZ1Ubedg9t4QsI9vLkLXGoLfn+9ixWV8=; b=FV9lVo8YbKEXKxM8vohws+D1HQuHKJKlcFvCA7V8QPRLvWj07YxSuoyYjnCmvMAgdN RhOPkP3DonYthnWY7nAqcMhcXrFTHRXZAOxNFwZt6w5BugfSmkb1X7a0ppkTJZ+yajRW 4uuoWhyXh/pfJn/l/0ZoMoOVnbARbthVD7itYZHydUDhuWfY2YqgKWyc+98JyYYdwJTD jAVA/3RFJVqQiQHOCOV1qduGci/YZa8BSFfwwwRHFaL2AOREpr+dLvkBKrTfgqXNouLx 149abE3abc3hXmprGeS9rVYlSrUAiAu88OtPEjE1LYaFHiykCdhmwMmGLQ04kzVCaUfE I16A== X-Forwarded-Encrypted: i=1; AJvYcCU/rdSlre6B1rpDFINrwOB23txlf4W/nF6J2VfpwAGFmYGbqzns6eA/6EeeW7ohRUjiHu9/WKZjt+Cj77TrBWfTgdqYZM99kaIvvbLx X-Gm-Message-State: AOJu0Yw/vmwpIy/GLkwNdhGiyvYeiEtIwRqvaZhnGLwwDE3kKvrhZdHh eeBQ6Oh9AGfCNsd31Die5EjuA3NNgMrvgRqAAjjLhQKlO5rKot4Di2xlqncR3jo= X-Google-Smtp-Source: AGHT+IFGyfzN/5kExRpukpNj4St1rBgfudB/pj+gt5M5G+xrt6pZdmPm+vpc0dav1zcXRIM1c0Qiiw== X-Received: by 2002:a17:902:e841:b0:1eb:66b6:930b with SMTP id t1-20020a170902e84100b001eb66b6930bmr2252492plg.55.1714565984846; Wed, 01 May 2024 05:19:44 -0700 (PDT) Received: from sunil-pc.Dlink ([106.51.188.106]) by smtp.gmail.com with ESMTPSA id im15-20020a170902bb0f00b001ec8888b22esm1336900plb.65.2024.05.01.05.19.37 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 01 May 2024 05:19:44 -0700 (PDT) From: Sunil V L To: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, linux-acpi@vger.kernel.org, linux-pci@vger.kernel.org, linux-serial@vger.kernel.org, acpica-devel@lists.linux.dev Cc: Catalin Marinas , Will Deacon , Paul Walmsley , Albert Ou , "Rafael J . Wysocki" , Len Brown , Bjorn Helgaas , Anup Patel , Thomas Gleixner , Samuel Holland , Greg Kroah-Hartman , Jiri Slaby , Robert Moore , Conor Dooley , Andrew Jones , Andy Shevchenko , Marc Zyngier , Atish Kumar Patra , Andrei Warkentin , Haibo1 Xu , =?UTF-8?q?Bj=C3=B6rn=20T=C3=B6pel?= , Sunil V L Subject: [PATCH v5 13/17] irqchip/riscv-intc: Add ACPI support for AIA Date: Wed, 1 May 2024 17:47:38 +0530 Message-Id: <20240501121742.1215792-14-sunilvl@ventanamicro.com> X-Mailer: git-send-email 2.40.1 In-Reply-To: <20240501121742.1215792-1-sunilvl@ventanamicro.com> References: <20240501121742.1215792-1-sunilvl@ventanamicro.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The RINTC subtype structure in MADT also has information about other interrupt controllers. Save this information and provide interfaces to retrieve them when required by corresponding drivers. Signed-off-by: Sunil V L --- arch/riscv/include/asm/irq.h | 35 +++++++++++ drivers/irqchip/irq-riscv-intc.c | 102 ++++++++++++++++++++++++++++++- 2 files changed, 135 insertions(+), 2 deletions(-) diff --git a/arch/riscv/include/asm/irq.h b/arch/riscv/include/asm/irq.h index 44a0b128c602..6bd578b1ffc9 100644 --- a/arch/riscv/include/asm/irq.h +++ b/arch/riscv/include/asm/irq.h @@ -25,9 +25,22 @@ enum riscv_irqchip_type { ACPI_RISCV_IRQCHIP_APLIC =3D 0x03, }; =20 +/* + * The ext_intc_id format is as follows: + * Bits [31:24] APLIC/PLIC ID + * Bits [15:0] APLIC IDC ID / PLIC S-Mode Context ID for this hart + */ +#define APLIC_PLIC_ID(x) ((x) >> 24) +#define IDC_CONTEXT_ID(x) ((x) & 0x0000ffff) + int riscv_acpi_get_gsi_info(struct fwnode_handle *fwnode, u32 *gsi_base, u32 *id, u32 *nr_irqs, u32 *nr_idcs); struct fwnode_handle *riscv_acpi_get_gsi_domain_id(u32 gsi); +int __init acpi_get_intc_index_hartid(u32 index, unsigned long *hartid); +int acpi_get_ext_intc_parent_hartid(u8 id, u32 idx, unsigned long *hartid); +void acpi_get_plic_nr_contexts(u8 id, int *nr_contexts); +int acpi_get_plic_context(u8 id, u32 idx, int *context_id); +int __init acpi_get_imsic_mmio_info(u32 index, struct resource *res); =20 #else static inline int riscv_acpi_get_gsi_info(struct fwnode_handle *fwnode, u3= 2 *gsi_base, @@ -36,6 +49,28 @@ static inline int riscv_acpi_get_gsi_info(struct fwnode_= handle *fwnode, u32 *gsi return 0; } =20 +static inline int __init acpi_get_intc_index_hartid(u32 index, unsigned lo= ng *hartid) +{ + return -EINVAL; +} + +static inline int acpi_get_ext_intc_parent_hartid(u8 id, u32 idx, unsigned= long *hartid) +{ + return -EINVAL; +} + +static inline void acpi_get_plic_nr_contexts(u8 id, int *nr_contexts) { } + +static inline int acpi_get_plic_context(u8 id, u32 idx, int *context_id) +{ + return -EINVAL; +} + +static inline int __init acpi_get_imsic_mmio_info(u32 index, struct resour= ce *res) +{ + return 0; +} + #endif /* CONFIG_ACPI */ =20 #endif /* _ASM_RISCV_IRQ_H */ diff --git a/drivers/irqchip/irq-riscv-intc.c b/drivers/irqchip/irq-riscv-i= ntc.c index 9e71c4428814..af7a2f78f0ee 100644 --- a/drivers/irqchip/irq-riscv-intc.c +++ b/drivers/irqchip/irq-riscv-intc.c @@ -249,14 +249,105 @@ IRQCHIP_DECLARE(riscv, "riscv,cpu-intc", riscv_intc_= init); IRQCHIP_DECLARE(andes, "andestech,cpu-intc", riscv_intc_init); =20 #ifdef CONFIG_ACPI +struct rintc_data { + u32 ext_intc_id; + unsigned long hart_id; + u64 imsic_addr; + u32 imsic_size; +}; + +static u32 nr_rintc; +static struct rintc_data *rintc_acpi_data[NR_CPUS]; + +int acpi_get_intc_index_hartid(u32 index, unsigned long *hartid) +{ + if (index >=3D nr_rintc) + return -1; + + *hartid =3D rintc_acpi_data[index]->hart_id; + return 0; +} + +int acpi_get_ext_intc_parent_hartid(u8 id, u32 idx, unsigned long *hartid) +{ + int i, j =3D 0; + + for (i =3D 0; i < nr_rintc; i++) { + if (APLIC_PLIC_ID(rintc_acpi_data[i]->ext_intc_id) =3D=3D id) { + if (idx =3D=3D j) { + *hartid =3D rintc_acpi_data[i]->hart_id; + return 0; + } + j++; + } + } + + return -1; +} + +void acpi_get_plic_nr_contexts(u8 id, int *nr_contexts) +{ + int i, j =3D 0; + + for (i =3D 0; i < nr_rintc; i++) { + if (APLIC_PLIC_ID(rintc_acpi_data[i]->ext_intc_id) =3D=3D id) + j++; + } + + *nr_contexts =3D j; +} + +int acpi_get_plic_context(u8 id, u32 idx, int *context_id) +{ + int i, j =3D 0; + + for (i =3D 0; i < nr_rintc; i++) { + if (APLIC_PLIC_ID(rintc_acpi_data[i]->ext_intc_id) =3D=3D id) { + if (idx =3D=3D j) { + *context_id =3D IDC_CONTEXT_ID(rintc_acpi_data[i]->ext_intc_id); + return 0; + } + + j++; + } + } + + return -1; +} + +int acpi_get_imsic_mmio_info(u32 index, struct resource *res) +{ + if (index >=3D nr_rintc) + return -1; + + res->start =3D rintc_acpi_data[index]->imsic_addr; + res->end =3D res->start + rintc_acpi_data[index]->imsic_size - 1; + res->flags =3D IORESOURCE_MEM; + return 0; +} + +static struct fwnode_handle *ext_entc_get_gsi_domain_id(u32 gsi) +{ + return riscv_acpi_get_gsi_domain_id(gsi); +} =20 static int __init riscv_intc_acpi_init(union acpi_subtable_headers *header, const unsigned long end) { - struct fwnode_handle *fn; struct acpi_madt_rintc *rintc; + struct fwnode_handle *fn; + int rc; =20 rintc =3D (struct acpi_madt_rintc *)header; + rintc_acpi_data[nr_rintc] =3D kzalloc(sizeof(*rintc_acpi_data[0]), GFP_KE= RNEL); + if (!rintc_acpi_data[nr_rintc]) + return -ENOMEM; + + rintc_acpi_data[nr_rintc]->ext_intc_id =3D rintc->ext_intc_id; + rintc_acpi_data[nr_rintc]->hart_id =3D rintc->hart_id; + rintc_acpi_data[nr_rintc]->imsic_addr =3D rintc->imsic_addr; + rintc_acpi_data[nr_rintc]->imsic_size =3D rintc->imsic_size; + nr_rintc++; =20 /* * The ACPI MADT will have one INTC for each CPU (or HART) @@ -273,7 +364,14 @@ static int __init riscv_intc_acpi_init(union acpi_subt= able_headers *header, return -ENOMEM; } =20 - return riscv_intc_init_common(fn, &riscv_intc_chip); + rc =3D riscv_intc_init_common(fn, &riscv_intc_chip); + if (rc) { + irq_domain_free_fwnode(fn); + return rc; + } + + acpi_set_irq_model(ACPI_IRQ_MODEL_RINTC, ext_entc_get_gsi_domain_id); + return 0; } =20 IRQCHIP_ACPI_DECLARE(riscv_intc, ACPI_MADT_TYPE_RINTC, NULL, --=20 2.40.1 From nobody Wed Dec 17 23:32:07 2025 Received: from mail-pg1-f181.google.com (mail-pg1-f181.google.com [209.85.215.181]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 2A7C712C462 for ; Wed, 1 May 2024 12:19:53 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.215.181 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1714565994; cv=none; b=oBI9tnHOa9hnRK1bKQ5hZOYVaAfah6tdcmbG5YzvyDcmd50Vjbt+xujkM+GjBmUhaMknbF8jrPT5CCwBsJaoLlATOIQzmAXVV7Q+E/VHekeeJaa1suTgMTan/Ww+riu09Xr1IsCGMRcgdwvGJ43HajDdyQjVDxqBqe8SK3jnpoU= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1714565994; c=relaxed/simple; bh=PIgRKdcBOY6xqaSxqFNwNiexk2/lPC9DEDH/ofVigro=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=JfnXGQCo7PGxPUr+a9k9+ymChskk7e2CrWQBvlnWUKUBAPsesVQ/kiFRzIVQ63U/Tf3lOLgmz9oRsC0Dly1XbKThrYVesTV8PQiDwSOfad+42uC7Z3cfGxdyhtzRd0V+xea75Txn9TyfdU8AscpNfUHDLdfivT+TUAoO0/8UeRM= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=ventanamicro.com; spf=pass smtp.mailfrom=ventanamicro.com; dkim=pass (2048-bit key) header.d=ventanamicro.com header.i=@ventanamicro.com header.b=BL/JPOXw; arc=none smtp.client-ip=209.85.215.181 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=ventanamicro.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=ventanamicro.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=ventanamicro.com header.i=@ventanamicro.com header.b="BL/JPOXw" Received: by mail-pg1-f181.google.com with SMTP id 41be03b00d2f7-5bdbe2de25fso5112245a12.3 for ; Wed, 01 May 2024 05:19:53 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1714565992; x=1715170792; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=EXYTa+lyps4skrflQeX/iviyMZf5mebO38NcRgvfQY0=; b=BL/JPOXwM7EIgrTtHZKdy4Ahg8WMe7UXRuq56+sDiDDUzbjcQHt9gp9ZvDNemTOr4c AC8XbOdKpsY7/Tjn0drb9YNXIg/aae2i29z6Ko4A62Ok3cHdpWrEG04V4oHGsalwX5ek LPZWvRClboZ2S7m+zu9azgp4fpSdRC30gDTFRWBC86ICDY4TzH7w882SEfu3Kg41MCvD SKreMrmBAEkDU1RtOeYQBzT6XSh2fhuXMz5buJ0sdDzJTbQNm6g14X2CS3fWRFSHSnFp X+2az7OrugHMIx2wBj131FbmyNva/qNB5KeFGAKkTsKE1KnQ0UR0SL7nLREgKqrCaHTk wYSw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1714565992; x=1715170792; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=EXYTa+lyps4skrflQeX/iviyMZf5mebO38NcRgvfQY0=; b=p72yEYmWozkIxrqxbBytuRbYTFh05Cvj/jsKrewkDQNUVqSgaJbA9wPqI2njK5cM1T 49zbz06h4SjCx2DIp4SBla/qk48v0t5H3vgRozc71SAcXF36ww6Ptb3iUQyeRj1f4O3o bGd5putDMbvzrwcU7IHvCeVnLch3RCNi9Ea26QBQVkb03LghnVscvLrnBAkaXYHXuFK1 ReQS75a4cE1nl4zvJHiaQX3gE581QAnvN4lO3m2zLvvB43KXYjuI38t647qOT7q+yTUI yZRun+TNHLc8/kyY9FOq1o3yhsGsVRjNDrz+GfDyppBbjKOIoy6wHnrkP0UWCm++Ezdq TvzQ== X-Forwarded-Encrypted: i=1; AJvYcCUoQuqwcwaeSOGo9UCuLhWEr3UrREjMhHMqlEXzEwvkUnEQfZIYzK1rmSQ2pY4ux8r7XSCqq5gdDTSrAJXDo7x0qwPJScJECAKpkyxQ X-Gm-Message-State: AOJu0Yxq0ILUCnVQKgXwCm6IXviDjaUHLCkRCu6+XxAqX49BSLuhmeAp biXrQTuGAROc17X/gY2bx3t6L03QRPFDWJV6iBPH8/L2G0+r4mp1AUmbxn93/Tw= X-Google-Smtp-Source: AGHT+IEYbbDg76A7S1g52ZK/aOehSAGVOKJv35qqCM5C5Vw6MRuD5Sdk6WDNaIS+1kkWSucq//am/w== X-Received: by 2002:a17:90b:1c0b:b0:2b3:2a3b:e4a0 with SMTP id oc11-20020a17090b1c0b00b002b32a3be4a0mr1170711pjb.32.1714565992555; Wed, 01 May 2024 05:19:52 -0700 (PDT) Received: from sunil-pc.Dlink ([106.51.188.106]) by smtp.gmail.com with ESMTPSA id im15-20020a170902bb0f00b001ec8888b22esm1336900plb.65.2024.05.01.05.19.45 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 01 May 2024 05:19:52 -0700 (PDT) From: Sunil V L To: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, linux-acpi@vger.kernel.org, linux-pci@vger.kernel.org, linux-serial@vger.kernel.org, acpica-devel@lists.linux.dev Cc: Catalin Marinas , Will Deacon , Paul Walmsley , Albert Ou , "Rafael J . Wysocki" , Len Brown , Bjorn Helgaas , Anup Patel , Thomas Gleixner , Samuel Holland , Greg Kroah-Hartman , Jiri Slaby , Robert Moore , Conor Dooley , Andrew Jones , Andy Shevchenko , Marc Zyngier , Atish Kumar Patra , Andrei Warkentin , Haibo1 Xu , =?UTF-8?q?Bj=C3=B6rn=20T=C3=B6pel?= , Sunil V L Subject: [PATCH v5 14/17] irqchip/riscv-imsic: Add ACPI support Date: Wed, 1 May 2024 17:47:39 +0530 Message-Id: <20240501121742.1215792-15-sunilvl@ventanamicro.com> X-Mailer: git-send-email 2.40.1 In-Reply-To: <20240501121742.1215792-1-sunilvl@ventanamicro.com> References: <20240501121742.1215792-1-sunilvl@ventanamicro.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" RISC-V IMSIC interrupt controller provides IPI and MSI support. Currently, DT based drivers setup the IPI feature early during boot but defer setting up the MSI functionality. However, in ACPI systems, ACPI, both IPI and MSI features need to be initialized early itself. Signed-off-by: Sunil V L --- drivers/irqchip/irq-riscv-imsic-early.c | 52 +++++++++- drivers/irqchip/irq-riscv-imsic-platform.c | 32 ++++-- drivers/irqchip/irq-riscv-imsic-state.c | 115 ++++++++++----------- drivers/irqchip/irq-riscv-imsic-state.h | 2 +- include/linux/irqchip/riscv-imsic.h | 10 ++ 5 files changed, 144 insertions(+), 67 deletions(-) diff --git a/drivers/irqchip/irq-riscv-imsic-early.c b/drivers/irqchip/irq-= riscv-imsic-early.c index 886418ec06cb..d8161243791d 100644 --- a/drivers/irqchip/irq-riscv-imsic-early.c +++ b/drivers/irqchip/irq-riscv-imsic-early.c @@ -5,13 +5,16 @@ */ =20 #define pr_fmt(fmt) "riscv-imsic: " fmt +#include #include #include #include #include #include #include +#include #include +#include #include #include =20 @@ -182,7 +185,7 @@ static int __init imsic_early_dt_init(struct device_nod= e *node, struct device_no int rc; =20 /* Setup IMSIC state */ - rc =3D imsic_setup_state(fwnode); + rc =3D imsic_setup_state(fwnode, NULL); if (rc) { pr_err("%pfwP: failed to setup state (error %d)\n", fwnode, rc); return rc; @@ -199,3 +202,50 @@ static int __init imsic_early_dt_init(struct device_no= de *node, struct device_no } =20 IRQCHIP_DECLARE(riscv_imsic, "riscv,imsics", imsic_early_dt_init); + +#ifdef CONFIG_ACPI + +static struct fwnode_handle *imsic_acpi_fwnode; + +struct fwnode_handle *imsic_acpi_get_fwnode(struct device *dev) +{ + return imsic_acpi_fwnode; +} + +static int __init imsic_early_acpi_init(union acpi_subtable_headers *heade= r, + const unsigned long end) +{ + struct acpi_madt_imsic *imsic =3D (struct acpi_madt_imsic *)header; + int rc; + + imsic_acpi_fwnode =3D irq_domain_alloc_named_fwnode("imsic"); + if (!imsic_acpi_fwnode) { + pr_err("unable to allocate IMSIC FW node\n"); + return -ENOMEM; + } + + /* Setup IMSIC state */ + rc =3D imsic_setup_state(imsic_acpi_fwnode, (void *)imsic); + if (rc) { + pr_err("%pfwP: failed to setup state (error %d)\n", imsic_acpi_fwnode, r= c); + return rc; + } + + /* Do early setup of IMSIC state and IPIs */ + rc =3D imsic_early_probe(imsic_acpi_fwnode); + if (rc) + return rc; + + rc =3D imsic_platform_acpi_probe(imsic_acpi_fwnode); + +#ifdef CONFIG_PCI + if (!rc) + pci_msi_register_fwnode_provider(&imsic_acpi_get_fwnode); +#endif + + return rc; +} + +IRQCHIP_ACPI_DECLARE(riscv_imsic, ACPI_MADT_TYPE_IMSIC, NULL, + 1, imsic_early_acpi_init); +#endif diff --git a/drivers/irqchip/irq-riscv-imsic-platform.c b/drivers/irqchip/i= rq-riscv-imsic-platform.c index 11723a763c10..64905e6f52d7 100644 --- a/drivers/irqchip/irq-riscv-imsic-platform.c +++ b/drivers/irqchip/irq-riscv-imsic-platform.c @@ -5,6 +5,7 @@ */ =20 #define pr_fmt(fmt) "riscv-imsic: " fmt +#include #include #include #include @@ -348,18 +349,37 @@ int imsic_irqdomain_init(void) return 0; } =20 -static int imsic_platform_probe(struct platform_device *pdev) +static int imsic_platform_probe_common(struct fwnode_handle *fwnode) { - struct device *dev =3D &pdev->dev; - - if (imsic && imsic->fwnode !=3D dev->fwnode) { - dev_err(dev, "fwnode mismatch\n"); + if (imsic && imsic->fwnode !=3D fwnode) { + pr_err("%pfwP: fwnode mismatch\n", fwnode); return -ENODEV; } =20 return imsic_irqdomain_init(); } =20 +static int imsic_platform_dt_probe(struct platform_device *pdev) +{ + return imsic_platform_probe_common(pdev->dev.fwnode); +} + +#ifdef CONFIG_ACPI + +/* + * On ACPI based systems, PCI enumeration happens early during boot in + * acpi_scan_init(). PCI enumeration expects MSI domain setup before + * it calls pci_set_msi_domain(). Hence, unlike in DT where + * imsic-platform drive probe happens late during boot, ACPI based + * systems need to setup the MSI domain early. + */ +int imsic_platform_acpi_probe(struct fwnode_handle *fwnode) +{ + return imsic_platform_probe_common(fwnode); +} + +#endif + static const struct of_device_id imsic_platform_match[] =3D { { .compatible =3D "riscv,imsics" }, {} @@ -370,6 +390,6 @@ static struct platform_driver imsic_platform_driver =3D= { .name =3D "riscv-imsic", .of_match_table =3D imsic_platform_match, }, - .probe =3D imsic_platform_probe, + .probe =3D imsic_platform_dt_probe, }; builtin_platform_driver(imsic_platform_driver); diff --git a/drivers/irqchip/irq-riscv-imsic-state.c b/drivers/irqchip/irq-= riscv-imsic-state.c index 5479f872e62b..608b87dd0784 100644 --- a/drivers/irqchip/irq-riscv-imsic-state.c +++ b/drivers/irqchip/irq-riscv-imsic-state.c @@ -5,6 +5,7 @@ */ =20 #define pr_fmt(fmt) "riscv-imsic: " fmt +#include #include #include #include @@ -516,12 +517,8 @@ static int __init imsic_get_parent_hartid(struct fwnod= e_handle *fwnode, struct of_phandle_args parent; int rc; =20 - /* - * Currently, only OF fwnode is supported so extend this - * function for ACPI support. - */ if (!is_of_node(fwnode)) - return -EINVAL; + return acpi_get_intc_index_hartid(index, hartid); =20 rc =3D of_irq_parse_one(to_of_node(fwnode), index, &parent); if (rc) @@ -540,12 +537,8 @@ static int __init imsic_get_parent_hartid(struct fwnod= e_handle *fwnode, static int __init imsic_get_mmio_resource(struct fwnode_handle *fwnode, u32 index, struct resource *res) { - /* - * Currently, only OF fwnode is supported so extend this - * function for ACPI support. - */ if (!is_of_node(fwnode)) - return -EINVAL; + return acpi_get_imsic_mmio_info(index, res); =20 return of_address_to_resource(to_of_node(fwnode), index, res); } @@ -553,20 +546,15 @@ static int __init imsic_get_mmio_resource(struct fwno= de_handle *fwnode, static int __init imsic_parse_fwnode(struct fwnode_handle *fwnode, struct imsic_global_config *global, u32 *nr_parent_irqs, - u32 *nr_mmios) + u32 *nr_mmios, + void *opaque) { + struct acpi_madt_imsic *imsic =3D (struct acpi_madt_imsic *)opaque; unsigned long hartid; struct resource res; int rc; u32 i; =20 - /* - * Currently, only OF fwnode is supported so extend this - * function for ACPI support. - */ - if (!is_of_node(fwnode)) - return -EINVAL; - *nr_parent_irqs =3D 0; *nr_mmios =3D 0; =20 @@ -578,51 +566,60 @@ static int __init imsic_parse_fwnode(struct fwnode_ha= ndle *fwnode, return -EINVAL; } =20 - /* Find number of guest index bits in MSI address */ - rc =3D of_property_read_u32(to_of_node(fwnode), "riscv,guest-index-bits", - &global->guest_index_bits); - if (rc) - global->guest_index_bits =3D 0; + if (is_of_node(fwnode)) { + /* Find number of guest index bits in MSI address */ + rc =3D of_property_read_u32(to_of_node(fwnode), "riscv,guest-index-bits", + &global->guest_index_bits); + if (rc) + global->guest_index_bits =3D 0; =20 - /* Find number of HART index bits */ - rc =3D of_property_read_u32(to_of_node(fwnode), "riscv,hart-index-bits", - &global->hart_index_bits); - if (rc) { - /* Assume default value */ - global->hart_index_bits =3D __fls(*nr_parent_irqs); - if (BIT(global->hart_index_bits) < *nr_parent_irqs) - global->hart_index_bits++; - } + /* Find number of HART index bits */ + rc =3D of_property_read_u32(to_of_node(fwnode), "riscv,hart-index-bits", + &global->hart_index_bits); + if (rc) { + /* Assume default value */ + global->hart_index_bits =3D __fls(*nr_parent_irqs); + if (BIT(global->hart_index_bits) < *nr_parent_irqs) + global->hart_index_bits++; + } =20 - /* Find number of group index bits */ - rc =3D of_property_read_u32(to_of_node(fwnode), "riscv,group-index-bits", - &global->group_index_bits); - if (rc) - global->group_index_bits =3D 0; + /* Find number of group index bits */ + rc =3D of_property_read_u32(to_of_node(fwnode), "riscv,group-index-bits", + &global->group_index_bits); + if (rc) + global->group_index_bits =3D 0; =20 - /* - * Find first bit position of group index. - * If not specified assumed the default APLIC-IMSIC configuration. - */ - rc =3D of_property_read_u32(to_of_node(fwnode), "riscv,group-index-shift", - &global->group_index_shift); - if (rc) - global->group_index_shift =3D IMSIC_MMIO_PAGE_SHIFT * 2; + /* + * Find first bit position of group index. + * If not specified assumed the default APLIC-IMSIC configuration. + */ + rc =3D of_property_read_u32(to_of_node(fwnode), "riscv,group-index-shift= ", + &global->group_index_shift); + if (rc) + global->group_index_shift =3D IMSIC_MMIO_PAGE_SHIFT * 2; + + /* Find number of interrupt identities */ + rc =3D of_property_read_u32(to_of_node(fwnode), "riscv,num-ids", + &global->nr_ids); + if (rc) { + pr_err("%pfwP: number of interrupt identities not found\n", fwnode); + return rc; + } =20 - /* Find number of interrupt identities */ - rc =3D of_property_read_u32(to_of_node(fwnode), "riscv,num-ids", - &global->nr_ids); - if (rc) { - pr_err("%pfwP: number of interrupt identities not found\n", fwnode); - return rc; + /* Find number of guest interrupt identities */ + rc =3D of_property_read_u32(to_of_node(fwnode), "riscv,num-guest-ids", + &global->nr_guest_ids); + if (rc) + global->nr_guest_ids =3D global->nr_ids; + } else { + global->guest_index_bits =3D imsic->guest_index_bits; + global->hart_index_bits =3D imsic->hart_index_bits; + global->group_index_bits =3D imsic->group_index_bits; + global->group_index_shift =3D imsic->group_index_shift; + global->nr_ids =3D imsic->num_ids; + global->nr_guest_ids =3D imsic->num_guest_ids; } =20 - /* Find number of guest interrupt identities */ - rc =3D of_property_read_u32(to_of_node(fwnode), "riscv,num-guest-ids", - &global->nr_guest_ids); - if (rc) - global->nr_guest_ids =3D global->nr_ids; - /* Sanity check guest index bits */ i =3D BITS_PER_LONG - IMSIC_MMIO_PAGE_SHIFT; if (i < global->guest_index_bits) { @@ -688,7 +685,7 @@ static int __init imsic_parse_fwnode(struct fwnode_hand= le *fwnode, return 0; } =20 -int __init imsic_setup_state(struct fwnode_handle *fwnode) +int __init imsic_setup_state(struct fwnode_handle *fwnode, void *opaque) { u32 i, j, index, nr_parent_irqs, nr_mmios, nr_handlers =3D 0; struct imsic_global_config *global; @@ -729,7 +726,7 @@ int __init imsic_setup_state(struct fwnode_handle *fwno= de) } =20 /* Parse IMSIC fwnode */ - rc =3D imsic_parse_fwnode(fwnode, global, &nr_parent_irqs, &nr_mmios); + rc =3D imsic_parse_fwnode(fwnode, global, &nr_parent_irqs, &nr_mmios, opa= que); if (rc) goto out_free_local; =20 diff --git a/drivers/irqchip/irq-riscv-imsic-state.h b/drivers/irqchip/irq-= riscv-imsic-state.h index 5ae2f69b035b..391e44280827 100644 --- a/drivers/irqchip/irq-riscv-imsic-state.h +++ b/drivers/irqchip/irq-riscv-imsic-state.h @@ -102,7 +102,7 @@ void imsic_vector_debug_show_summary(struct seq_file *m= , int ind); =20 void imsic_state_online(void); void imsic_state_offline(void); -int imsic_setup_state(struct fwnode_handle *fwnode); +int imsic_setup_state(struct fwnode_handle *fwnode, void *opaque); int imsic_irqdomain_init(void); =20 #endif diff --git a/include/linux/irqchip/riscv-imsic.h b/include/linux/irqchip/ri= scv-imsic.h index faf0b800b1b0..e08680b1932b 100644 --- a/include/linux/irqchip/riscv-imsic.h +++ b/include/linux/irqchip/riscv-imsic.h @@ -84,4 +84,14 @@ static inline const struct imsic_global_config *imsic_ge= t_global_config(void) =20 #endif =20 +#ifdef CONFIG_ACPI +int imsic_platform_acpi_probe(struct fwnode_handle *fwnode); +struct fwnode_handle *imsic_acpi_get_fwnode(struct device *dev); +#else +static inline struct fwnode_handle *imsic_acpi_get_fwnode(struct device *d= ev) +{ + return NULL; +} +#endif + #endif --=20 2.40.1 From nobody Wed Dec 17 23:32:07 2025 Received: from mail-pl1-f177.google.com (mail-pl1-f177.google.com [209.85.214.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B50D212BF2D for ; Wed, 1 May 2024 12:20:00 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.214.177 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1714566002; cv=none; b=TRJBWOQTNmwwNd97LBD3qTDAHZ2xTKYZTE6Z/v0vH6ziBhWpyiP1gA/JmEdUfX2AqLZ2v+iy9LyPuBTeCNysqaJJiXaXfYYi6WU2Gby13OKFMZTJcPyCUNg0bq/vFU/cJ1vz7PhKmZTyJcX/T1OGZhHLqlhzkTa3FUd3MDjcYYc= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1714566002; c=relaxed/simple; bh=Ctl8fjOGCMekGTE69fIp5aXSPpH0EKsLQAWGYrwV+bE=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=IPNFfUbfQXyoasTIh8LFEk5Ac3zgBL/f5/dTMTA6Jqo2uXuYiWip7Yaiv358BIWmHKbz4BCnW0Bht/Od0OujeMSHiJ4z7kP+Ai5OXafRnfOpjXz7BYVUNWcrAPrTN+fnNuV92nCSOwNYCJZT40HI3cyDY6JYkE5/47OK1JoLHoo= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=ventanamicro.com; spf=pass smtp.mailfrom=ventanamicro.com; dkim=pass (2048-bit key) header.d=ventanamicro.com header.i=@ventanamicro.com header.b=Mx6D60oz; arc=none smtp.client-ip=209.85.214.177 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=ventanamicro.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=ventanamicro.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=ventanamicro.com header.i=@ventanamicro.com header.b="Mx6D60oz" Received: by mail-pl1-f177.google.com with SMTP id d9443c01a7336-1e651a9f3ffso33948465ad.1 for ; Wed, 01 May 2024 05:20:00 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1714566000; x=1715170800; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=YKprQ9DjgmWeNOp2jgUX6DT/fQdt5/GgPVbDil8wt68=; b=Mx6D60ozBCEMv0lOoFeLktbUdwnBFtOgnA2ygphrCXXQljGtOKEvFaFUOuCcjbTjHJ iowu6qury78Y6uvqUVojiWdoiF+2Vv7xjB4DPk83V1Qjp7tHiYdNvKzJuecj4SdWuAxu PKR7ggUt6QjuHNUtn21T4jFCkQbDPlwKiEkOUpYs5M7TzcDCdxoqSalf/Ue/MwMeqZ1/ pDB6jRMYKJ4a3H61HR7tvRSNh2rMAbN5mVnDk3euksBv6WiRAOJq50rUqYTRXAd+Nw4a RUsS2THk/jsAjZQ9U5QvQ5XUQMQgtLX/LFOdW2NYaWoCXBIfg18aHE89q1/OHRfKVVuf pEdA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1714566000; x=1715170800; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=YKprQ9DjgmWeNOp2jgUX6DT/fQdt5/GgPVbDil8wt68=; b=YGo3m3/3YkYjzO9/KrcLFvljYAqJkiR5ERunApHFNIqTFZq8rswLGbaHc/Od94RYXi 8QXYlwn0RlRHCu/m8icA+S7X+wkUyX8FBMXLWDedxC8ILC3kiTuZcizGMuE0TuadhQ5q WDJvRTeyxFJH3u77KniRp02egjn6oMoM/7zwz3IsUbUgQcKAxrlLlX5o8o4fEEANPFy+ wpjreLiVCmPwWprPhQH1kmIDMkzqXJtjCAuG8+Nye0UxrWSRNZMtk0dIzFuam6ugmE5N +vf92kSHcfLJpN9faTgXA8npUmDFDfDAszMcLAllPB4yYxkrCFJGaI2R1w4/59bxhD+z Q6TQ== X-Forwarded-Encrypted: i=1; AJvYcCWnakpLKK//cdzEnw2hnEMiXL+GKAU5nuSwc/POCGNcnJyQpC+uHu/1Hhh9l1fGry6tvyH5U/o9lWui2K1J/n27UICCAajeTnkVKsEV X-Gm-Message-State: AOJu0Yy+30zYB4p4JjTgqLnul+d3m9mcqRsZ0A4O9sg3CXRCZIpW19z6 Defr2rXPS80gK/VQvinle7jTZJIE8UGUVGqJXI5JeXKv3ErerwqONybqEi1LZ8U= X-Google-Smtp-Source: AGHT+IHXX5ILEyglT/Py3DGUVj43d4poupz49yi1BZblVtQazhBuHxJlZGQemov9OMPe6qk3xCXV3Q== X-Received: by 2002:a17:902:e841:b0:1eb:156f:8d01 with SMTP id t1-20020a170902e84100b001eb156f8d01mr2061754plg.40.1714566000196; Wed, 01 May 2024 05:20:00 -0700 (PDT) Received: from sunil-pc.Dlink ([106.51.188.106]) by smtp.gmail.com with ESMTPSA id im15-20020a170902bb0f00b001ec8888b22esm1336900plb.65.2024.05.01.05.19.52 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 01 May 2024 05:19:59 -0700 (PDT) From: Sunil V L To: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, linux-acpi@vger.kernel.org, linux-pci@vger.kernel.org, linux-serial@vger.kernel.org, acpica-devel@lists.linux.dev Cc: Catalin Marinas , Will Deacon , Paul Walmsley , Albert Ou , "Rafael J . Wysocki" , Len Brown , Bjorn Helgaas , Anup Patel , Thomas Gleixner , Samuel Holland , Greg Kroah-Hartman , Jiri Slaby , Robert Moore , Conor Dooley , Andrew Jones , Andy Shevchenko , Marc Zyngier , Atish Kumar Patra , Andrei Warkentin , Haibo1 Xu , =?UTF-8?q?Bj=C3=B6rn=20T=C3=B6pel?= , Sunil V L Subject: [PATCH v5 15/17] irqchip/riscv-aplic: Add ACPI support Date: Wed, 1 May 2024 17:47:40 +0530 Message-Id: <20240501121742.1215792-16-sunilvl@ventanamicro.com> X-Mailer: git-send-email 2.40.1 In-Reply-To: <20240501121742.1215792-1-sunilvl@ventanamicro.com> References: <20240501121742.1215792-1-sunilvl@ventanamicro.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add ACPI support in APLIC drivers. Use the mapping created early during boot to get the details about the APLIC. Signed-off-by: Sunil V L --- drivers/irqchip/irq-riscv-aplic-direct.c | 20 ++++--- drivers/irqchip/irq-riscv-aplic-main.c | 70 ++++++++++++++++-------- drivers/irqchip/irq-riscv-aplic-main.h | 1 + drivers/irqchip/irq-riscv-aplic-msi.c | 9 ++- 4 files changed, 67 insertions(+), 33 deletions(-) diff --git a/drivers/irqchip/irq-riscv-aplic-direct.c b/drivers/irqchip/irq= -riscv-aplic-direct.c index 4a3ffe856d6c..e24c2d3c78f6 100644 --- a/drivers/irqchip/irq-riscv-aplic-direct.c +++ b/drivers/irqchip/irq-riscv-aplic-direct.c @@ -4,6 +4,7 @@ * Copyright (C) 2022 Ventana Micro Systems Inc. */ =20 +#include #include #include #include @@ -189,17 +190,20 @@ static int aplic_direct_starting_cpu(unsigned int cpu) } =20 static int aplic_direct_parse_parent_hwirq(struct device *dev, u32 index, - u32 *parent_hwirq, unsigned long *parent_hartid) + u32 *parent_hwirq, unsigned long *parent_hartid, + struct aplic_priv *priv) { struct of_phandle_args parent; int rc; =20 - /* - * Currently, only OF fwnode is supported so extend this - * function for ACPI support. - */ - if (!is_of_node(dev->fwnode)) - return -EINVAL; + if (!is_of_node(dev->fwnode)) { + rc =3D acpi_get_ext_intc_parent_hartid(priv->id, index, parent_hartid); + if (rc) + return rc; + + *parent_hwirq =3D RV_IRQ_EXT; + return 0; + } =20 rc =3D of_irq_parse_one(to_of_node(dev->fwnode), index, &parent); if (rc) @@ -237,7 +241,7 @@ int aplic_direct_setup(struct device *dev, void __iomem= *regs) /* Setup per-CPU IDC and target CPU mask */ current_cpu =3D get_cpu(); for (i =3D 0; i < priv->nr_idcs; i++) { - rc =3D aplic_direct_parse_parent_hwirq(dev, i, &hwirq, &hartid); + rc =3D aplic_direct_parse_parent_hwirq(dev, i, &hwirq, &hartid, priv); if (rc) { dev_warn(dev, "parent irq for IDC%d not found\n", i); continue; diff --git a/drivers/irqchip/irq-riscv-aplic-main.c b/drivers/irqchip/irq-r= iscv-aplic-main.c index 774a0c97fdab..c1fd328ddf7d 100644 --- a/drivers/irqchip/irq-riscv-aplic-main.c +++ b/drivers/irqchip/irq-riscv-aplic-main.c @@ -4,8 +4,10 @@ * Copyright (C) 2022 Ventana Micro Systems Inc. */ =20 +#include #include #include +#include #include #include #include @@ -125,39 +127,50 @@ static void aplic_init_hw_irqs(struct aplic_priv *pri= v) writel(0, priv->regs + APLIC_DOMAINCFG); } =20 +#ifdef CONFIG_ACPI +static const struct acpi_device_id aplic_acpi_match[] =3D { + { "RSCV0002", 0 }, + {} +}; +MODULE_DEVICE_TABLE(acpi, aplic_acpi_match); + +#endif + int aplic_setup_priv(struct aplic_priv *priv, struct device *dev, void __i= omem *regs) { struct of_phandle_args parent; int rc; =20 - /* - * Currently, only OF fwnode is supported so extend this - * function for ACPI support. - */ - if (!is_of_node(dev->fwnode)) - return -EINVAL; - /* Save device pointer and register base */ priv->dev =3D dev; priv->regs =3D regs; =20 - /* Find out number of interrupt sources */ - rc =3D of_property_read_u32(to_of_node(dev->fwnode), "riscv,num-sources", - &priv->nr_irqs); - if (rc) { - dev_err(dev, "failed to get number of interrupt sources\n"); - return rc; - } - - /* - * Find out number of IDCs based on parent interrupts - * - * If "msi-parent" property is present then we ignore the - * APLIC IDCs which forces the APLIC driver to use MSI mode. - */ - if (!of_property_present(to_of_node(dev->fwnode), "msi-parent")) { - while (!of_irq_parse_one(to_of_node(dev->fwnode), priv->nr_idcs, &parent= )) - priv->nr_idcs++; + if (is_of_node(dev->fwnode)) { + /* Find out number of interrupt sources */ + rc =3D of_property_read_u32(to_of_node(dev->fwnode), "riscv,num-sources", + &priv->nr_irqs); + if (rc) { + dev_err(dev, "failed to get number of interrupt sources\n"); + return rc; + } + + /* + * Find out number of IDCs based on parent interrupts + * + * If "msi-parent" property is present then we ignore the + * APLIC IDCs which forces the APLIC driver to use MSI mode. + */ + if (!of_property_present(to_of_node(dev->fwnode), "msi-parent")) { + while (!of_irq_parse_one(to_of_node(dev->fwnode), priv->nr_idcs, &paren= t)) + priv->nr_idcs++; + } + } else { + rc =3D riscv_acpi_get_gsi_info(dev->fwnode, &priv->gsi_base, &priv->id, + &priv->nr_irqs, &priv->nr_idcs); + if (rc) { + dev_err(dev, "failed to find GSI mapping\n"); + return rc; + } } =20 /* Setup initial state APLIC interrupts */ @@ -186,6 +199,9 @@ static int aplic_probe(struct platform_device *pdev) */ if (is_of_node(dev->fwnode)) msi_mode =3D of_property_present(to_of_node(dev->fwnode), "msi-parent"); + else + msi_mode =3D imsic_acpi_get_fwnode(NULL) ? 1 : 0; + if (msi_mode) rc =3D aplic_msi_setup(dev, regs); else @@ -193,6 +209,11 @@ static int aplic_probe(struct platform_device *pdev) if (rc) dev_err(dev, "failed to setup APLIC in %s mode\n", msi_mode ? "MSI" : "d= irect"); =20 +#ifdef CONFIG_ACPI + if (!acpi_disabled) + acpi_dev_clear_dependencies(ACPI_COMPANION(dev)); +#endif + return rc; } =20 @@ -205,6 +226,7 @@ static struct platform_driver aplic_driver =3D { .driver =3D { .name =3D "riscv-aplic", .of_match_table =3D aplic_match, + .acpi_match_table =3D ACPI_PTR(aplic_acpi_match), }, .probe =3D aplic_probe, }; diff --git a/drivers/irqchip/irq-riscv-aplic-main.h b/drivers/irqchip/irq-r= iscv-aplic-main.h index 4393927d8c80..9fbf45c7b4f7 100644 --- a/drivers/irqchip/irq-riscv-aplic-main.h +++ b/drivers/irqchip/irq-riscv-aplic-main.h @@ -28,6 +28,7 @@ struct aplic_priv { u32 gsi_base; u32 nr_irqs; u32 nr_idcs; + u32 id; void __iomem *regs; struct aplic_msicfg msicfg; }; diff --git a/drivers/irqchip/irq-riscv-aplic-msi.c b/drivers/irqchip/irq-ri= scv-aplic-msi.c index 028444af48bd..f5020241e0ed 100644 --- a/drivers/irqchip/irq-riscv-aplic-msi.c +++ b/drivers/irqchip/irq-riscv-aplic-msi.c @@ -157,6 +157,7 @@ static const struct msi_domain_template aplic_msi_templ= ate =3D { int aplic_msi_setup(struct device *dev, void __iomem *regs) { const struct imsic_global_config *imsic_global; + struct irq_domain *msi_domain; struct aplic_priv *priv; struct aplic_msicfg *mc; phys_addr_t pa; @@ -239,8 +240,14 @@ int aplic_msi_setup(struct device *dev, void __iomem *= regs) * IMSIC and the IMSIC MSI domains are created later through * the platform driver probing so we set it explicitly here. */ - if (is_of_node(dev->fwnode)) + if (is_of_node(dev->fwnode)) { of_msi_configure(dev, to_of_node(dev->fwnode)); + } else { + msi_domain =3D irq_find_matching_fwnode(imsic_acpi_get_fwnode(dev), + DOMAIN_BUS_PLATFORM_MSI); + if (msi_domain) + dev_set_msi_domain(dev, msi_domain); + } } =20 if (!msi_create_device_irq_domain(dev, MSI_DEFAULT_DOMAIN, &aplic_msi_tem= plate, --=20 2.40.1 From nobody Wed Dec 17 23:32:07 2025 Received: from mail-pl1-f180.google.com (mail-pl1-f180.google.com [209.85.214.180]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 6147E128385 for ; Wed, 1 May 2024 12:20:08 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.214.180 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1714566009; cv=none; b=uQ3p36LjipItSyyLeJefmviVZHZ06PzQ5RWTYN3yHqDPO8OFklQUXkBJVoiMxFbqPYOdLGti6GzIC6+UrZYFiT8cxZXhsxxQOtHFTm27p0geSkk2STHdEbZcRTpaWxUR8k7V8qBBJ5hK3RP/BSobEx657pPnMHNmE8uCfAmPe+E= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1714566009; c=relaxed/simple; bh=m6TSaqDnA4vNxdsvAdEsFy7ZWBxeRMhznnW8/gHp2ag=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=ayBNBOgvPUNirGvzWSFBnObG3QsWQsodN0VWzCnMvBFZyEXbs4/fyC7ykS2WN/7OnW30OmevsvprLO8xLg3ZLdvkirevWkifzCU1XBNvAB83nVmsDMLEsQ+o+QP1JVcplWuN40CDePhoiz6GrxVp31zK9LXQ9kHgnJ1o4vKGbG0= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=ventanamicro.com; spf=pass smtp.mailfrom=ventanamicro.com; dkim=pass (2048-bit key) header.d=ventanamicro.com header.i=@ventanamicro.com header.b=DRcpgpEN; arc=none smtp.client-ip=209.85.214.180 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=ventanamicro.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=ventanamicro.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=ventanamicro.com header.i=@ventanamicro.com header.b="DRcpgpEN" Received: by mail-pl1-f180.google.com with SMTP id d9443c01a7336-1e9ffd3f96eso54548385ad.3 for ; Wed, 01 May 2024 05:20:08 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1714566008; x=1715170808; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=sCs3yrmzFwEswQj2N8wV0vpYdlRUqd+77n2ry9m3784=; b=DRcpgpEN5mKVeJmcdK8mPgOLT4hftb/Sm7Y/6UQqNMwV6Mh190Gg4ytwn3Zdplw7qb yRU9SovhmqWpTv2qflFvir3UuYu3yXRI4RohidsXIuYKzOuhdPTB2RZrQGghhF5YD29U 6L7YWRP1WJciPA30b6Rf+4c8NOcNcogx+aWJlYBAF+0GABai7bY2O+MLRSTnQbke+RSW I+IenjwArZLcyjIKn+Lqz6lirH0p/+8o3ZxTM15KGVDY+mKHnJUwyQqiUs0KOEgFTV4A R8zTLRHFLZmZ05UxnjquD4t10MjgdD1+97R4QJFHQPmfEJZ9PpOP+j72nQdXB97V0tLG rlNA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1714566008; x=1715170808; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=sCs3yrmzFwEswQj2N8wV0vpYdlRUqd+77n2ry9m3784=; b=S0OpRi3hlhcMcBktONyApOXpMo/p4pEOcUh8Rj2UgjVOuiKabrolgg09H/DHiQqRLh AxaCoqdCid1S6lumn4qaPtPSBT2jlJo1rlWIdEAAzcGQXGBVmr8xA3cZzMhMSeRvaEL2 YSaxRjUjLbk63p8T/2skj72vxXfT1aMi31BOjncRhmRYBXNNJdHVZDCVFds77ef7NKLe Y5xUu4NVPNyZdlUz0GNim8Ljo3MOtmPbM8MZaSdgqOG42wdR+ZEwMr5BbJmMcq4/uUvU cuhV9oIpmAK0WYmmAwRFQxg9zym0Akr5AOwSi059heHEv1xLsv70GMYClphSMsKCgNdm y/4w== X-Forwarded-Encrypted: i=1; AJvYcCVYPrPkCGlp3kwEbLAs3tF5eKYKSYrpz6no4BFvEV6broF9q48POMlj5oCvdvFLhkKUz+vT2NZ0p7sbGLbsmDJVjWNKrFNA9bi4KDRe X-Gm-Message-State: AOJu0YwWA0kUEdJSrKbpfCLz3GjG+LlGYAeafeoL1K3CwYhvTIaBtew2 s7sclIpNIJnmqT1YBsEhix4ss0JZ7gn2W/z1tbDzzPYc+4L0lRwUJQwuLC26vFQ= X-Google-Smtp-Source: AGHT+IEE0GElfwoFz8rK8ax73/m32/DYftPNktmYVGk+PoIc+wfQ5hYwE+vbTd662q3C/FXcAaIUlQ== X-Received: by 2002:a17:903:2303:b0:1eb:7172:673b with SMTP id d3-20020a170903230300b001eb7172673bmr2574288plh.16.1714566007835; Wed, 01 May 2024 05:20:07 -0700 (PDT) Received: from sunil-pc.Dlink ([106.51.188.106]) by smtp.gmail.com with ESMTPSA id im15-20020a170902bb0f00b001ec8888b22esm1336900plb.65.2024.05.01.05.20.00 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 01 May 2024 05:20:07 -0700 (PDT) From: Sunil V L To: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, linux-acpi@vger.kernel.org, linux-pci@vger.kernel.org, linux-serial@vger.kernel.org, acpica-devel@lists.linux.dev Cc: Catalin Marinas , Will Deacon , Paul Walmsley , Albert Ou , "Rafael J . Wysocki" , Len Brown , Bjorn Helgaas , Anup Patel , Thomas Gleixner , Samuel Holland , Greg Kroah-Hartman , Jiri Slaby , Robert Moore , Conor Dooley , Andrew Jones , Andy Shevchenko , Marc Zyngier , Atish Kumar Patra , Andrei Warkentin , Haibo1 Xu , =?UTF-8?q?Bj=C3=B6rn=20T=C3=B6pel?= , Sunil V L Subject: [PATCH v5 16/17] irqchip/sifive-plic: Add ACPI support Date: Wed, 1 May 2024 17:47:41 +0530 Message-Id: <20240501121742.1215792-17-sunilvl@ventanamicro.com> X-Mailer: git-send-email 2.40.1 In-Reply-To: <20240501121742.1215792-1-sunilvl@ventanamicro.com> References: <20240501121742.1215792-1-sunilvl@ventanamicro.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add ACPI support in PLIC driver. Use the mapping created early during boot to get details about the PLIC. Signed-off-by: Sunil V L Co-developed-by: Haibo Xu Signed-off-by: Haibo Xu --- drivers/irqchip/irq-sifive-plic.c | 89 +++++++++++++++++++++++-------- 1 file changed, 68 insertions(+), 21 deletions(-) diff --git a/drivers/irqchip/irq-sifive-plic.c b/drivers/irqchip/irq-sifive= -plic.c index 8fb183ced1e7..b6b04b5923c2 100644 --- a/drivers/irqchip/irq-sifive-plic.c +++ b/drivers/irqchip/irq-sifive-plic.c @@ -3,6 +3,7 @@ * Copyright (C) 2017 SiFive * Copyright (C) 2018 Christoph Hellwig */ +#include #include #include #include @@ -70,6 +71,8 @@ struct plic_priv { unsigned long plic_quirks; unsigned int nr_irqs; unsigned long *prio_save; + u32 gsi_base; + int id; }; =20 struct plic_handler { @@ -324,6 +327,10 @@ static int plic_irq_domain_translate(struct irq_domain= *d, { struct plic_priv *priv =3D d->host_data; =20 + /* For DT, gsi_base is always zero. */ + if (fwspec->param[0] >=3D priv->gsi_base) + fwspec->param[0] =3D fwspec->param[0] - priv->gsi_base; + if (test_bit(PLIC_QUIRK_EDGE_INTERRUPT, &priv->plic_quirks)) return irq_domain_translate_twocell(d, fwspec, hwirq, type); =20 @@ -424,18 +431,32 @@ static const struct of_device_id plic_match[] =3D { {} }; =20 +#ifdef CONFIG_ACPI + +static const struct acpi_device_id plic_acpi_match[] =3D { + { "RSCV0001", 0 }, + {} +}; +MODULE_DEVICE_TABLE(acpi, plic_acpi_match); + +#endif static int plic_parse_nr_irqs_and_contexts(struct platform_device *pdev, - u32 *nr_irqs, u32 *nr_contexts) + u32 *nr_irqs, u32 *nr_contexts, + u32 *gsi_base, u32 *id) { struct device *dev =3D &pdev->dev; int rc; =20 - /* - * Currently, only OF fwnode is supported so extend this - * function for ACPI support. - */ - if (!is_of_node(dev->fwnode)) - return -EINVAL; + if (!is_of_node(dev->fwnode)) { + riscv_acpi_get_gsi_info(dev->fwnode, gsi_base, id, nr_irqs, NULL); + acpi_get_plic_nr_contexts(*id, nr_contexts); + if (WARN_ON(!*nr_contexts)) { + dev_err(dev, "no PLIC context available\n"); + return -EINVAL; + } + + return 0; + } =20 rc =3D of_property_read_u32(to_of_node(dev->fwnode), "riscv,ndev", nr_irq= s); if (rc) { @@ -449,23 +470,29 @@ static int plic_parse_nr_irqs_and_contexts(struct pla= tform_device *pdev, return -EINVAL; } =20 + *gsi_base =3D 0; + *id =3D 0; + return 0; } =20 static int plic_parse_context_parent(struct platform_device *pdev, u32 con= text, - u32 *parent_hwirq, int *parent_cpu) + u32 *parent_hwirq, int *parent_cpu, u32 id) { struct device *dev =3D &pdev->dev; struct of_phandle_args parent; unsigned long hartid; int rc; =20 - /* - * Currently, only OF fwnode is supported so extend this - * function for ACPI support. - */ - if (!is_of_node(dev->fwnode)) - return -EINVAL; + if (!is_of_node(dev->fwnode)) { + rc =3D acpi_get_ext_intc_parent_hartid(id, context, &hartid); + if (rc) + return rc; + + *parent_cpu =3D riscv_hartid_to_cpuid(hartid); + *parent_hwirq =3D RV_IRQ_EXT; + return 0; + } =20 rc =3D of_irq_parse_one(to_of_node(dev->fwnode), context, &parent); if (rc) @@ -490,7 +517,9 @@ static int plic_probe(struct platform_device *pdev) struct irq_domain *domain; struct plic_priv *priv; irq_hw_number_t hwirq; + int id, context_id; bool cpuhp_setup; + u32 gsi_base; =20 if (is_of_node(dev->fwnode)) { const struct of_device_id *id; @@ -500,7 +529,7 @@ static int plic_probe(struct platform_device *pdev) plic_quirks =3D (unsigned long)id->data; } =20 - error =3D plic_parse_nr_irqs_and_contexts(pdev, &nr_irqs, &nr_contexts); + error =3D plic_parse_nr_irqs_and_contexts(pdev, &nr_irqs, &nr_contexts, &= gsi_base, &id); if (error) return error; =20 @@ -511,6 +540,8 @@ static int plic_probe(struct platform_device *pdev) priv->dev =3D dev; priv->plic_quirks =3D plic_quirks; priv->nr_irqs =3D nr_irqs; + priv->gsi_base =3D gsi_base; + priv->id =3D id; =20 priv->regs =3D devm_platform_ioremap_resource(pdev, 0); if (WARN_ON(!priv->regs)) @@ -521,12 +552,22 @@ static int plic_probe(struct platform_device *pdev) return -ENOMEM; =20 for (i =3D 0; i < nr_contexts; i++) { - error =3D plic_parse_context_parent(pdev, i, &parent_hwirq, &cpu); + error =3D plic_parse_context_parent(pdev, i, &parent_hwirq, &cpu, priv->= id); if (error) { dev_warn(dev, "hwirq for context%d not found\n", i); continue; } =20 + if (is_of_node(dev->fwnode)) { + context_id =3D i; + } else { + error =3D acpi_get_plic_context(priv->id, i, &context_id); + if (error) { + dev_warn(dev, "invalid context id for context%d\n", i); + continue; + } + } + /* * Skip contexts other than external interrupts for our * privilege level. @@ -572,10 +613,10 @@ static int plic_probe(struct platform_device *pdev) cpumask_set_cpu(cpu, &priv->lmask); handler->present =3D true; handler->hart_base =3D priv->regs + CONTEXT_BASE + - i * CONTEXT_SIZE; + context_id * CONTEXT_SIZE; raw_spin_lock_init(&handler->enable_lock); handler->enable_base =3D priv->regs + CONTEXT_ENABLE_BASE + - i * CONTEXT_ENABLE_SIZE; + context_id * CONTEXT_ENABLE_SIZE; handler->priv =3D priv; =20 handler->enable_save =3D devm_kcalloc(dev, DIV_ROUND_UP(nr_irqs, 32), @@ -591,8 +632,8 @@ static int plic_probe(struct platform_device *pdev) nr_handlers++; } =20 - priv->irqdomain =3D irq_domain_add_linear(to_of_node(dev->fwnode), nr_irq= s + 1, - &plic_irqdomain_ops, priv); + priv->irqdomain =3D irq_domain_create_linear(dev->fwnode, nr_irqs + 1, + &plic_irqdomain_ops, priv); if (WARN_ON(!priv->irqdomain)) goto fail_cleanup_contexts; =20 @@ -619,13 +660,18 @@ static int plic_probe(struct platform_device *pdev) } } =20 +#ifdef CONFIG_ACPI + if (!acpi_disabled) + acpi_dev_clear_dependencies(ACPI_COMPANION(dev)); +#endif + dev_info(dev, "mapped %d interrupts with %d handlers for %d contexts.\n", nr_irqs, nr_handlers, nr_contexts); return 0; =20 fail_cleanup_contexts: for (i =3D 0; i < nr_contexts; i++) { - if (plic_parse_context_parent(pdev, i, &parent_hwirq, &cpu)) + if (plic_parse_context_parent(pdev, i, &parent_hwirq, &cpu, priv->id)) continue; if (parent_hwirq !=3D RV_IRQ_EXT || cpu < 0) continue; @@ -644,6 +690,7 @@ static struct platform_driver plic_driver =3D { .driver =3D { .name =3D "riscv-plic", .of_match_table =3D plic_match, + .acpi_match_table =3D ACPI_PTR(plic_acpi_match), }, .probe =3D plic_probe, }; --=20 2.40.1 From nobody Wed Dec 17 23:32:07 2025 Received: from mail-pl1-f181.google.com (mail-pl1-f181.google.com [209.85.214.181]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 1D81512880A for ; Wed, 1 May 2024 12:20:16 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.214.181 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1714566017; cv=none; b=Z1vyPMJ6oBuhtLr+ZWlJUglG+7jqiU/pY9wzHot5vs+Zn5agR36rJoFQ5FLFA6NeUU3eKz5gydHtdUJg7A1wTaA0tPIO2VRmclMjvi1or8Ba9nrBPtXbGUnKKjtV5I2PyYZU3+qkpBYQX5h1GYEHg0om/JH87YzDpCCTzwwFV3A= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1714566017; c=relaxed/simple; bh=VlgCsjgHFwA68EYgPCGJqFoun4py/yY/7/kh2NDKDJI=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=ZY3EW1/gly5aBRETyUPtj6xeSKnwEmQTv3nCmTPrsU/R+4pQ2BBhqJ8Bida8NSuTVg9a9MKJ4tRSPo2BkEjaPrAyzLI8w31E55LdRVOCe/S4dIauxcmbjuoxodAEaqnzvKnKrSoYes8A0GJ2m0cRhUsAgg1SHB2665DXrjJ8Rq4= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=ventanamicro.com; spf=pass smtp.mailfrom=ventanamicro.com; dkim=pass (2048-bit key) header.d=ventanamicro.com header.i=@ventanamicro.com header.b=Glp0pIEB; arc=none smtp.client-ip=209.85.214.181 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=ventanamicro.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=ventanamicro.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=ventanamicro.com header.i=@ventanamicro.com header.b="Glp0pIEB" Received: by mail-pl1-f181.google.com with SMTP id d9443c01a7336-1eb0e08bfd2so33078575ad.1 for ; Wed, 01 May 2024 05:20:16 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1714566015; x=1715170815; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=NA6fALA+ztvPArpqc5Jdn/FWi0fZsP181uxTjKG28r0=; b=Glp0pIEBnVyWeZfWxXYwNzC8oBfI/wqSyuBNSK23gqbox17wl8dbxbg3SLmsFTLuBc aFmZvcC5mFntdKMRgAyyLdoPUf5w10nExohVbqrACvqZfyvpmualCzeh4MeCQb33XFUN TfcsYtAApQ4/CbhKCTUEqy5m2PcmhLUY0veX7jB7ec3fX5NGhc2xpvz5nr1GEcpbCwY6 tiWnjhdCIJICqwtQpFlohK+LmIVwmu4JKc1HIdGvTwk6OnIQEN63TYyyYEoAgYfI63QQ z8wr9ovAubxPsHobyewJw+ZPDK0fOge/1KstpFBphf6a5HhU8WaIvFMwe3CQxl7oILnj yL7g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1714566015; x=1715170815; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=NA6fALA+ztvPArpqc5Jdn/FWi0fZsP181uxTjKG28r0=; b=X8liK3k3+n7cMsi4pEz7Fmn5UNbcqqhSimUt1/77vIWCZWhn6M4pkSSNsExb5vDGuv pojGQi2VmzUektHC7RzZlx5TlHlC5rucBAzBpLVOf/Vu5EXbLoaMC9Z2iY1f6/5gjsb1 PHZOCL8dc/oVis7G9Xs1bl76TPSoAQp9kJoLNesai+eDLsAoq+P3ZoyC7X4q/qWCKNW3 /Z0z+Xqrkml1s1RD/H1ZLCYkyM4xqoRGzN8vLJPU/X/3GnN117f1uDINrO01LC88Punr 8r/0ADcVmZ4/6Lo3kXS6AnO7u0CfpqX0QOtthhxuW+iIefrIzJ9R3EE+nRrNKbQC+Mp0 DqJQ== X-Forwarded-Encrypted: i=1; AJvYcCVA3lJf5ytzsoq42rJsNIoBYFLi/pCIUmJXFeYNLPv60kNU2SYU8o0ujU1fYrnvU/XO3pKvyx1Ev7jwAzMQeQ6pe7n64lFiUYweQjlo X-Gm-Message-State: AOJu0YyFoLTnXOUHHb5w/djJm2RYIInJrxCOMVCdwh65zTNhJB/sBo6/ 4MqTBlW3rWu4zFBQEVjTjOORAw2oqKO6WNH6dNRbxgBs0IxdwnUwKzxaF9Lh5to= X-Google-Smtp-Source: AGHT+IHYfyPObdgft5ubD0a+EdF/ZUFESa543BOMp550uRgpGcGY3JeWyQR+nmnrayByMoL+UjNZmA== X-Received: by 2002:a17:902:ed01:b0:1eb:494f:dc66 with SMTP id b1-20020a170902ed0100b001eb494fdc66mr2209312pld.23.1714566015601; Wed, 01 May 2024 05:20:15 -0700 (PDT) Received: from sunil-pc.Dlink ([106.51.188.106]) by smtp.gmail.com with ESMTPSA id im15-20020a170902bb0f00b001ec8888b22esm1336900plb.65.2024.05.01.05.20.08 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 01 May 2024 05:20:15 -0700 (PDT) From: Sunil V L To: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, linux-acpi@vger.kernel.org, linux-pci@vger.kernel.org, linux-serial@vger.kernel.org, acpica-devel@lists.linux.dev Cc: Catalin Marinas , Will Deacon , Paul Walmsley , Albert Ou , "Rafael J . Wysocki" , Len Brown , Bjorn Helgaas , Anup Patel , Thomas Gleixner , Samuel Holland , Greg Kroah-Hartman , Jiri Slaby , Robert Moore , Conor Dooley , Andrew Jones , Andy Shevchenko , Marc Zyngier , Atish Kumar Patra , Andrei Warkentin , Haibo1 Xu , =?UTF-8?q?Bj=C3=B6rn=20T=C3=B6pel?= , Sunil V L Subject: [PATCH v5 17/17] serial: 8250: Add 8250_acpi driver Date: Wed, 1 May 2024 17:47:42 +0530 Message-Id: <20240501121742.1215792-18-sunilvl@ventanamicro.com> X-Mailer: git-send-email 2.40.1 In-Reply-To: <20240501121742.1215792-1-sunilvl@ventanamicro.com> References: <20240501121742.1215792-1-sunilvl@ventanamicro.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" RISC-V has non-PNP generic 16550A compatible UART which needs to be enumerated as ACPI platform device. Add driver support for such devices similar to 8250_of. The driver is enabled when the CONFIG_SERIAL_ACPI_PLATFORM option is enabled. Enable this option for RISC-V. Signed-off-by: Sunil V L --- arch/riscv/configs/defconfig | 1 + drivers/tty/serial/8250/8250_acpi.c | 96 +++++++++++++++++++++++++++++ drivers/tty/serial/8250/Kconfig | 8 +++ drivers/tty/serial/8250/Makefile | 1 + 4 files changed, 106 insertions(+) create mode 100644 drivers/tty/serial/8250/8250_acpi.c diff --git a/arch/riscv/configs/defconfig b/arch/riscv/configs/defconfig index 3cae018f9315..bea8241f52eb 100644 --- a/arch/riscv/configs/defconfig +++ b/arch/riscv/configs/defconfig @@ -150,6 +150,7 @@ CONFIG_SERIAL_8250=3Dy CONFIG_SERIAL_8250_CONSOLE=3Dy CONFIG_SERIAL_8250_DW=3Dy CONFIG_SERIAL_OF_PLATFORM=3Dy +CONFIG_SERIAL_ACPI_PLATFORM=3Dy CONFIG_SERIAL_SH_SCI=3Dy CONFIG_SERIAL_EARLYCON_RISCV_SBI=3Dy CONFIG_VIRTIO_CONSOLE=3Dy diff --git a/drivers/tty/serial/8250/8250_acpi.c b/drivers/tty/serial/8250/= 8250_acpi.c new file mode 100644 index 000000000000..3682443bb69c --- /dev/null +++ b/drivers/tty/serial/8250/8250_acpi.c @@ -0,0 +1,96 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Serial Port driver for ACPI platform devices + * + * This driver is for generic 16550 compatible UART enumerated via ACPI + * platform bus instead of PNP bus like PNP0501. This is not a full + * driver but mostly provides the ACPI wrapper and uses generic + * 8250 framework for rest of the functionality. + */ + +#include +#include +#include + +#include "8250.h" + +struct acpi_serial_info { + int line; +}; + +static int acpi_platform_serial_probe(struct platform_device *pdev) +{ + struct acpi_serial_info *data; + struct uart_8250_port port8250; + struct device *dev =3D &pdev->dev; + struct resource *regs; + + int ret, irq; + + regs =3D platform_get_resource(pdev, IORESOURCE_MEM, 0); + if (!regs) { + dev_err(dev, "no registers defined\n"); + return -EINVAL; + } + + irq =3D platform_get_irq(pdev, 0); + if (irq < 0) + return irq; + + memset(&port8250, 0, sizeof(port8250)); + + spin_lock_init(&port8250.port.lock); + + port8250.port.mapbase =3D regs->start; + port8250.port.irq =3D irq; + port8250.port.type =3D PORT_16550A; + port8250.port.flags =3D UPF_SHARE_IRQ | UPF_BOOT_AUTOCONF | U= PF_FIXED_PORT | + UPF_IOREMAP | UPF_FIXED_TYPE; + port8250.port.dev =3D dev; + port8250.port.mapsize =3D resource_size(regs); + port8250.port.iotype =3D UPIO_MEM; + port8250.port.irqflags =3D IRQF_SHARED; + + port8250.port.membase =3D devm_ioremap(dev, port8250.port.mapbase, port82= 50.port.mapsize); + if (!port8250.port.membase) + return -ENOMEM; + + ret =3D uart_read_and_validate_port_properties(&port8250.port); + if (ret) + return -EINVAL; + + data =3D devm_kzalloc(dev, sizeof(*data), GFP_KERNEL); + if (!data) + return -ENOMEM; + + data->line =3D serial8250_register_8250_port(&port8250); + if (data->line < 0) + return data->line; + + platform_set_drvdata(pdev, data); + return 0; +} + +static void acpi_platform_serial_remove(struct platform_device *pdev) +{ + struct acpi_serial_info *data =3D platform_get_drvdata(pdev); + + serial8250_unregister_port(data->line); +} + +static const struct acpi_device_id acpi_platform_serial_table[] =3D { + { "RSCV0003", 0 }, + { }, +}; +MODULE_DEVICE_TABLE(acpi, acpi_platform_serial_table); + +static struct platform_driver acpi_platform_serial_driver =3D { + .driver =3D { + .name =3D "acpi_serial", + .acpi_match_table =3D ACPI_PTR(acpi_platform_serial_table), + }, + .probe =3D acpi_platform_serial_probe, + .remove_new =3D acpi_platform_serial_remove, +}; + +builtin_platform_driver(acpi_platform_serial_driver); diff --git a/drivers/tty/serial/8250/Kconfig b/drivers/tty/serial/8250/Kcon= fig index 47ff50763c04..fbfe4d3501b1 100644 --- a/drivers/tty/serial/8250/Kconfig +++ b/drivers/tty/serial/8250/Kconfig @@ -576,3 +576,11 @@ config SERIAL_OF_PLATFORM are probed through devicetree, including Open Firmware based PowerPC systems and embedded systems on architectures using the flattened device tree format. + +config SERIAL_ACPI_PLATFORM + tristate "ACPI platform bus based probing for 8250 ports" + depends on SERIAL_8250 && ACPI + default n + help + This option is used for generic 8250 compatible serial ports + that are enumerated through ACPI platform bus. diff --git a/drivers/tty/serial/8250/Makefile b/drivers/tty/serial/8250/Mak= efile index ea2e81f58eac..8c0ef357fc4e 100644 --- a/drivers/tty/serial/8250/Makefile +++ b/drivers/tty/serial/8250/Makefile @@ -18,6 +18,7 @@ obj-$(CONFIG_SERIAL_8250_CONSOLE) +=3D 8250_early.o =20 obj-$(CONFIG_SERIAL_8250_ACCENT) +=3D 8250_accent.o obj-$(CONFIG_SERIAL_8250_ACORN) +=3D 8250_acorn.o +obj-$(CONFIG_SERIAL_ACPI_PLATFORM) +=3D 8250_acpi.o obj-$(CONFIG_SERIAL_8250_ASPEED_VUART) +=3D 8250_aspeed_vuart.o obj-$(CONFIG_SERIAL_8250_BCM2835AUX) +=3D 8250_bcm2835aux.o obj-$(CONFIG_SERIAL_8250_BCM7271) +=3D 8250_bcm7271.o --=20 2.40.1