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[34.125.198.4]) by smtp.gmail.com with UTF8SMTPSA id a4-20020a170902ecc400b001eac9aa55edsm8059703plh.250.2024.04.29.13.00.17 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 29 Apr 2024 13:00:17 -0700 (PDT) From: Stephen Boyd To: stable@vger.kernel.org Cc: Johan Hovold , linux-kernel@vger.kernel.org, patches@lists.linux.dev, Abhinav Kumar , Dmitry Baryshkov , Vinod Koul Subject: [PATCH 6.6.y] phy: qcom: qmp-combo: fix VCO div offset on v5_5nm and v6 Date: Mon, 29 Apr 2024 13:00:16 -0700 Message-ID: <20240429200017.3751576-1-swboyd@chromium.org> X-Mailer: git-send-email 2.45.0.rc0.197.gbae5840b3b-goog In-Reply-To: <2024042919-enlisted-punch-79a5@gregkh> References: <2024042919-enlisted-punch-79a5@gregkh> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Johan Hovold Commit 5abed58a8bde ("phy: qcom: qmp-combo: Fix VCO div offset on v3") fixed a regression introduced in 6.5 by making sure that the correct offset is used for the DP_PHY_VCO_DIV register on v3 hardware. Unfortunately, that fix instead broke DisplayPort on v5_5nm and v6 hardware as it failed to add the corresponding offsets also to those register tables. Fixes: 815891eee668 ("phy: qcom-qmp-combo: Introduce orientation variable") Fixes: 5abed58a8bde ("phy: qcom: qmp-combo: Fix VCO div offset on v3") Cc: stable@vger.kernel.org # 6.5: 5abed58a8bde Cc: Stephen Boyd Cc: Abhinav Kumar Cc: Dmitry Baryshkov Signed-off-by: Johan Hovold Reviewed-by: Dmitry Baryshkov Reviewed-by: Stephen Boyd Reviewed-by: Abhinav Kumar Link: https://lore.kernel.org/r/20240408093023.506-1-johan+linaro@kernel.org Signed-off-by: Vinod Koul (cherry picked from commit 025a6f7448f7bb5f4fceb62498ee33d89ae266bb) Signed-off-by: Stephen Boyd --- drivers/phy/qualcomm/phy-qcom-qmp-combo.c | 2 ++ drivers/phy/qualcomm/phy-qcom-qmp.h | 2 ++ 2 files changed, 4 insertions(+) diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-combo.c b/drivers/phy/qualco= mm/phy-qcom-qmp-combo.c index 27d7895a9b61..be837dee81f7 100644 --- a/drivers/phy/qualcomm/phy-qcom-qmp-combo.c +++ b/drivers/phy/qualcomm/phy-qcom-qmp-combo.c @@ -188,6 +188,7 @@ static const unsigned int qmp_v5_5nm_usb3phy_regs_layou= t[QPHY_LAYOUT_SIZE] =3D { [QPHY_COM_BIAS_EN_CLKBUFLR_EN] =3D QSERDES_V5_COM_BIAS_EN_CLKBUFLR_EN, =20 [QPHY_DP_PHY_STATUS] =3D QSERDES_V5_DP_PHY_STATUS, + [QPHY_DP_PHY_VCO_DIV] =3D QSERDES_V5_DP_PHY_VCO_DIV, =20 [QPHY_TX_TX_POL_INV] =3D QSERDES_V5_5NM_TX_TX_POL_INV, [QPHY_TX_TX_DRV_LVL] =3D QSERDES_V5_5NM_TX_TX_DRV_LVL, @@ -212,6 +213,7 @@ static const unsigned int qmp_v6_usb3phy_regs_layout[QP= HY_LAYOUT_SIZE] =3D { [QPHY_COM_BIAS_EN_CLKBUFLR_EN] =3D QSERDES_V6_COM_PLL_BIAS_EN_CLK_BUFLR_E= N, =20 [QPHY_DP_PHY_STATUS] =3D QSERDES_V6_DP_PHY_STATUS, + [QPHY_DP_PHY_VCO_DIV] =3D QSERDES_V6_DP_PHY_VCO_DIV, =20 [QPHY_TX_TX_POL_INV] =3D QSERDES_V6_TX_TX_POL_INV, [QPHY_TX_TX_DRV_LVL] =3D QSERDES_V6_TX_TX_DRV_LVL, diff --git a/drivers/phy/qualcomm/phy-qcom-qmp.h b/drivers/phy/qualcomm/phy= -qcom-qmp.h index 32d897684755..e2c22edfe653 100644 --- a/drivers/phy/qualcomm/phy-qcom-qmp.h +++ b/drivers/phy/qualcomm/phy-qcom-qmp.h @@ -134,9 +134,11 @@ #define QPHY_V4_PCS_MISC_TYPEC_STATUS 0x10 #define QPHY_V4_PCS_MISC_PLACEHOLDER_STATUS 0x14 =20 +#define QSERDES_V5_DP_PHY_VCO_DIV 0x070 #define QSERDES_V5_DP_PHY_STATUS 0x0dc =20 /* Only for QMP V6 PHY - DP PHY registers */ +#define QSERDES_V6_DP_PHY_VCO_DIV 0x070 #define QSERDES_V6_DP_PHY_AUX_INTERRUPT_STATUS 0x0e0 #define QSERDES_V6_DP_PHY_STATUS 0x0e4 =20 --=20 https://chromeos.dev