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(h-178-174-189-39.A498.priv.bahnhof.se. [178.174.189.39]) by smtp.gmail.com with ESMTPSA id l5-20020a2e9085000000b002d7095bf808sm3636733ljg.128.2024.04.29.07.05.58 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 29 Apr 2024 07:05:59 -0700 (PDT) From: Ulf Hansson To: "Rafael J . Wysocki" , Sudeep Holla , linux-pm@vger.kernel.org Cc: Lorenzo Pieralisi , Nikunj Kela , Prasad Sodagudi , Maulik Shah , Daniel Lezcano , Krzysztof Kozlowski , Ulf Hansson , linux-rt-users@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH 5/6] cpuidle: psci: Enable the hierarchical topology for s2ram on PREEMPT_RT Date: Mon, 29 Apr 2024 16:05:30 +0200 Message-Id: <20240429140531.210576-6-ulf.hansson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240429140531.210576-1-ulf.hansson@linaro.org> References: <20240429140531.210576-1-ulf.hansson@linaro.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The hierarchical PM domain topology are currently disabled on a PREEMPT_RT based configuration. As a first step to enable it to be used, let's try to attach the CPU devices to their PM domains on PREEMPT_RT. In this way the syscore ops becomes available, allowing the PM domain topology to be managed during s2ram. For the moment let's leave the support for CPU hotplug outside PREEMPT_RT, as it's depending on using runtime PM. For s2ram, this isn't a problem as all CPUs are managed via the syscore ops. Signed-off-by: Ulf Hansson --- drivers/cpuidle/cpuidle-psci.c | 20 +++++++++++++++----- 1 file changed, 15 insertions(+), 5 deletions(-) diff --git a/drivers/cpuidle/cpuidle-psci.c b/drivers/cpuidle/cpuidle-psci.c index d82a8bc1b194..ad6ce9fe12b4 100644 --- a/drivers/cpuidle/cpuidle-psci.c +++ b/drivers/cpuidle/cpuidle-psci.c @@ -37,6 +37,7 @@ struct psci_cpuidle_data { =20 static DEFINE_PER_CPU_READ_MOSTLY(struct psci_cpuidle_data, psci_cpuidle_d= ata); static DEFINE_PER_CPU(u32, domain_state); +static bool psci_cpuidle_use_syscore; static bool psci_cpuidle_use_cpuhp; =20 void psci_set_domain_state(u32 state) @@ -166,6 +167,12 @@ static struct syscore_ops psci_idle_syscore_ops =3D { .resume =3D psci_idle_syscore_resume, }; =20 +static void psci_idle_init_syscore(void) +{ + if (psci_cpuidle_use_syscore) + register_syscore_ops(&psci_idle_syscore_ops); +} + static void psci_idle_init_cpuhp(void) { int err; @@ -173,8 +180,6 @@ static void psci_idle_init_cpuhp(void) if (!psci_cpuidle_use_cpuhp) return; =20 - register_syscore_ops(&psci_idle_syscore_ops); - err =3D cpuhp_setup_state_nocalls(CPUHP_AP_CPU_PM_STARTING, "cpuidle/psci:online", psci_idle_cpuhp_up, @@ -222,13 +227,16 @@ static int psci_dt_cpu_init_topology(struct cpuidle_d= river *drv, if (!psci_has_osi_support()) return 0; =20 - if (IS_ENABLED(CONFIG_PREEMPT_RT)) - return 0; - data->dev =3D dt_idle_attach_cpu(cpu, "psci"); if (IS_ERR_OR_NULL(data->dev)) return PTR_ERR_OR_ZERO(data->dev); =20 + psci_cpuidle_use_syscore =3D true; + + /* The hierarchical topology is limited to s2ram on PREEMPT_RT. */ + if (IS_ENABLED(CONFIG_PREEMPT_RT)) + return 0; + /* * Using the deepest state for the CPU to trigger a potential selection * of a shared state for the domain, assumes the domain states are all @@ -312,6 +320,7 @@ static void psci_cpu_deinit_idle(int cpu) struct psci_cpuidle_data *data =3D per_cpu_ptr(&psci_cpuidle_data, cpu); =20 dt_idle_detach_cpu(data->dev); + psci_cpuidle_use_syscore =3D false; psci_cpuidle_use_cpuhp =3D false; } =20 @@ -408,6 +417,7 @@ static int psci_cpuidle_probe(struct platform_device *p= dev) goto out_fail; } =20 + psci_idle_init_syscore(); psci_idle_init_cpuhp(); return 0; =20 --=20 2.34.1