From nobody Fri Dec 19 02:55:22 2025 Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.8]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 40C1D3B7A0; Mon, 29 Apr 2024 10:46:56 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=192.198.163.8 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1714387617; cv=none; b=o7VyS3YQAU7tE/WksLzJazlcvSgXPes3nH37ZRS9g+5pJXSsJnXZouyqpwhTE3kiDuYzxGL1ZebQEQEEqXyPTfBsYK7PSTlehHGzM+7cdLmps6ko0E2zr5+I09Dgp54PqPhfC1puPnOnKv3u+Y0EVuL7omvL6nMggSTxGBQD/Tw= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1714387617; c=relaxed/simple; bh=R2riUg/Wc1wqrQ5JnljoOoCmOH+vsHTb6i6sFG4RQIs=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version:Content-Type; b=nloWPX3plTXJATyRayba5DRMdvW/urzQH5AwA49n3EQoMmiSSyQwekffZM1LcJTEOS69q9kgXQlVWn65nWOfFwa8pzRBZn+DFy7d+km3mCnFiZcbmIpfL7nT3VFc7z/f1RYZxQCEldYg9DZwqpUw40fSIDX3X0r4N0y6XKShn9U= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com; spf=none smtp.mailfrom=linux.intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=DV7rtGNg; arc=none smtp.client-ip=192.198.163.8 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; spf=none smtp.mailfrom=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="DV7rtGNg" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1714387616; x=1745923616; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=R2riUg/Wc1wqrQ5JnljoOoCmOH+vsHTb6i6sFG4RQIs=; b=DV7rtGNgmisbdzuxAC2wVNJ+aWVXPizoyDTbCjETCLyjYT4k6oLE/Ks4 v27inOtscSRiCoIw0xA3GCARhvy8pw3xzeiV8H3h7/YqytnxlXICfx7hC ZOLOBmhwOZhtJKOceKEdZV3MpIXKs4cSFI5Jsero6jh08FtSqQIqp7pOV NpO6eyVKBwqcBJ4oevVzVJVVWsk889D7KU4dbShaIKBeljCb320Jiq4JU ZGIjPbHAfreZBVTpjOoBjeaYqc5+uIyMQ0jkj4lZixFwU6n9AUnENeJVg 4/pScTEX2Mbk6hhQt5Elif+3aBX5Tf/FsuQ2MHwltYlRhbJCYPEpP07US A==; X-CSE-ConnectionGUID: gLCXlhBgQcasfVScuPfcXw== X-CSE-MsgGUID: b1+wGhy8SFCWRmkuzJ4iCA== X-IronPort-AV: E=McAfee;i="6600,9927,11057"; a="27558815" X-IronPort-AV: E=Sophos;i="6.07,239,1708416000"; d="scan'208";a="27558815" Received: from orviesa004.jf.intel.com ([10.64.159.144]) by fmvoesa102.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 29 Apr 2024 03:46:55 -0700 X-CSE-ConnectionGUID: 8awMQp1vRrWFMQAWhN3V4A== X-CSE-MsgGUID: nM3+DbKYRoC6OTW0EV+TyA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.07,239,1708416000"; d="scan'208";a="30896676" Received: from ijarvine-desk1.ger.corp.intel.com (HELO localhost) ([10.245.247.45]) by orviesa004-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 29 Apr 2024 03:46:50 -0700 From: =?UTF-8?q?Ilpo=20J=C3=A4rvinen?= To: linux-pci@vger.kernel.org, Bjorn Helgaas , Lorenzo Pieralisi , Rob Herring , =?UTF-8?q?Krzysztof=20Wilczy=C5=84ski?= , Andrew Lunn , Sebastian Hesselbarth , Gregory Clement , Russell King , linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Cc: =?UTF-8?q?Ilpo=20J=C3=A4rvinen?= Subject: [PATCH 01/10] ARM: orion5x: Rename PCI_CONF_{REG,FUNC}() out of the way Date: Mon, 29 Apr 2024 13:46:24 +0300 Message-Id: <20240429104633.11060-2-ilpo.jarvinen@linux.intel.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20240429104633.11060-1-ilpo.jarvinen@linux.intel.com> References: <20240429104633.11060-1-ilpo.jarvinen@linux.intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable orion5x defines PCI_CONF_REG() and PCI_CONF_FUNC() that are problematic because PCI core is going to introduce defines with the same names. Add ORION5X prefix to those defines to avoid name conflicts. Note: as this is part of series that replaces the code in question anyway, only bare minimum renaming is done and other similarly named macros are not touched. Signed-off-by: Ilpo J=C3=A4rvinen Acked-by: Gregory CLEMENT Reviewed-by: Andrew Lunn --- arch/arm/mach-orion5x/pci.c | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/arch/arm/mach-orion5x/pci.c b/arch/arm/mach-orion5x/pci.c index 3313bc5a63ea..77ddab90f448 100644 --- a/arch/arm/mach-orion5x/pci.c +++ b/arch/arm/mach-orion5x/pci.c @@ -219,8 +219,8 @@ static int __init pcie_setup(struct pci_sys_data *sys) /* * PCI_CONF_ADDR bits */ -#define PCI_CONF_REG(reg) ((reg) & 0xfc) -#define PCI_CONF_FUNC(func) (((func) & 0x3) << 8) +#define ORION5X_PCI_CONF_REG(reg) ((reg) & 0xfc) +#define ORION5X_PCI_CONF_FUNC(func) (((func) & 0x3) << 8) #define PCI_CONF_DEV(dev) (((dev) & 0x1f) << 11) #define PCI_CONF_BUS(bus) (((bus) & 0xff) << 16) #define PCI_CONF_ADDR_EN (1 << 31) @@ -277,8 +277,8 @@ static int orion5x_pci_hw_rd_conf(int bus, int dev, u32= func, spin_lock_irqsave(&orion5x_pci_lock, flags); =20 writel(PCI_CONF_BUS(bus) | - PCI_CONF_DEV(dev) | PCI_CONF_REG(where) | - PCI_CONF_FUNC(func) | PCI_CONF_ADDR_EN, PCI_CONF_ADDR); + PCI_CONF_DEV(dev) | ORION5X_PCI_CONF_REG(where) | + ORION5X_PCI_CONF_FUNC(func) | PCI_CONF_ADDR_EN, PCI_CONF_ADDR); =20 *val =3D readl(PCI_CONF_DATA); =20 @@ -301,8 +301,8 @@ static int orion5x_pci_hw_wr_conf(int bus, int dev, u32= func, spin_lock_irqsave(&orion5x_pci_lock, flags); =20 writel(PCI_CONF_BUS(bus) | - PCI_CONF_DEV(dev) | PCI_CONF_REG(where) | - PCI_CONF_FUNC(func) | PCI_CONF_ADDR_EN, PCI_CONF_ADDR); + PCI_CONF_DEV(dev) | ORION5X_PCI_CONF_REG(where) | + ORION5X_PCI_CONF_FUNC(func) | PCI_CONF_ADDR_EN, PCI_CONF_ADDR); =20 if (size =3D=3D 4) { __raw_writel(val, PCI_CONF_DATA); --=20 2.39.2 From nobody Fri Dec 19 02:55:22 2025 Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.8]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 346AD1EB2F; Mon, 29 Apr 2024 10:47:06 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=192.198.163.8 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1714387629; cv=none; b=EvvHfaF8Y2b9CNxra+NmO93Zn+XPaLyLkK14ayIfX5EWRCJyzV8AicPKQGBSlFkckgbGQZS9XcBDS1I7sdAzWEgpuDsc5o061XW68IOXaBeQFydO4NoqmiG4De4NDlSoLpwHHjWCEsGJFL/NT1eQryYxsjBvBAd7kVQwaAsakmM= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1714387629; c=relaxed/simple; bh=5RZ+h1IoRyl+mzWTI7YpuHfoFDK7vqb4rzWTaBr0ZpE=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version:Content-Type; b=ESpDYlXwyBlsq5/NuWXLXAceZN53F6NI8zAZBEazh7FJShBcCZ+AQc9IzENqvtegXLKy6PLVs6KWsbGio5buVateXXT+TZOPfvNNwKkIE4CZp6KgB7VLofi4wB/DwtyMbZtTKkMSFZliepHrsxtvHRMiiNxBDSiwq2GdTrMQqSo= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com; spf=none smtp.mailfrom=linux.intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=C1NnVp3+; arc=none smtp.client-ip=192.198.163.8 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; spf=none smtp.mailfrom=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="C1NnVp3+" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1714387627; x=1745923627; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=5RZ+h1IoRyl+mzWTI7YpuHfoFDK7vqb4rzWTaBr0ZpE=; b=C1NnVp3+7Cpd4AFJNVijywjb7JkzPWJH3J11XRC8/Dl+iAgk4olZboNG KR80j4gQXW3LSDa4p7nv+KbgSyGYZPmBee/zQWLiBQgnmkYV1QhauIt5g uy+tw1iaNT8TrlnEPwv6yp4GsO/892Rf9gZdZETwY1etsC3pix1F9z0jB mXccSGazPx5BkHBEUu00kYM9rXwFWvzf7UWl03LbyJTMGTSbUHVc6lU5S QoNgR/kFXf3VcsXjRvDsO1/s55XN9ACx9ouVOGd7rxBB6h7c8/F6254bu 4dkqOw5/mHzYhCRbS5uwqp3JrTjxNhd/as3UrV4s6yLjf2S2bfQg3Hxw9 A==; X-CSE-ConnectionGUID: BCDj1uMMSPWr7lri/ZmiPA== X-CSE-MsgGUID: pfQLVlSeQqSjaInedNxZqw== X-IronPort-AV: E=McAfee;i="6600,9927,11057"; a="27558897" X-IronPort-AV: E=Sophos;i="6.07,239,1708416000"; d="scan'208";a="27558897" Received: from orviesa004.jf.intel.com ([10.64.159.144]) by fmvoesa102.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 29 Apr 2024 03:47:05 -0700 X-CSE-ConnectionGUID: 8t7syE0iRJuBM5i997zQkg== X-CSE-MsgGUID: BCE0VLeCQZihz3IHH40oOA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.07,239,1708416000"; d="scan'208";a="30896725" Received: from ijarvine-desk1.ger.corp.intel.com (HELO localhost) ([10.245.247.45]) by orviesa004-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 29 Apr 2024 03:47:00 -0700 From: =?UTF-8?q?Ilpo=20J=C3=A4rvinen?= To: linux-pci@vger.kernel.org, Bjorn Helgaas , Lorenzo Pieralisi , Rob Herring , =?UTF-8?q?Krzysztof=20Wilczy=C5=84ski?= , linux-kernel@vger.kernel.org Cc: =?UTF-8?q?Ilpo=20J=C3=A4rvinen?= Subject: [PATCH 02/10] PCI: Add helpers to calculate PCI Conf Type 0/1 addresses Date: Mon, 29 Apr 2024 13:46:25 +0300 Message-Id: <20240429104633.11060-3-ilpo.jarvinen@linux.intel.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20240429104633.11060-1-ilpo.jarvinen@linux.intel.com> References: <20240429104633.11060-1-ilpo.jarvinen@linux.intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Many places in arch and PCI controller code need to calculate PCI Configuration Space Addresses for Type 0/1 accesses. There are small variations between archs when it comes to bits outside of [10:2] (Type 0) and [24:2] (Type 1) but the basic calculation can still be generalized. drivers/pci/pci.h has PCI_CONF1{,_EXT}_ADDRESS() but due to their location the use is limited to PCI subsys and the also always enable PCI_CONF1_ENABLE which is not what all the callers want. Add generic pci_conf{0,1}_addr() and pci_conf1_ext_addr() helpers into include/linux/pci.h which can be reused by various parts of the kernel that have to calculate PCI Conf Type 0/1 addresses. The PCI_CONF* defines are needed by the new helpers so move also them to include/linux/pci.h. The new helpers use true bitmasks and FIELD_PREP() instead of open coded masking and shifting so adjust PCI_CONF* definitions to match that. Signed-off-by: Ilpo J=C3=A4rvinen --- drivers/pci/pci.h | 43 ++--------------------- include/linux/pci.h | 85 +++++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 88 insertions(+), 40 deletions(-) diff --git a/drivers/pci/pci.h b/drivers/pci/pci.h index 17fed1846847..cf0530a60105 100644 --- a/drivers/pci/pci.h +++ b/drivers/pci/pci.h @@ -833,49 +833,12 @@ struct pci_devres { =20 struct pci_devres *find_pci_dr(struct pci_dev *pdev); =20 -/* - * Config Address for PCI Configuration Mechanism #1 - * - * See PCI Local Bus Specification, Revision 3.0, - * Section 3.2.2.3.2, Figure 3-2, p. 50. - */ - -#define PCI_CONF1_BUS_SHIFT 16 /* Bus number */ -#define PCI_CONF1_DEV_SHIFT 11 /* Device number */ -#define PCI_CONF1_FUNC_SHIFT 8 /* Function number */ - -#define PCI_CONF1_BUS_MASK 0xff -#define PCI_CONF1_DEV_MASK 0x1f -#define PCI_CONF1_FUNC_MASK 0x7 -#define PCI_CONF1_REG_MASK 0xfc /* Limit aligned offset to a maximum of 25= 6B */ - -#define PCI_CONF1_ENABLE BIT(31) -#define PCI_CONF1_BUS(x) (((x) & PCI_CONF1_BUS_MASK) << PCI_CONF1_BUS_SHIF= T) -#define PCI_CONF1_DEV(x) (((x) & PCI_CONF1_DEV_MASK) << PCI_CONF1_DEV_SHIF= T) -#define PCI_CONF1_FUNC(x) (((x) & PCI_CONF1_FUNC_MASK) << PCI_CONF1_FUNC_S= HIFT) -#define PCI_CONF1_REG(x) ((x) & PCI_CONF1_REG_MASK) - #define PCI_CONF1_ADDRESS(bus, dev, func, reg) \ (PCI_CONF1_ENABLE | \ - PCI_CONF1_BUS(bus) | \ - PCI_CONF1_DEV(dev) | \ - PCI_CONF1_FUNC(func) | \ - PCI_CONF1_REG(reg)) - -/* - * Extension of PCI Config Address for accessing extended PCIe registers - * - * No standardized specification, but used on lot of non-ECAM-compliant AR= M SoCs - * or on AMD Barcelona and new CPUs. Reserved bits [27:24] of PCI Config A= ddress - * are used for specifying additional 4 high bits of PCI Express register. - */ - -#define PCI_CONF1_EXT_REG_SHIFT 16 -#define PCI_CONF1_EXT_REG_MASK 0xf00 -#define PCI_CONF1_EXT_REG(x) (((x) & PCI_CONF1_EXT_REG_MASK) << PCI_CONF1_= EXT_REG_SHIFT) + pci_conf1_addr(bus, PCI_DEVFN(dev, func), reg & ~0x3U)) =20 #define PCI_CONF1_EXT_ADDRESS(bus, dev, func, reg) \ - (PCI_CONF1_ADDRESS(bus, dev, func, reg) | \ - PCI_CONF1_EXT_REG(reg)) + (PCI_CONF1_ENABLE | \ + pci_conf1_ext_addr(bus, PCI_DEVFN(dev, func), reg & ~0x3U)) =20 #endif /* DRIVERS_PCI_H */ diff --git a/include/linux/pci.h b/include/linux/pci.h index 16493426a04f..4c4e3bb52a0a 100644 --- a/include/linux/pci.h +++ b/include/linux/pci.h @@ -26,6 +26,8 @@ #include #include =20 +#include +#include #include #include #include @@ -1183,6 +1185,89 @@ void pci_sort_breadthfirst(void); #define dev_is_pci(d) ((d)->bus =3D=3D &pci_bus_type) #define dev_is_pf(d) ((dev_is_pci(d) ? to_pci_dev(d)->is_physfn : false)) =20 +/* + * Config Address for PCI Configuration Mechanism #0/1 + * + * See PCI Local Bus Specification, Revision 3.0, + * Section 3.2.2.3.2, Figure 3-1 and 3-2, p. 48-50. + */ +#define PCI_CONF_REG 0x000000ffU /* common for Type 0/1 */ +#define PCI_CONF_FUNC 0x00000700U /* common for Type 0/1 */ +#define PCI_CONF1_DEV 0x0000f800U +#define PCI_CONF1_BUS 0x00ff0000U +#define PCI_CONF1_ENABLE BIT(31) + +/** + * pci_conf0_addr - PCI Base Configuration Space address for Type 0 access + * @devfn: Device and function numbers (device number will be ignored) + * @reg: Base configuration space offset + * + * Calculates the PCI Configuration Space address for Type 0 accesses. + * + * Note: the caller is responsible for adding the bits outside of [10:0]. + * + * Return: Base Configuration Space address. + */ +static inline u32 pci_conf0_addr(u8 devfn, u8 reg) +{ + return FIELD_PREP(PCI_CONF_FUNC, PCI_FUNC(devfn)) | + FIELD_PREP(PCI_CONF_REG, reg & ~3); +} + +/** + * pci_conf1_addr - PCI Base Configuration Space address for Type 1 access + * @bus: Bus number of the device + * @devfn: Device and function numbers + * @reg: Base configuration space offset + * @enable: Assert enable bit (bit 31) + * + * Calculates the PCI Base Configuration Space (first 256 bytes) address f= or + * Type 1 accesses. + * + * Note: the caller is responsible for adding the bits outside of [24:2] + * and enable bit. + * + * Return: PCI Base Configuration Space address. + */ +static inline u32 pci_conf1_addr(u8 bus, u8 devfn, u8 reg, bool enable) +{ + return (enable ? PCI_CONF1_ENABLE : 0) | + FIELD_PREP(PCI_CONF1_BUS, bus) | + FIELD_PREP(PCI_CONF1_DEV | PCI_CONF_FUNC, devfn) | + FIELD_PREP(PCI_CONF_REG, reg & ~3); +} + +/* + * Extension of PCI Config Address for accessing extended PCIe registers + * + * No standardized specification, but used on lot of non-ECAM-compliant AR= M SoCs + * or on AMD Barcelona and new CPUs. Reserved bits [27:24] of PCI Config A= ddress + * are used for specifying additional 4 high bits of PCI Express register. + */ +#define PCI_CONF1_EXT_REG 0x0f000000UL + +/** + * pci_conf1_ext_addr - PCI Configuration Space address for Type 1 access + * @bus: Bus number of the device + * @devfn: Device and function numbers + * @reg: Base or Extended Configuration space offset + * @enable: Assert enable bit (bit 31) + * + * Calculates the PCI Base and Extended (4096 bytes per PCI function) + * Configuration Space address for Type 1 accesses. This function assumes + * the Extended Conguration Space is using the reserved bits [27:24]. + * + * Note: the caller is responsible for adding the bits outside of [27:2] a= nd + * enable bit. + * + * Return: PCI Configuration Space address. + */ +static inline u32 pci_conf1_ext_addr(u8 bus, u8 devfn, u16 reg, bool enabl= e) +{ + return FIELD_PREP(PCI_CONF1_EXT_REG, (reg & 0xf00) >> 8) | + pci_conf1_addr(bus, devfn, reg & 0xff, enable); +} + /* Generic PCI functions exported to card drivers */ =20 u8 pci_bus_find_capability(struct pci_bus *bus, unsigned int devfn, int ca= p); --=20 2.39.2 From nobody Fri Dec 19 02:55:22 2025 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.21]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D07273BBF9; Mon, 29 Apr 2024 10:47:13 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.21 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1714387635; cv=none; b=BkPGa1yV1TWbshwZ5wIrOY6S3j43Ng1Xvc83zLSlqNpNWGa7ePCi7bSgP6028R1ULQGeHzxMiQ9b2/qXaoePtGWPz9ybc3iVC/lcTG9aBzc1vglK8rVF5FLjcncLMNv2xqAny7nJsjsTtsFPs3gFRH04cK8brRIRvZjz5vkTnuE= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1714387635; c=relaxed/simple; bh=WdCmZ4jx3b0oIOMBkGiXkCJsrYOJWNmYImReokvOXZQ=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version:Content-Type; b=FSgqngpuU+X6UfNySG1SYNufGRaXtas3OIY6N+d8kLddKSIT3HU4FpNu0HC69ylTOJWtReLxC34f7/UOEvzcjFZKA4szbUZsEgz9D5FkBJvYC4zZ/s2d7rq7XBMw9D3lJyBI8nS0SKmhCZLKEPmaok+ZU0H7AjryXbSyMJa7YDo= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com; spf=none smtp.mailfrom=linux.intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=J7UnnBF+; arc=none smtp.client-ip=198.175.65.21 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; spf=none smtp.mailfrom=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="J7UnnBF+" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1714387634; x=1745923634; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=WdCmZ4jx3b0oIOMBkGiXkCJsrYOJWNmYImReokvOXZQ=; b=J7UnnBF+OB6LPuz/RbN/V82c7J7ibI0fH1XjOO7HExeMN0csQuYfRWGo KNj+pSIXaRLnOWgk/tbX1AAdMKVriH41L7WGgoSr7FWT2dwIyVtA9MS9Z ABOVHoLcnPCWfBVbGorRCv5msQTfenO+MABLlRHVUqcZzbqFHJBI1dbZv unuysnzYIrfEGPSwALq1mjkaLbQuAKdJIH0QXkwbe6WLbDeycLQC1WaeB jvV+Y3hfISV/NiilJ3ppRHnZOrksgb9K2VDsMO/99A32IGz5hLHq085NY l85pp31s3I/N2qse2/YJArVMRPwzvL1Nj/cRIA/KK+aQEXOp/4Oge3YVN Q==; X-CSE-ConnectionGUID: piFqYSDxTOW3vNEYNZEA5Q== X-CSE-MsgGUID: 6eWig0gpRDaZfCn9DXVhPw== X-IronPort-AV: E=McAfee;i="6600,9927,11057"; a="9966393" X-IronPort-AV: E=Sophos;i="6.07,239,1708416000"; d="scan'208";a="9966393" Received: from fmviesa009.fm.intel.com ([10.60.135.149]) by orvoesa113.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 29 Apr 2024 03:47:13 -0700 X-CSE-ConnectionGUID: stDX6XgTSJuv+E6+WewvQg== X-CSE-MsgGUID: rEQrG+G5SKmYxHUm7cDUyA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.07,239,1708416000"; d="scan'208";a="26037436" Received: from ijarvine-desk1.ger.corp.intel.com (HELO localhost) ([10.245.247.45]) by fmviesa009-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 29 Apr 2024 03:47:09 -0700 From: =?UTF-8?q?Ilpo=20J=C3=A4rvinen?= To: linux-pci@vger.kernel.org, Bjorn Helgaas , Lorenzo Pieralisi , Rob Herring , =?UTF-8?q?Krzysztof=20Wilczy=C5=84ski?= , Andrew Lunn , Sebastian Hesselbarth , Gregory Clement , Russell King , linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Cc: =?UTF-8?q?Ilpo=20J=C3=A4rvinen?= Subject: [PATCH 03/10] ARM: orion5x: Pass devfn to orion5x_pci_hw_{rd,wr}_conf() Date: Mon, 29 Apr 2024 13:46:26 +0300 Message-Id: <20240429104633.11060-4-ilpo.jarvinen@linux.intel.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20240429104633.11060-1-ilpo.jarvinen@linux.intel.com> References: <20240429104633.11060-1-ilpo.jarvinen@linux.intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Pass the usual devfn instead of individual components into orion5x_pci_hw_{rd,wr}_conf() to make the change into pci_conf1_offset() in an upcoming commit easier. Signed-off-by: Ilpo J=C3=A4rvinen Acked-by: Gregory CLEMENT Reviewed-by: Andrew Lunn --- arch/arm/mach-orion5x/pci.c | 45 +++++++++++++++++++------------------ 1 file changed, 23 insertions(+), 22 deletions(-) diff --git a/arch/arm/mach-orion5x/pci.c b/arch/arm/mach-orion5x/pci.c index 77ddab90f448..6376e1db6386 100644 --- a/arch/arm/mach-orion5x/pci.c +++ b/arch/arm/mach-orion5x/pci.c @@ -270,15 +270,15 @@ static int orion5x_pci_local_bus_nr(void) return((conf & PCI_P2P_BUS_MASK) >> PCI_P2P_BUS_OFFS); } =20 -static int orion5x_pci_hw_rd_conf(int bus, int dev, u32 func, - u32 where, u32 size, u32 *val) +static int orion5x_pci_hw_rd_conf(int bus, u8 devfn, u32 where, + u32 size, u32 *val) { unsigned long flags; spin_lock_irqsave(&orion5x_pci_lock, flags); =20 writel(PCI_CONF_BUS(bus) | - PCI_CONF_DEV(dev) | ORION5X_PCI_CONF_REG(where) | - ORION5X_PCI_CONF_FUNC(func) | PCI_CONF_ADDR_EN, PCI_CONF_ADDR); + PCI_CONF_DEV(PCI_SLOT(devfn)) | ORION5X_PCI_CONF_REG(where) | + ORION5X_PCI_CONF_FUNC(PCI_FUNC(devfn)) | PCI_CONF_ADDR_EN, PCI_CONF_ADDR= ); =20 *val =3D readl(PCI_CONF_DATA); =20 @@ -292,8 +292,8 @@ static int orion5x_pci_hw_rd_conf(int bus, int dev, u32= func, return PCIBIOS_SUCCESSFUL; } =20 -static int orion5x_pci_hw_wr_conf(int bus, int dev, u32 func, - u32 where, u32 size, u32 val) +static int orion5x_pci_hw_wr_conf(int bus, u8 devfn, u32 where, + u32 size, u32 val) { unsigned long flags; int ret =3D PCIBIOS_SUCCESSFUL; @@ -301,8 +301,8 @@ static int orion5x_pci_hw_wr_conf(int bus, int dev, u32= func, spin_lock_irqsave(&orion5x_pci_lock, flags); =20 writel(PCI_CONF_BUS(bus) | - PCI_CONF_DEV(dev) | ORION5X_PCI_CONF_REG(where) | - ORION5X_PCI_CONF_FUNC(func) | PCI_CONF_ADDR_EN, PCI_CONF_ADDR); + PCI_CONF_DEV(PCI_SLOT(devfn)) | ORION5X_PCI_CONF_REG(where) | + ORION5X_PCI_CONF_FUNC(PCI_FUNC(devfn)) | PCI_CONF_ADDR_EN, PCI_CONF_ADDR= ); =20 if (size =3D=3D 4) { __raw_writel(val, PCI_CONF_DATA); @@ -347,8 +347,7 @@ static int orion5x_pci_rd_conf(struct pci_bus *bus, u32= devfn, return PCIBIOS_DEVICE_NOT_FOUND; } =20 - return orion5x_pci_hw_rd_conf(bus->number, PCI_SLOT(devfn), - PCI_FUNC(devfn), where, size, val); + return orion5x_pci_hw_rd_conf(bus->number, devfn, where, size, val); } =20 static int orion5x_pci_wr_conf(struct pci_bus *bus, u32 devfn, @@ -357,8 +356,7 @@ static int orion5x_pci_wr_conf(struct pci_bus *bus, u32= devfn, if (!orion5x_pci_valid_config(bus->number, devfn)) return PCIBIOS_DEVICE_NOT_FOUND; =20 - return orion5x_pci_hw_wr_conf(bus->number, PCI_SLOT(devfn), - PCI_FUNC(devfn), where, size, val); + return orion5x_pci_hw_wr_conf(bus->number, devfn, where, size, val); } =20 static struct pci_ops pci_ops =3D { @@ -375,12 +373,14 @@ static void __init orion5x_pci_set_bus_nr(int nr) * PCI-X mode */ u32 pcix_status, bus, dev; + u8 devfn; bus =3D (p2p & PCI_P2P_BUS_MASK) >> PCI_P2P_BUS_OFFS; dev =3D (p2p & PCI_P2P_DEV_MASK) >> PCI_P2P_DEV_OFFS; - orion5x_pci_hw_rd_conf(bus, dev, 0, PCIX_STAT, 4, &pcix_status); + devfn =3D PCI_DEVFN(dev, 0); + orion5x_pci_hw_rd_conf(bus, devfn, PCIX_STAT, 4, &pcix_status); pcix_status &=3D ~PCIX_STAT_BUS_MASK; pcix_status |=3D (nr << PCIX_STAT_BUS_OFFS); - orion5x_pci_hw_wr_conf(bus, dev, 0, PCIX_STAT, 4, pcix_status); + orion5x_pci_hw_wr_conf(bus, devfn, PCIX_STAT, 4, pcix_status); } else { /* * PCI Conventional mode @@ -393,15 +393,16 @@ static void __init orion5x_pci_set_bus_nr(int nr) =20 static void __init orion5x_pci_master_slave_enable(void) { - int bus_nr, func, reg; + int bus_nr, reg; + u8 devfn; u32 val; =20 bus_nr =3D orion5x_pci_local_bus_nr(); - func =3D PCI_CONF_FUNC_STAT_CMD; + devfn =3D PCI_DEVFN(0, PCI_CONF_FUNC_STAT_CMD); reg =3D PCI_CONF_REG_STAT_CMD; - orion5x_pci_hw_rd_conf(bus_nr, 0, func, reg, 4, &val); + orion5x_pci_hw_rd_conf(bus_nr, devfn, reg, 4, &val); val |=3D (PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER); - orion5x_pci_hw_wr_conf(bus_nr, 0, func, reg, 4, val | 0x7); + orion5x_pci_hw_wr_conf(bus_nr, devfn, reg, 4, val | 0x7); } =20 static void __init orion5x_setup_pci_wins(void) @@ -424,7 +425,7 @@ static void __init orion5x_setup_pci_wins(void) =20 for (i =3D 0; i < dram->num_cs; i++) { const struct mbus_dram_window *cs =3D dram->cs + i; - u32 func =3D PCI_CONF_FUNC_BAR_CS(cs->cs_index); + u8 devfn =3D PCI_DEVFN(0, PCI_CONF_FUNC_BAR_CS(cs->cs_index)); u32 reg; u32 val; =20 @@ -432,15 +433,15 @@ static void __init orion5x_setup_pci_wins(void) * Write DRAM bank base address register. */ reg =3D PCI_CONF_REG_BAR_LO_CS(cs->cs_index); - orion5x_pci_hw_rd_conf(bus, 0, func, reg, 4, &val); + orion5x_pci_hw_rd_conf(bus, devfn, reg, 4, &val); val =3D (cs->base & 0xfffff000) | (val & 0xfff); - orion5x_pci_hw_wr_conf(bus, 0, func, reg, 4, val); + orion5x_pci_hw_wr_conf(bus, devfn, reg, 4, val); =20 /* * Write DRAM bank size register. */ reg =3D PCI_CONF_REG_BAR_HI_CS(cs->cs_index); - orion5x_pci_hw_wr_conf(bus, 0, func, reg, 4, 0); + orion5x_pci_hw_wr_conf(bus, devfn, reg, 4, 0); writel((cs->size - 1) & 0xfffff000, PCI_BAR_SIZE_DDR_CS(cs->cs_index)); writel(cs->base & 0xfffff000, --=20 2.39.2 From nobody Fri Dec 19 02:55:22 2025 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.21]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id BC8B539AC7; Mon, 29 Apr 2024 10:47:21 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.21 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1714387643; cv=none; b=e4pTWmeMCBy6wx8KUg2WyQdL2acq2fW+89Pi2hCB0KoQVbH1nMOP9Ldl2ioZraPHEE3qsDeOcRmPkn8kmoXSxtDjA8FaIgkvY4nRwCVft6r3vtG8V8fk/vSDeG5xzD7CSmOIeW+Org0FL4dEhXVx394G4+1+TXFqskZb1S6InWM= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1714387643; c=relaxed/simple; bh=xm79CcWQkryZA5hqm6JEw6+gJt6rJs0jHDkc/Fm0Kvo=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version:Content-Type; b=PMkCPamOIaZciajlXTZUehtyCBPm+9i2AakerHu2nVKu2k6AV7/CGMwmBPsfiS7O3GbPvsSYzgEHf6/OJOiPwADW7ek1SEmah7vprQJ26EwxlITeiA7U5vkx60RwBgqSE4kBBG72vNKD+tiLsZMu9XqRRPJA5Cz8Qn+9zozARFg= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com; spf=none smtp.mailfrom=linux.intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=Qu3vcQ5U; arc=none smtp.client-ip=198.175.65.21 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; spf=none smtp.mailfrom=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="Qu3vcQ5U" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1714387642; x=1745923642; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=xm79CcWQkryZA5hqm6JEw6+gJt6rJs0jHDkc/Fm0Kvo=; b=Qu3vcQ5UG/cmqwNXpYZe7J/1dzkv/nGko92CM2YZCtuhfNbxAnRv4zgM /+fPjCgG41S60LisqFNIDBbrbgewYVQa6UJrFd/Huqqc626xD9/VLH3mB uk6A1yGvlk2OI6vkFsUJLE5/Z4s1oDqhrgEB3/+Jdeq0xfIR/L+s6s+An 5LPxbIYMNLSQ048cmQyTsJ2rKPq5kIz//eiFFu+wQmWs1TVESTdbbeVBR 5Wu3yAZhJbG52I1JLGeAxYzDUIBldUJqAcLwqOm/3w77MZt2Qrg8SuopW cyDtp1XqYk/q1ug8IRbyUFO1DrttgoIltbM9ElGnwcnWl/pAF7UXdADA5 A==; X-CSE-ConnectionGUID: wDQjT4U1T7SbMyjplIAeFQ== X-CSE-MsgGUID: DxJIkC6lQjesVH6XCElxqg== X-IronPort-AV: E=McAfee;i="6600,9927,11057"; a="9966408" X-IronPort-AV: E=Sophos;i="6.07,239,1708416000"; d="scan'208";a="9966408" Received: from fmviesa009.fm.intel.com ([10.60.135.149]) by orvoesa113.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 29 Apr 2024 03:47:21 -0700 X-CSE-ConnectionGUID: 4DvHrAC2QZakeUA59jFLEA== X-CSE-MsgGUID: d/YhKH28ScaMZhNP8uPcwQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.07,239,1708416000"; d="scan'208";a="26037455" Received: from ijarvine-desk1.ger.corp.intel.com (HELO localhost) ([10.245.247.45]) by fmviesa009-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 29 Apr 2024 03:47:18 -0700 From: =?UTF-8?q?Ilpo=20J=C3=A4rvinen?= To: linux-pci@vger.kernel.org, Bjorn Helgaas , Lorenzo Pieralisi , Rob Herring , =?UTF-8?q?Krzysztof=20Wilczy=C5=84ski?= , Andrew Lunn , Sebastian Hesselbarth , Gregory Clement , Russell King , linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Cc: =?UTF-8?q?Ilpo=20J=C3=A4rvinen?= Subject: [PATCH 04/10] ARM: orion5x: Use generic PCI Conf Type 1 helper Date: Mon, 29 Apr 2024 13:46:27 +0300 Message-Id: <20240429104633.11060-5-ilpo.jarvinen@linux.intel.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20240429104633.11060-1-ilpo.jarvinen@linux.intel.com> References: <20240429104633.11060-1-ilpo.jarvinen@linux.intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Convert orion5x PCI code to use pci_conf1_ext_addr() from PCI core to calculate PCI Configuration Type 1 address. Signed-off-by: Ilpo J=C3=A4rvinen Acked-by: Gregory CLEMENT --- arch/arm/mach-orion5x/pci.c | 17 ++--------------- 1 file changed, 2 insertions(+), 15 deletions(-) diff --git a/arch/arm/mach-orion5x/pci.c b/arch/arm/mach-orion5x/pci.c index 6376e1db6386..8b7d67549adf 100644 --- a/arch/arm/mach-orion5x/pci.c +++ b/arch/arm/mach-orion5x/pci.c @@ -216,15 +216,6 @@ static int __init pcie_setup(struct pci_sys_data *sys) #define PCI_P2P_DEV_OFFS 24 #define PCI_P2P_DEV_MASK (0x1f << PCI_P2P_DEV_OFFS) =20 -/* - * PCI_CONF_ADDR bits - */ -#define ORION5X_PCI_CONF_REG(reg) ((reg) & 0xfc) -#define ORION5X_PCI_CONF_FUNC(func) (((func) & 0x3) << 8) -#define PCI_CONF_DEV(dev) (((dev) & 0x1f) << 11) -#define PCI_CONF_BUS(bus) (((bus) & 0xff) << 16) -#define PCI_CONF_ADDR_EN (1 << 31) - /* * Internal configuration space */ @@ -276,9 +267,7 @@ static int orion5x_pci_hw_rd_conf(int bus, u8 devfn, u3= 2 where, unsigned long flags; spin_lock_irqsave(&orion5x_pci_lock, flags); =20 - writel(PCI_CONF_BUS(bus) | - PCI_CONF_DEV(PCI_SLOT(devfn)) | ORION5X_PCI_CONF_REG(where) | - ORION5X_PCI_CONF_FUNC(PCI_FUNC(devfn)) | PCI_CONF_ADDR_EN, PCI_CONF_ADDR= ); + writel(pci_conf1_addr(bus, devfn, where, true), PCI_CONF_ADDR); =20 *val =3D readl(PCI_CONF_DATA); =20 @@ -300,9 +289,7 @@ static int orion5x_pci_hw_wr_conf(int bus, u8 devfn, u3= 2 where, =20 spin_lock_irqsave(&orion5x_pci_lock, flags); =20 - writel(PCI_CONF_BUS(bus) | - PCI_CONF_DEV(PCI_SLOT(devfn)) | ORION5X_PCI_CONF_REG(where) | - ORION5X_PCI_CONF_FUNC(PCI_FUNC(devfn)) | PCI_CONF_ADDR_EN, PCI_CONF_ADDR= ); + writel(pci_conf1_addr(bus, devfn, where, true), PCI_CONF_ADDR); =20 if (size =3D=3D 4) { __raw_writel(val, PCI_CONF_DATA); --=20 2.39.2 From nobody Fri Dec 19 02:55:22 2025 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.21]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 0C6303F8DE; Mon, 29 Apr 2024 10:47:29 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.21 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1714387651; cv=none; b=TipEkuDuB2cSSG2rI9D2YU93Tz8gNVOCjVkgZ/TjCjT1y3ntMuM+YsKjOb9kuvNZBtGymahWWmCpE7R6ADYriwgMc+VdWPV0s5Pg0CVJT30NeSAbvQnL73X2ll5+lI/eBfjTPMbDJ90CDuPANvBKyecBIDLLu7Uejwd8qH3GkGM= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1714387651; c=relaxed/simple; bh=Hv9GyAS0KBbDT8QkEmIsUuVpOXGR/BLCaX7u38Yg14I=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version:Content-Type; b=eLlWdzL15kDp59IwOAX0vX5ZdawuC+ZviRgz/8Ff3xeY+20wCnjchtAZOD/7C857xGFRlJrJG+ZictEgaT1i4Pp1WFtfMI6MZNRL4WRFGIuCJEivzKWr4vGVx8Z9OjZrdtHnmMoZoNNRP0LYmwcx3J9UACZ3AhrzrpK0QN73HZ0= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com; spf=none smtp.mailfrom=linux.intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=J3sGDOe6; arc=none smtp.client-ip=198.175.65.21 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; spf=none smtp.mailfrom=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="J3sGDOe6" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1714387650; x=1745923650; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=Hv9GyAS0KBbDT8QkEmIsUuVpOXGR/BLCaX7u38Yg14I=; b=J3sGDOe6PGufggvz79bBM4DiXD+KlgGmMLfNEJY7mU7H+XGlE2/kfaRs N5nHrk4WU9ZO4ZUDwNSpkWRsw4nbFdGz2BoUad1JEK+bfgGuGZA1PBodU 1hUYpNZxX1QtW5YKhlECKNfo4oLMsjIsV7u0zSUYqhml+I/bfitz6Tirp TQBNYb+4PtzkLjLUKiwzeWzKJ16jPCVQg0A3AgCRq7SKfEK0lKiVno2m8 TX8PsmVJCXlj584aaHS3dKBZzk5q+FCK9wAWkpy3CPFJoEqlZmQOUS6MS EdEUxeLn59NVyrdXbnr3Vok12x/zGSzVjQ5RWxsr86CUkxLN96Xpu9aFN g==; X-CSE-ConnectionGUID: quk2ILq0SyasmrmSVZCgBw== X-CSE-MsgGUID: tS55weukSeGY+J50V5JpsA== X-IronPort-AV: E=McAfee;i="6600,9927,11057"; a="9966431" X-IronPort-AV: E=Sophos;i="6.07,239,1708416000"; d="scan'208";a="9966431" Received: from fmviesa009.fm.intel.com ([10.60.135.149]) by orvoesa113.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 29 Apr 2024 03:47:30 -0700 X-CSE-ConnectionGUID: TpdIB9STR46fUwIXJHCNnQ== X-CSE-MsgGUID: iuWN04UaTO+9rByUaag7oQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.07,239,1708416000"; d="scan'208";a="26037489" Received: from ijarvine-desk1.ger.corp.intel.com (HELO localhost) ([10.245.247.45]) by fmviesa009-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 29 Apr 2024 03:47:26 -0700 From: =?UTF-8?q?Ilpo=20J=C3=A4rvinen?= To: linux-pci@vger.kernel.org, Bjorn Helgaas , Lorenzo Pieralisi , Rob Herring , =?UTF-8?q?Krzysztof=20Wilczy=C5=84ski?= , Linus Walleij , Lorenzo Pieralisi , linux-kernel@vger.kernel.org Cc: =?UTF-8?q?Ilpo=20J=C3=A4rvinen?= Subject: [PATCH 05/10] PCI: ixp4xx: Use generic PCI Conf Type 0 helper Date: Mon, 29 Apr 2024 13:46:28 +0300 Message-Id: <20240429104633.11060-6-ilpo.jarvinen@linux.intel.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20240429104633.11060-1-ilpo.jarvinen@linux.intel.com> References: <20240429104633.11060-1-ilpo.jarvinen@linux.intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Convert Type 0 address calculation to use pci_conf0_offset() instead of abusing PCI_CONF1_ADDRESS(). Signed-off-by: Ilpo J=C3=A4rvinen Reviewed-by: Linus Walleij --- drivers/pci/controller/pci-ixp4xx.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/pci/controller/pci-ixp4xx.c b/drivers/pci/controller/p= ci-ixp4xx.c index acb85e0d5675..44639838df9c 100644 --- a/drivers/pci/controller/pci-ixp4xx.c +++ b/drivers/pci/controller/pci-ixp4xx.c @@ -188,8 +188,8 @@ static u32 ixp4xx_config_addr(u8 bus_num, u16 devfn, in= t where) /* Root bus is always 0 in this hardware */ if (bus_num =3D=3D 0) { /* type 0 */ - return (PCI_CONF1_ADDRESS(0, 0, PCI_FUNC(devfn), where) & - ~PCI_CONF1_ENABLE) | BIT(32-PCI_SLOT(devfn)); + return pci_conf0_addr(devfn, where) | + BIT(32 - PCI_SLOT(devfn)); } else { /* type 1 */ return (PCI_CONF1_ADDRESS(bus_num, PCI_SLOT(devfn), --=20 2.39.2 From nobody Fri Dec 19 02:55:22 2025 Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.8]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 9CFEB3B1AA; Mon, 29 Apr 2024 10:47:38 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=192.198.163.8 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1714387660; cv=none; b=vFg6o3dx3XFg5nxW5moV8mClwMzcuUz7um+LB2rtg2olZU/Gd4hKtsJNy0uGqhlDsvG3cwZ1InPTWgHRfXI0vDteoLESyM8mBf2KgWvwwaJp1S+hisWWSeZY8cIE1KRBWeIYPLMQdcahWTL+rd6TtutIgpYU6BnA6pAOiPCr4V4= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1714387660; c=relaxed/simple; bh=Wc916WtLXl32fK/4WeXrrKL3Hri/FYOhOpr0WIpoRgU=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version:Content-Type; b=qD3ush3We6HsOt2RrgK5CSMkqiUeHUfirwcVP2Hc3O9ukMPCGVQ8EbLX4jNWJO0H88ZhKK/F0nUw2omw7ttym/mFrYfR90EzAFn1xjv0uyN1G0N1bIEPkUbj/tbcyu1VFk5T/b2peXxaGF2HNnvmEisMiAao+6pgnFsbJD4XOpY= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com; spf=none smtp.mailfrom=linux.intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=hSoAbYLz; arc=none smtp.client-ip=192.198.163.8 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; spf=none smtp.mailfrom=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="hSoAbYLz" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1714387658; x=1745923658; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=Wc916WtLXl32fK/4WeXrrKL3Hri/FYOhOpr0WIpoRgU=; b=hSoAbYLzCoQDLKgkwqA9ZORLRXn3e/UKeHzqJsxwDi6JqhbfsyDaO3cz fLBWWqo1UzbcdwLgTJu122Wi4QjDq7P9y/HCuNd8RMg2Q8tz/4rSxmWzr 8MDL9c0tXWEknG7lhXSD0NrsVNN7glkVZL0GHgZNXi3iEOwO51gjAac0H cXWrPz12EIoTxQHFk3Cmqohu+VKhqDFzr6mkyk4XIgQHiEov75RuLrfLs 7oVpcRt6JMV3J1J6Am22f/hMaBfNq5M/asAH1Otg2sYUoZ+QylLYtFAXF 0EfuT+ar6PUDe5yy7BYdHzdr0zZUaE2qmtvnCS+qh6lJ/o/HJgyMqu5cl A==; X-CSE-ConnectionGUID: 3qFg9pUMTme0Q6saKGACLQ== X-CSE-MsgGUID: J9BfgjE+S6m2QRBL9fpssQ== X-IronPort-AV: E=McAfee;i="6600,9927,11057"; a="27558986" X-IronPort-AV: E=Sophos;i="6.07,239,1708416000"; d="scan'208";a="27558986" Received: from orviesa004.jf.intel.com ([10.64.159.144]) by fmvoesa102.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 29 Apr 2024 03:47:38 -0700 X-CSE-ConnectionGUID: TIoj9xeOS469TRfuYgY/TQ== X-CSE-MsgGUID: gWr1b7dpS1ObYa3kQl/YNg== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.07,239,1708416000"; d="scan'208";a="30896766" Received: from ijarvine-desk1.ger.corp.intel.com (HELO localhost) ([10.245.247.45]) by orviesa004-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 29 Apr 2024 03:47:35 -0700 From: =?UTF-8?q?Ilpo=20J=C3=A4rvinen?= To: linux-pci@vger.kernel.org, Bjorn Helgaas , Lorenzo Pieralisi , Rob Herring , =?UTF-8?q?Krzysztof=20Wilczy=C5=84ski?= , Linus Walleij , Lorenzo Pieralisi , linux-kernel@vger.kernel.org Cc: =?UTF-8?q?Ilpo=20J=C3=A4rvinen?= Subject: [PATCH 06/10] PCI: ixp4xx: Replace 1 with PCI_CONF1_TRANSACTION Date: Mon, 29 Apr 2024 13:46:29 +0300 Message-Id: <20240429104633.11060-7-ilpo.jarvinen@linux.intel.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20240429104633.11060-1-ilpo.jarvinen@linux.intel.com> References: <20240429104633.11060-1-ilpo.jarvinen@linux.intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Add PCI_CONF1_TRANSACTION and replace literal 1 within PCI Configuration Space Type 1 address with it. Signed-off-by: Ilpo J=C3=A4rvinen Reviewed-by: Linus Walleij --- drivers/pci/controller/pci-ixp4xx.c | 2 +- include/linux/pci.h | 1 + 2 files changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/pci/controller/pci-ixp4xx.c b/drivers/pci/controller/p= ci-ixp4xx.c index 44639838df9c..ec0125344ca1 100644 --- a/drivers/pci/controller/pci-ixp4xx.c +++ b/drivers/pci/controller/pci-ixp4xx.c @@ -194,7 +194,7 @@ static u32 ixp4xx_config_addr(u8 bus_num, u16 devfn, in= t where) /* type 1 */ return (PCI_CONF1_ADDRESS(bus_num, PCI_SLOT(devfn), PCI_FUNC(devfn), where) & - ~PCI_CONF1_ENABLE) | 1; + ~PCI_CONF1_ENABLE) | PCI_CONF1_TRANSACTION; } } =20 diff --git a/include/linux/pci.h b/include/linux/pci.h index 4c4e3bb52a0a..df613428bc4d 100644 --- a/include/linux/pci.h +++ b/include/linux/pci.h @@ -1191,6 +1191,7 @@ void pci_sort_breadthfirst(void); * See PCI Local Bus Specification, Revision 3.0, * Section 3.2.2.3.2, Figure 3-1 and 3-2, p. 48-50. */ +#define PCI_CONF1_TRANSACTION BIT(0) #define PCI_CONF_REG 0x000000ffU /* common for Type 0/1 */ #define PCI_CONF_FUNC 0x00000700U /* common for Type 0/1 */ #define PCI_CONF1_DEV 0x0000f800U --=20 2.39.2 From nobody Fri Dec 19 02:55:22 2025 Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.15]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 9723439FFD; Mon, 29 Apr 2024 10:47:49 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=192.198.163.15 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1714387671; cv=none; b=pDC6MB05oCOlvB2rkoNXi5OKCOM6qYFp4m2usf5pDzSellNF5aoGz+yp9h3l4gUt/vZsDUJhD3WIRxLdRsi+t/3oIuzSbbfpvBx5bPqTC1AFRum4AExfT+l2Ljz5VwmvwebfJ4DEEdw8soKjaKH5uvuEB3zPqppdLru5XWi9LsI= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1714387671; c=relaxed/simple; bh=6Mc4DmXEXO6Kz1kJ/fVcR7ZcfLPUG4RYhvrVnAwaq+0=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version:Content-Type; b=snZqe2ZMeW8Bcgiafr4HOiLmTGzKRmx2wzk4z3zTw4dOSusXyNOOSQvOKvcbmtebAoG6AJhQfIbMaXzlt3CdZ0yr85Vd1Lx56CdKbWvyWAn1+ForNJcTZ1sY8KMkQYwGuQ1h/xqczVZZ6DTj2XF7gdsMM0HBVaelNJRJuZDBMiM= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com; spf=none smtp.mailfrom=linux.intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=nGn8u6PF; arc=none smtp.client-ip=192.198.163.15 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; spf=none smtp.mailfrom=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="nGn8u6PF" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1714387670; x=1745923670; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=6Mc4DmXEXO6Kz1kJ/fVcR7ZcfLPUG4RYhvrVnAwaq+0=; b=nGn8u6PFD9V+x8+C+PTitC8kIEN5+owjLW5/bpEidY9ooB/TrgYAaMI/ xYPLAsGiaHPjcBXrltJ4YwxwpV2HzMlzHRSUa3dUXfqyH1BVvIYNFVDKP hspiLdiynFC68rmOld2Gvp6GtAc3WGQj9YzKc418+R3Ma/Nw8ZE57p/RR J7VSKpZtyhvqx0M3JE1nZgtUsecCjkFE5PdfpbicesvbLwJVfhVgiFEJ1 cCSsTY08sGC6Z8E8jvrylWAcP7UXjarVtEK6f3yURSoPpDGQF+J1sagkl G0cd/FiVfcK3j/s+HEZ2uPUz+K4mXyjKnu+SMSId/66vy2bEuFRb0RSQO w==; X-CSE-ConnectionGUID: KW/h/wAWTKGMWsbNa4lgdw== X-CSE-MsgGUID: IhjGo+7lSLeZx6JRMYwkzQ== X-IronPort-AV: E=McAfee;i="6600,9927,11057"; a="10201841" X-IronPort-AV: E=Sophos;i="6.07,239,1708416000"; d="scan'208";a="10201841" Received: from orviesa007.jf.intel.com ([10.64.159.147]) by fmvoesa109.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 29 Apr 2024 03:47:49 -0700 X-CSE-ConnectionGUID: /nnKB6kaSHeZOlfWFHxV8w== X-CSE-MsgGUID: k64qq1ZHTVWYmwqvHsqZzA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.07,239,1708416000"; d="scan'208";a="26589567" Received: from ijarvine-desk1.ger.corp.intel.com (HELO localhost) ([10.245.247.45]) by orviesa007-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 29 Apr 2024 03:47:44 -0700 From: =?UTF-8?q?Ilpo=20J=C3=A4rvinen?= To: linux-pci@vger.kernel.org, Bjorn Helgaas , Lorenzo Pieralisi , Rob Herring , =?UTF-8?q?Krzysztof=20Wilczy=C5=84ski?= , Lorenzo Pieralisi , Linus Walleij , Sergio Paracuellos , Matthias Brugger , AngeloGioacchino Del Regno , linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org Cc: =?UTF-8?q?Ilpo=20J=C3=A4rvinen?= Subject: [PATCH 07/10] PCI: Replace PCI_CONF1{,_EXT}_ADDRESS() with the new helpers Date: Mon, 29 Apr 2024 13:46:30 +0300 Message-Id: <20240429104633.11060-8-ilpo.jarvinen@linux.intel.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20240429104633.11060-1-ilpo.jarvinen@linux.intel.com> References: <20240429104633.11060-1-ilpo.jarvinen@linux.intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Replace the old PCI_CONF1{,_EXT}_ADDRESS() helpers used to calculate PCI Configuration Space Type 1 addresses with the new pci_conf1{,_ext}_offset() helpers that are more generic and more widely available. Signed-off-by: Ilpo J=C3=A4rvinen Acked-by: Sergio Paracuellos Reviewed-by: Linus Walleij Tested-by: Sergio Paracuellos --- drivers/pci/controller/pci-ftpci100.c | 6 ++---- drivers/pci/controller/pci-ixp4xx.c | 5 ++--- drivers/pci/controller/pcie-mt7621.c | 7 +++---- drivers/pci/pci.h | 8 -------- 4 files changed, 7 insertions(+), 19 deletions(-) diff --git a/drivers/pci/controller/pci-ftpci100.c b/drivers/pci/controller= /pci-ftpci100.c index ffdeed25e961..a8d0217a0b94 100644 --- a/drivers/pci/controller/pci-ftpci100.c +++ b/drivers/pci/controller/pci-ftpci100.c @@ -182,8 +182,7 @@ static int faraday_raw_pci_read_config(struct faraday_p= ci *p, int bus_number, unsigned int fn, int config, int size, u32 *value) { - writel(PCI_CONF1_ADDRESS(bus_number, PCI_SLOT(fn), - PCI_FUNC(fn), config), + writel(pci_conf1_addr(bus_number, fn, config, true), p->base + FTPCI_CONFIG); =20 *value =3D readl(p->base + FTPCI_DATA); @@ -214,8 +213,7 @@ static int faraday_raw_pci_write_config(struct faraday_= pci *p, int bus_number, { int ret =3D PCIBIOS_SUCCESSFUL; =20 - writel(PCI_CONF1_ADDRESS(bus_number, PCI_SLOT(fn), - PCI_FUNC(fn), config), + writel(pci_conf1_addr(bus_number, fn, config, true), p->base + FTPCI_CONFIG); =20 switch (size) { diff --git a/drivers/pci/controller/pci-ixp4xx.c b/drivers/pci/controller/p= ci-ixp4xx.c index ec0125344ca1..fd52f4a3ef31 100644 --- a/drivers/pci/controller/pci-ixp4xx.c +++ b/drivers/pci/controller/pci-ixp4xx.c @@ -192,9 +192,8 @@ static u32 ixp4xx_config_addr(u8 bus_num, u16 devfn, in= t where) BIT(32 - PCI_SLOT(devfn)); } else { /* type 1 */ - return (PCI_CONF1_ADDRESS(bus_num, PCI_SLOT(devfn), - PCI_FUNC(devfn), where) & - ~PCI_CONF1_ENABLE) | PCI_CONF1_TRANSACTION; + return pci_conf1_addr(bus_num, devfn, where, false) | + PCI_CONF1_TRANSACTION; } } =20 diff --git a/drivers/pci/controller/pcie-mt7621.c b/drivers/pci/controller/= pcie-mt7621.c index 79e225edb42a..2b2d9828a910 100644 --- a/drivers/pci/controller/pcie-mt7621.c +++ b/drivers/pci/controller/pcie-mt7621.c @@ -127,8 +127,7 @@ static void __iomem *mt7621_pcie_map_bus(struct pci_bus= *bus, unsigned int devfn, int where) { struct mt7621_pcie *pcie =3D bus->sysdata; - u32 address =3D PCI_CONF1_EXT_ADDRESS(bus->number, PCI_SLOT(devfn), - PCI_FUNC(devfn), where); + u32 address =3D pci_conf1_ext_addr(bus->number, devfn, where, true); =20 writel_relaxed(address, pcie->base + RALINK_PCI_CONFIG_ADDR); =20 @@ -143,7 +142,7 @@ static struct pci_ops mt7621_pcie_ops =3D { =20 static u32 read_config(struct mt7621_pcie *pcie, unsigned int dev, u32 reg) { - u32 address =3D PCI_CONF1_EXT_ADDRESS(0, dev, 0, reg); + u32 address =3D pci_conf1_ext_addr(0, PCI_DEVFN(dev, 0), reg, true); =20 pcie_write(pcie, address, RALINK_PCI_CONFIG_ADDR); return pcie_read(pcie, RALINK_PCI_CONFIG_DATA); @@ -152,7 +151,7 @@ static u32 read_config(struct mt7621_pcie *pcie, unsign= ed int dev, u32 reg) static void write_config(struct mt7621_pcie *pcie, unsigned int dev, u32 reg, u32 val) { - u32 address =3D PCI_CONF1_EXT_ADDRESS(0, dev, 0, reg); + u32 address =3D pci_conf1_ext_addr(0, PCI_DEVFN(dev, 0), reg, true); =20 pcie_write(pcie, address, RALINK_PCI_CONFIG_ADDR); pcie_write(pcie, val, RALINK_PCI_CONFIG_DATA); diff --git a/drivers/pci/pci.h b/drivers/pci/pci.h index cf0530a60105..fdf9624b0b12 100644 --- a/drivers/pci/pci.h +++ b/drivers/pci/pci.h @@ -833,12 +833,4 @@ struct pci_devres { =20 struct pci_devres *find_pci_dr(struct pci_dev *pdev); =20 -#define PCI_CONF1_ADDRESS(bus, dev, func, reg) \ - (PCI_CONF1_ENABLE | \ - pci_conf1_addr(bus, PCI_DEVFN(dev, func), reg & ~0x3U)) - -#define PCI_CONF1_EXT_ADDRESS(bus, dev, func, reg) \ - (PCI_CONF1_ENABLE | \ - pci_conf1_ext_addr(bus, PCI_DEVFN(dev, func), reg & ~0x3U)) - #endif /* DRIVERS_PCI_H */ --=20 2.39.2 From nobody Fri Dec 19 02:55:22 2025 Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.15]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 6D2BB3D969; Mon, 29 Apr 2024 10:47:59 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=192.198.163.15 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1714387680; cv=none; b=J3ho+RsXulMJfA4+a3SBB1K3JerHubQ8iA+xQnBHTezYEQboQyv4rUcgyot8h/o8/vjDTEzHaaQKK0mIkXxnGlE0B8lYi5HFnLC1G/h3AuP5gaVrsIb2dw95MT8t958KabDIKXQbF7yD4/mUdxy3cnKQT0V8FuYi8feNaSjkdHA= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1714387680; c=relaxed/simple; bh=/qjKS1tRau5PVYvMBMsW64xOEOfBMtAi8Dq49OisY+E=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version:Content-Type; b=URuXMUvJb4txMaZNMu2OrN+W+QNf6L5TnZKtbWRk3up/4EJt9rw+BuywDtTeUNjbLN4bFGAm4UlNq6Ne5qIs8V1sP8cOVrDvIWi7nTMjDK9AS8x9nIc4LvIidhXOmxAj63DiGKUTcSC0f1GVeWV+IrylnX1R8yIjDqPcjyBBJas= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com; spf=none smtp.mailfrom=linux.intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=MXaHI2s9; arc=none smtp.client-ip=192.198.163.15 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; spf=none smtp.mailfrom=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="MXaHI2s9" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1714387680; x=1745923680; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=/qjKS1tRau5PVYvMBMsW64xOEOfBMtAi8Dq49OisY+E=; b=MXaHI2s9lYzybNZ7VGtsMyyYt/BDulr8BVJDgNv9e64eWfR2Qbfi1dU6 BElXezv0o/+18x9+fT1/c5lyq/RtoK1wK/ngRXzAVQgMCnx4R1BC4bMbp H6OhVx2QDyqBvb1AJcNtzIe+RWfJydco/FRdLGTT7TN+m9Y/kqLnmoV+j PN580tjiQf5pEtS/9ICIoLvwAFtyG+EvcLxtGBMIhpuy+ZnR+6u/h4RJ1 0ZXyLhIm6vx1egCQ6zqDEFlsg9A2lz3Dv4flbgu21/S2qW1f7vGii3dNL mEYtO/uzVXFwH7btuzNtybQrwO4tO1FXWZAq6T54PpaN2xEbQzspUzYjE g==; X-CSE-ConnectionGUID: ojziekXaTg+l5iaGVWE7+Q== X-CSE-MsgGUID: JwXF3WkRTRW3cxLzoIOXDA== X-IronPort-AV: E=McAfee;i="6600,9927,11057"; a="10201861" X-IronPort-AV: E=Sophos;i="6.07,239,1708416000"; d="scan'208";a="10201861" Received: from orviesa007.jf.intel.com ([10.64.159.147]) by fmvoesa109.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 29 Apr 2024 03:47:59 -0700 X-CSE-ConnectionGUID: 1wCkMPVTRN2RWdOSG3Sqqg== X-CSE-MsgGUID: d8wqhGNfSNSRJnAXcewYnw== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.07,239,1708416000"; d="scan'208";a="26589582" Received: from ijarvine-desk1.ger.corp.intel.com (HELO localhost) ([10.245.247.45]) by orviesa007-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 29 Apr 2024 03:47:55 -0700 From: =?UTF-8?q?Ilpo=20J=C3=A4rvinen?= To: linux-pci@vger.kernel.org, Bjorn Helgaas , Lorenzo Pieralisi , Rob Herring , =?UTF-8?q?Krzysztof=20Wilczy=C5=84ski?= , Thierry Reding , Lorenzo Pieralisi , Jonathan Hunter , linux-tegra@vger.kernel.org, linux-kernel@vger.kernel.org Cc: =?UTF-8?q?Ilpo=20J=C3=A4rvinen?= Subject: [PATCH 08/10] PCI: tegra: Use generic PCI Conf Type 1 helper Date: Mon, 29 Apr 2024 13:46:31 +0300 Message-Id: <20240429104633.11060-9-ilpo.jarvinen@linux.intel.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20240429104633.11060-1-ilpo.jarvinen@linux.intel.com> References: <20240429104633.11060-1-ilpo.jarvinen@linux.intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Convert tegra to use the pci_conf1_ext_addr() helper from PCI core to calculate PCI Configuration Space address for Type 1 access. Signed-off-by: Ilpo J=C3=A4rvinen --- Note: where mask is changed from 0xff -> 0xfc by this change. --- drivers/pci/controller/pci-tegra.c | 12 ++---------- 1 file changed, 2 insertions(+), 10 deletions(-) diff --git a/drivers/pci/controller/pci-tegra.c b/drivers/pci/controller/pc= i-tegra.c index 038d974a318e..a86e88c6b87a 100644 --- a/drivers/pci/controller/pci-tegra.c +++ b/drivers/pci/controller/pci-tegra.c @@ -415,13 +415,6 @@ static inline u32 pads_readl(struct tegra_pcie *pcie, = unsigned long offset) * address (access to which generates correct config transaction) falls in * this 4 KiB region. */ -static unsigned int tegra_pcie_conf_offset(u8 bus, unsigned int devfn, - unsigned int where) -{ - return ((where & 0xf00) << 16) | (bus << 16) | (PCI_SLOT(devfn) << 11) | - (PCI_FUNC(devfn) << 8) | (where & 0xff); -} - static void __iomem *tegra_pcie_map_bus(struct pci_bus *bus, unsigned int devfn, int where) @@ -440,10 +433,9 @@ static void __iomem *tegra_pcie_map_bus(struct pci_bus= *bus, } } } else { - unsigned int offset; - u32 base; + u32 base, offset; =20 - offset =3D tegra_pcie_conf_offset(bus->number, devfn, where); + offset =3D pci_conf1_ext_addr(bus->number, devfn, where, false); =20 /* move 4 KiB window to offset within the FPCI region */ base =3D 0xfe100000 + ((offset & ~(SZ_4K - 1)) >> 8); --=20 2.39.2 From nobody Fri Dec 19 02:55:22 2025 Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.8]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id DD4333B295; Mon, 29 Apr 2024 10:48:08 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=192.198.163.8 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1714387690; cv=none; b=Fo8xaF7NZOTe4+tLpbh0O04/FGYViDgvCL5iWSG1SWmgh4apdDvTfsi7NjGmLReqYfCDftN+woUDScSYeOxsDpNNJMH5y2pQq1vQ9P/0Eg6yleyJngTHFRVg3JHwXyIbU6Np0xvAZ/jWJUfiftaG0eHKTNC3P7CFwSbt4b/SVt0= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1714387690; c=relaxed/simple; bh=tqeeFaSWoH51snX4RlgEW30pWGpLH600kN4A4Ggy4L8=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version:Content-Type; b=Hf2UN4kjXEF7pdy8wQzRkvrV22YG5Fj/bacgfrp8sVGBUm4ECATTDqiQ/BoD+ndL2tI7koiv9lbClS39MpaXBJvt8ovqXI+JgI4htvjvXXnqDIB4ly5K5QhGRCHkS6bXNOkNHuqOYTxNH39v5pGdK1ZDOwVjPAYirltqTfh5oUM= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com; spf=none smtp.mailfrom=linux.intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=KcPGcGF9; arc=none smtp.client-ip=192.198.163.8 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; spf=none smtp.mailfrom=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="KcPGcGF9" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1714387689; x=1745923689; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=tqeeFaSWoH51snX4RlgEW30pWGpLH600kN4A4Ggy4L8=; b=KcPGcGF9gq8eaRkOL5XfzW6QnWGV8QPdZjZIlY5gpBQQBmRhYbdiY88G Igbdu0CGzbKzaDUzy/eG9o4ILTiOFspq3SS4NU9qc2wyK0UuZIT2MyGiV jyKhAyJq2EDrZ+g1PI/IScg/0iVGAKWFLAx6xaQlaps1RszUsEjhV/2K4 8bx3EkVzZCsiB7R5O6DsdHOoS9X+xvOXqGOj4azgfsx55C3YQvNjZyZpT CujcKdF8/8dtRt8vkFAUeWGnFbtNjfobVj4ZZ4HFTX1czxfdKwTu2DGW1 a6Oqgd9giaVURRBRG7v66XOFMDB3GhVznGdy1lYLtRD/pphMA+frX4m5N A==; X-CSE-ConnectionGUID: i4XZuEK3QheesmEM+KMfIw== X-CSE-MsgGUID: vpFNrnG4SLy+Q+h7PEsUPA== X-IronPort-AV: E=McAfee;i="6600,9927,11057"; a="27559079" X-IronPort-AV: E=Sophos;i="6.07,239,1708416000"; d="scan'208";a="27559079" Received: from orviesa004.jf.intel.com ([10.64.159.144]) by fmvoesa102.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 29 Apr 2024 03:48:08 -0700 X-CSE-ConnectionGUID: bOPtYgLLRmirNCTAizYk1Q== X-CSE-MsgGUID: 0IPQ+Z+tQTiB4Q/+A6EYGQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.07,239,1708416000"; d="scan'208";a="30896807" Received: from ijarvine-desk1.ger.corp.intel.com (HELO localhost) ([10.245.247.45]) by orviesa004-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 29 Apr 2024 03:48:04 -0700 From: =?UTF-8?q?Ilpo=20J=C3=A4rvinen?= To: linux-pci@vger.kernel.org, Bjorn Helgaas , Lorenzo Pieralisi , Rob Herring , =?UTF-8?q?Krzysztof=20Wilczy=C5=84ski?= , Thomas Petazzoni , =?UTF-8?q?Pali=20Roh=C3=A1r?= , Lorenzo Pieralisi , linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Cc: =?UTF-8?q?Ilpo=20J=C3=A4rvinen?= Subject: [PATCH 09/10] PCI: mvebu: Use generic PCI Conf Type 1 helper Date: Mon, 29 Apr 2024 13:46:32 +0300 Message-Id: <20240429104633.11060-10-ilpo.jarvinen@linux.intel.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20240429104633.11060-1-ilpo.jarvinen@linux.intel.com> References: <20240429104633.11060-1-ilpo.jarvinen@linux.intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Convert mvebu to use the pci_conf1_ext_addr() helper from PCI core to calculate PCI Configuration Space address for Type 1 access. Signed-off-by: Ilpo J=C3=A4rvinen Tested-by: Andrew Lunn --- drivers/pci/controller/pci-mvebu.c | 13 ++----------- 1 file changed, 2 insertions(+), 11 deletions(-) diff --git a/drivers/pci/controller/pci-mvebu.c b/drivers/pci/controller/pc= i-mvebu.c index 29fe09c99e7d..1908754ee6fd 100644 --- a/drivers/pci/controller/pci-mvebu.c +++ b/drivers/pci/controller/pci-mvebu.c @@ -45,15 +45,6 @@ #define PCIE_WIN5_BASE_OFF 0x1884 #define PCIE_WIN5_REMAP_OFF 0x188c #define PCIE_CONF_ADDR_OFF 0x18f8 -#define PCIE_CONF_ADDR_EN 0x80000000 -#define PCIE_CONF_REG(r) ((((r) & 0xf00) << 16) | ((r) & 0xfc)) -#define PCIE_CONF_BUS(b) (((b) & 0xff) << 16) -#define PCIE_CONF_DEV(d) (((d) & 0x1f) << 11) -#define PCIE_CONF_FUNC(f) (((f) & 0x7) << 8) -#define PCIE_CONF_ADDR(bus, devfn, where) \ - (PCIE_CONF_BUS(bus) | PCIE_CONF_DEV(PCI_SLOT(devfn)) | \ - PCIE_CONF_FUNC(PCI_FUNC(devfn)) | PCIE_CONF_REG(where) | \ - PCIE_CONF_ADDR_EN) #define PCIE_CONF_DATA_OFF 0x18fc #define PCIE_INT_CAUSE_OFF 0x1900 #define PCIE_INT_UNMASK_OFF 0x1910 @@ -361,7 +352,7 @@ static int mvebu_pcie_child_rd_conf(struct pci_bus *bus= , u32 devfn, int where, =20 conf_data =3D port->base + PCIE_CONF_DATA_OFF; =20 - mvebu_writel(port, PCIE_CONF_ADDR(bus->number, devfn, where), + mvebu_writel(port, pci_conf1_ext_addr(bus->number, devfn, where, true), PCIE_CONF_ADDR_OFF); =20 switch (size) { @@ -397,7 +388,7 @@ static int mvebu_pcie_child_wr_conf(struct pci_bus *bus= , u32 devfn, =20 conf_data =3D port->base + PCIE_CONF_DATA_OFF; =20 - mvebu_writel(port, PCIE_CONF_ADDR(bus->number, devfn, where), + mvebu_writel(port, pci_conf1_ext_addr(bus->number, devfn, where, true), PCIE_CONF_ADDR_OFF); =20 switch (size) { --=20 2.39.2 From nobody Fri Dec 19 02:55:22 2025 Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.9]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 537EF3B295; Mon, 29 Apr 2024 10:48:18 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=192.198.163.9 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1714387699; cv=none; b=fxZlOtpDBInA8g7Ynv7kw7KZZby0W+pTOU4XcsJJFAb5iwIph2rvqFEIwQQSqoexpg/sjmc6pSbsZjFQAezZoLVoulU4Ai07mXbxIK3dYQAHVeCZ01ZJ9nUhy90wJmBDB1nzf3muQz8/3roZNZzDHtWTBpCLLZtWdcHy0EwcJY8= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1714387699; c=relaxed/simple; bh=3qNUeNNqvAX2EUpER+BCy2WtfN/wfJPQesC9InOcInY=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version:Content-Type; b=HHgcPBeNGykBdMaKu2FeyTIf1aEP6R8XzrZofGXQ4LVo0LCHLbWsRZQCRIHkkHt7sLDs4L6qEdP54D3UuYlf2p94h2Mb2/Dxqs/ICgDo5nI1qkE707CttCEmbRAVFx3Nw5puxcQOnCHN4FT/BT5NpzOPMDFWRtsia/zPVEGo58M= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com; spf=none smtp.mailfrom=linux.intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=hV0rZwhv; arc=none smtp.client-ip=192.198.163.9 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; spf=none smtp.mailfrom=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="hV0rZwhv" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1714387698; x=1745923698; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=3qNUeNNqvAX2EUpER+BCy2WtfN/wfJPQesC9InOcInY=; b=hV0rZwhvrSPBjcuu0ekLoViJi7dWmLOaCQDPOY/5VuSACztOHR9A06n1 jci3LPFYf6zAO6AtJAXjPyWjSwZ4FvKWj+6O98AGk/ExrNCd5ZZBGM9kb MRVmbgne5kLJwcbZzcTCBtojy8o/v554DuACDBSSJIEG3uItDytZBn11T JdmsMtpH+CqBnPUfs9WhoXtP3P0YO4Wtv2sEra1IfBb91OdF0BBmtzuYf 1FAGj/CPvdBHBbhcnzUoz3kDjWy5Mwhx45VdLXlVAM0OmktNOK5DvklIj inIMcx584adibGbJ5+pO/MsxbMZvOIQfjKXCGh6BJJS3YmNPRoPmWE3ej g==; X-CSE-ConnectionGUID: SYekFPNDSFCOP89w4CKohg== X-CSE-MsgGUID: q4JRwSLLTOOhAYEcFI/dRA== X-IronPort-AV: E=McAfee;i="6600,9927,11057"; a="20729455" X-IronPort-AV: E=Sophos;i="6.07,239,1708416000"; d="scan'208";a="20729455" Received: from fmviesa007.fm.intel.com ([10.60.135.147]) by fmvoesa103.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 29 Apr 2024 03:48:17 -0700 X-CSE-ConnectionGUID: GKf41xG9T0G5foS4CYye8A== X-CSE-MsgGUID: z23Bu2lZSkGhazCdiU8p9Q== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.07,239,1708416000"; d="scan'208";a="26067723" Received: from ijarvine-desk1.ger.corp.intel.com (HELO localhost) ([10.245.247.45]) by fmviesa007-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 29 Apr 2024 03:48:14 -0700 From: =?UTF-8?q?Ilpo=20J=C3=A4rvinen?= To: linux-pci@vger.kernel.org, Bjorn Helgaas , Lorenzo Pieralisi , Rob Herring , =?UTF-8?q?Krzysztof=20Wilczy=C5=84ski?= , Linus Walleij , Lorenzo Pieralisi , linux-kernel@vger.kernel.org Cc: =?UTF-8?q?Ilpo=20J=C3=A4rvinen?= Subject: [PATCH 10/10] PCI: v3: Use generic PCI Conf Type 0/1 helpers Date: Mon, 29 Apr 2024 13:46:33 +0300 Message-Id: <20240429104633.11060-11-ilpo.jarvinen@linux.intel.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20240429104633.11060-1-ilpo.jarvinen@linux.intel.com> References: <20240429104633.11060-1-ilpo.jarvinen@linux.intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Convert v3 to use pci_conf{0,1}_addr() from PCI core to calculate PCI Configuration Space address for Type 0/1 access. Signed-off-by: Ilpo J=C3=A4rvinen Reviewed-by: Linus Walleij --- drivers/pci/controller/pci-v3-semi.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/pci/controller/pci-v3-semi.c b/drivers/pci/controller/= pci-v3-semi.c index 460a825325dd..a07323148007 100644 --- a/drivers/pci/controller/pci-v3-semi.c +++ b/drivers/pci/controller/pci-v3-semi.c @@ -327,7 +327,7 @@ static void __iomem *v3_map_bus(struct pci_bus *bus, * 3:1 =3D config cycle (101) * 0 =3D PCI A1 & A0 are 0 (0) */ - address =3D PCI_FUNC(devfn) << 8; + address =3D pci_conf0_addr(devfn, offset); mapaddress =3D V3_LB_MAP_TYPE_CONFIG; =20 if (slot > 12) @@ -354,7 +354,7 @@ static void __iomem *v3_map_bus(struct pci_bus *bus, * 0 =3D PCI A1 & A0 from host bus (1) */ mapaddress =3D V3_LB_MAP_TYPE_CONFIG | V3_LB_MAP_AD_LOW_EN; - address =3D (busnr << 16) | (devfn << 8); + address =3D pci_conf1_addr(busnr, devfn, offset, false); } =20 /* @@ -375,7 +375,7 @@ static void __iomem *v3_map_bus(struct pci_bus *bus, v3->base + V3_LB_BASE1); writew(mapaddress, v3->base + V3_LB_MAP1); =20 - return v3->config_base + address + offset; + return v3->config_base + address; } =20 static void v3_unmap_bus(struct v3_pci *v3) --=20 2.39.2