From nobody Sun May 19 13:54:39 2024 Received: from smtpcmd0757.aruba.it (smtpcmd0757.aruba.it [62.149.156.57]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B6ED414901A for ; Fri, 26 Apr 2024 15:30:42 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=62.149.156.57 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1714145446; cv=none; b=aW/CflI4OF7G3OzhPGz5XHOOwPYtDcxYpuFtddDNPgoYlU9tJvt2Zpgo86FpG14P5m8uNOZIp1Gd2FaTRwx6NsnRRWx448C2HZntgmnBfAkHqc+XGADta8cvCEhKa98skOWmToYm7GagLOoDhDMmXeQ4Hv1TJJiQ6lPKb0XLm0A= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1714145446; c=relaxed/simple; bh=AL/RIHlDSD7TG5DlDkAMmKi18A+T8P4sO4zdcXPXefU=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=aXDLzmma739xdLqOQK7OJAgrZxqosWAN+kkPubdv40pzECEnbMtiI6Cz9bt6XUYxSynL2w26D+RjhNz477O5zUTXNhMozM39faThxvg+PCv061zXguBMcUeLauYI56tvjWdvCBX4MDpsfxRSAehdJ4gcK0ARdOpw9zr5NTzo5bc= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=engicam.com; spf=pass smtp.mailfrom=engicam.com; dkim=pass (2048-bit key) header.d=aruba.it header.i=@aruba.it header.b=kOuOHeAT; arc=none smtp.client-ip=62.149.156.57 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=engicam.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=engicam.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=aruba.it header.i=@aruba.it header.b="kOuOHeAT" Received: from engicam.com ([146.241.23.148]) by Aruba Outgoing Smtp with ESMTPSA id 0NU4sgEVa6epj0NU5seY30; Fri, 26 Apr 2024 17:27:34 +0200 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=aruba.it; s=a1; t=1714145254; bh=AL/RIHlDSD7TG5DlDkAMmKi18A+T8P4sO4zdcXPXefU=; h=From:To:Subject:Date:MIME-Version; b=kOuOHeAThuJp/LE1dluXA9fhCl3DfboaH+ZZKpug382AHP6KsB3Iy9GB03WAG9QLn geeHZ86ot/vMjxPrnr36ogu5xaVS4zLoUnuJ4OJ65IDXKf5GcdtJ6Vd77Uz0cIicz8 y81dTqCEW4n75MbnF5m0zhRr1syxOOoCuvmIRbjpWCQiiJwnxDVNZQJa04L63rdT0U IAlPWTzpcVw9OQ3WMdhrtYSpDVIlKcdqGl5IFzsj4eLVsAg4dr/oF57mtaJ2Htds9r Siaf9g09YilJQ7wsV62OGD4fN9IXj9YeBKW+zs6cqEkn4Z1wB5ndkFTT792SvMKH6k 7HKIo8yXLoRZA== From: Fabio Aiuto To: Shawn Guo , Sascha Hauer , Krzysztof Kozlowski , Rob Herring , Conor Dooley Cc: devicetree@vger.kernel.org, imx@lists.linux.dev, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Fabio Aiuto , Matteo Lisi , Mirko Ardinghi , Krzysztof Kozlowsky , Conor Dooley Subject: [PATCH v6 1/3] dt-bindings: arm: fsl: add Engicam i.Core MX93 EDIMM 2.0 Starter Kit Date: Fri, 26 Apr 2024 17:27:28 +0200 Message-Id: <20240426152730.9806-2-fabio.aiuto@engicam.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240426152730.9806-1-fabio.aiuto@engicam.com> References: <20240426152730.9806-1-fabio.aiuto@engicam.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CMAE-Envelope: MS4xfBpXg0R56R6cOqqviDj0eVmGiholy62key5QTgyVk64OidOQYPGH8pVLedjYxirnNH6w/6GZ4Q20PGL/9G4lcxVEb1HqAuHoaiBg3k+uHfCvX0yYs7at emkjG2GRa/L83oeTGTAoiARWlNfviUBynjZIIyeHylgRXT80iuGPhtZ7ZpUjseLwoPebJiFJ/95Xip/FdggUI9xdAiT86HmyAPR34qj1+bc0sTgzQbqOJIBS REUxZiP187uYRJJ2SQ/bBSf9kvSxO59aqga5U6Or49v6BFH0/+ClIds0hxPaSwgmPXB3weXmUOhuwiSkSf/zA6LGEw5INyOXF27jaYq68xK9yB1/WXAKd4Qc qp6ghCVk/x/iWk7GPSWyMTgGT6TCYDt9DvrieVkZc7OtPhtfFuJwaEIr9DOOtu71bSZaKWpa56YqsuBJ4SJXWOYt0tmZf2Q0ijbnmGfJQ9vdwVbThbzpKqdj VduN/792uCWTYFA5WlhsRZqgRWVVxBoMzT1BR/NwHjg6pC7xO4UjPixm7y0ttyU41gyuh1sd4ibRQ5mLdGE95LOUkVqNos0tfj8sKtvbYK6/NajfCE86w8QH X0LAg0aXWZGMpDpwJZqvhpoy7jcJg98mO1UhVrRKRBfUUxDcPvT+thL1bUtn6Znz9JUbUyU0vqhPiujQBliDldpZ Content-Type: text/plain; charset="utf-8" i.Core MX93 is a NXP i.MX93 based EDIMM SoM by Engicam. EDIMM 2.0 Starter Kit is an EDIMM 2.0 Form Factor Capacitive Evaluation Board by Engicam. i.Core MX93 needs to be mounted on top of EDIMM 2.0 Starter Kit to get the full i.Core MX93 EDIMM 2.0 Starter Kit board. Add bindings for this board. Cc: Matteo Lisi Cc: Mirko Ardinghi Reviewed-by: Krzysztof Kozlowsky Acked-by: Conor Dooley Signed-off-by: Fabio Aiuto --- v3 ---> v6: - no changes v2 ---> v3: - added {Reviewed,Acked}-by tags v1 ---> v2: - no changes Documentation/devicetree/bindings/arm/fsl.yaml | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/fsl.yaml b/Documentation= /devicetree/bindings/arm/fsl.yaml index 0027201e19f8..b497a01c7418 100644 --- a/Documentation/devicetree/bindings/arm/fsl.yaml +++ b/Documentation/devicetree/bindings/arm/fsl.yaml @@ -1265,6 +1265,13 @@ properties: - fsl,imx93-11x11-evk # i.MX93 11x11 EVK Board - const: fsl,imx93 =20 + - description: Engicam i.Core MX93 based Boards + items: + - enum: + - engicam,icore-mx93-edimm2 # i.MX93 Engicam i.Core = MX93 EDIMM 2.0 Starter Kit + - const: engicam,icore-mx93 # i.MX93 Engicam i.Core = MX93 Som + - const: fsl,imx93 + - description: i.MXRT1050 based Boards items: - enum: --=20 2.34.1 From nobody Sun May 19 13:54:39 2024 Received: from smtpcmd0757.aruba.it (smtpcmd0757.aruba.it [62.149.156.57]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id AA6C214901F for ; Fri, 26 Apr 2024 15:30:43 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=62.149.156.57 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1714145446; cv=none; b=BcitdFKnBd8yhQnr2ePOP/jNMGXMxI5Zb+hp/0y8lY6tDNNHiYrWGakxF+s8irdCR93WLd2sChVxXdEB7jHmRzAN/9Yp4+yivy1iaCNILPk3KLMIEk2ymYXsn2HHI2nb6SdtgD24mEvaQNH1EZIv/T4vI3ny8AlJUS+2DM1QXmI= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1714145446; c=relaxed/simple; bh=jq8VcbPwIv0D1saPBa87tJSgOEKyrHw9hVrzmv0jva4=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=E9dxb19kJ5OM3Mx1qiBQEsXKqyGUxV7PDVzyESAOgDV4EEoNtUtVFjEzJdGSyDNZV6/76UIPomGXc+gqlOFykWibVUanfF2VDsa3jIecOlOCUUUmS3YT+mjtwiPD7/fc8ElHktbjCumxvu6HganqhtvS9Og5SUg9Z4S6HHCxMWY= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=engicam.com; spf=pass smtp.mailfrom=engicam.com; dkim=pass (2048-bit key) header.d=aruba.it header.i=@aruba.it header.b=G1FYtMw6; arc=none smtp.client-ip=62.149.156.57 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=engicam.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=engicam.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=aruba.it header.i=@aruba.it header.b="G1FYtMw6" Received: from engicam.com ([146.241.23.148]) by Aruba Outgoing Smtp with ESMTPSA id 0NU4sgEVa6epj0NU6seY3S; Fri, 26 Apr 2024 17:27:35 +0200 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=aruba.it; s=a1; t=1714145255; bh=jq8VcbPwIv0D1saPBa87tJSgOEKyrHw9hVrzmv0jva4=; h=From:To:Subject:Date:MIME-Version; b=G1FYtMw6eSw55QRSeSAZa0EI5sQrJ5iCwM5azL1MVk/IJrrymTmCyeL+6Zcrb1R6Y zZq/yHHn8iUrPpcQGLlE0wRPKLhsHaQNrOhd6aBf/1wPvxi/3Muyo4fN5yjeRxJCG9 M4+bLPUKkUXO7y92stWt8n0oPt/QJ/C7DlVqwVE+tBfUqU5/vFIjKqFcPB/0rjgTBP tAPtk5CRiifOV/mTBRMabYqF5HaLA+RGeO+I4qgKAmugQ1fL5FoIkZ7UJERLTKIuGB N8VWLFmKDM3ao/zxtcu8vUgNGeBbKp+G0h/Egxev0HILFpoNIAPwOdT4Kx9nB8qPsr KidtVt+AAu/3g== From: Fabio Aiuto To: Shawn Guo , Sascha Hauer , Krzysztof Kozlowski , Rob Herring , Conor Dooley Cc: devicetree@vger.kernel.org, imx@lists.linux.dev, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Fabio Aiuto , Matteo Lisi , Mirko Ardinghi , Peng Fan Subject: [PATCH v6 2/3] arm64: dts: imx93: add Engicam i.Core MX93 SoM Date: Fri, 26 Apr 2024 17:27:29 +0200 Message-Id: <20240426152730.9806-3-fabio.aiuto@engicam.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240426152730.9806-1-fabio.aiuto@engicam.com> References: <20240426152730.9806-1-fabio.aiuto@engicam.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CMAE-Envelope: MS4xfMTfbUipsuTo9QC65IIra2IWaM0mKsJfDj9zfbXQmRjufylmEzNJehgnSko4fi+/+BklfTDOJ8LsUk2/bUpOsPb7YOFVGeZ36PasM9ez9ca6oOdHZWYN Qu6GRIl9Aioj+iLepDChmzOR5TO6/Yk+mvAvsC91hrZnB64irxlVmMos6C8hLxhv2231IacyhUkhb54I6jhIy1H6/79xBeN3D0t3tXe0EakxdndBNVaKlGYc Nm0bxG127QvDedapSlufF4+2ZkI6f5yHA4tFJB1dR1ky/VjsZPDZqPIUVcLyH+pL9PgC28tvNbFePnNKk/SWR0kDcZOsOM2VOtAai4oEfkKIIA/teRu+4LJF VaaJW/Vi5ERcS7uI4Pdu+cvT5cxbXvDwVy9xWDPD/+RfSJ2uyQirMH8F1f45JxXeARX5RCqWwVemA9wjPfbpP5zew1jylEN7vLmNg5i1CkkMFE7LXrpjLMUr 2k437FZDEpa3imZnVU9l9OWCpNaYU9jBso+Jr7UCLU/w6myzBVYdujo/rbbszYpWJgCjG4A9/YtxI34H8smP8gR8grxU24fhuop1sczi8HaK9tzIv2/KsPpD LMgWAF/f61IVxsuMxC13o/fxhkGVk81odM2RM3IyTpkYjg== Content-Type: text/plain; charset="utf-8" i.Core MX93 is a NXP i.MX93 based EDIMM SoM by Engicam. Main features: CPU: NXP i.MX 93 MEMORY: Up to 2GB LPDDR4 NETWORKING: 2x Gb Ethernet USB: USB OTG 2.0, USB HOST 2.0 STORAGE: eMMC starting from 4GB PERIPHERALS: UART, I2C, SPI, CAN, SDIO, GPIO The i.Core MX93 needs to be mounted on top of Engicam baseboards to work. Add devicetree include file. Cc: Matteo Lisi Cc: Mirko Ardinghi Reviewed-by: Peng Fan Signed-off-by: Fabio Aiuto --- v5 ---> v6: - no changes v4 ---> v5: - added Reviewed-by tag - fixed line wrapping in commit msg - fixed indentation, dropped newlines, reordered property v3 ---> v4: - no changes v2 ---> v3: - added wdog_b-warm-reset property in pmic v1 ---> v2: - remove unneeded include .../boot/dts/freescale/imx93-icore-mx93.dtsi | 269 ++++++++++++++++++ 1 file changed, 269 insertions(+) create mode 100644 arch/arm64/boot/dts/freescale/imx93-icore-mx93.dtsi diff --git a/arch/arm64/boot/dts/freescale/imx93-icore-mx93.dtsi b/arch/arm= 64/boot/dts/freescale/imx93-icore-mx93.dtsi new file mode 100644 index 000000000000..9c97b620ccfc --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx93-icore-mx93.dtsi @@ -0,0 +1,269 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2022 NXP + * Copyright 2024 Engicam s.r.l. + */ + +/dts-v1/; + +#include "imx93.dtsi" + +/ { + model =3D "Engicam i.Core MX93 SoM"; + compatible =3D "engicam,icore-mx93", "fsl,imx93"; + + reg_vref_1v8: regulator-adc-vref { + compatible =3D "regulator-fixed"; + regulator-name =3D "vref_1v8"; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + }; +}; + +&adc1 { + vref-supply =3D <®_vref_1v8>; + status =3D "okay"; +}; + +&eqos { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_eqos>; + phy-mode =3D "rgmii-id"; + phy-handle =3D <ðphy1>; + status =3D "okay"; + + mdio { + compatible =3D "snps,dwmac-mdio"; + #address-cells =3D <1>; + #size-cells =3D <0>; + + ethphy1: ethernet-phy@7 { + compatible =3D "ethernet-phy-ieee802.3-c22"; + reg =3D <7>; + }; + }; +}; + +&fec { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_fec>; + phy-mode =3D "rgmii-id"; + phy-handle =3D <ðphy2>; + fsl,magic-packet; + status =3D "okay"; + + mdio { + #address-cells =3D <1>; + #size-cells =3D <0>; + + ethphy2: ethernet-phy@7 { + compatible =3D "ethernet-phy-ieee802.3-c22"; + reg =3D <7>; + }; + }; +}; + +&lpi2c2 { + #address-cells =3D <1>; + #size-cells =3D <0>; + clock-frequency =3D <400000>; + pinctrl-names =3D "default", "sleep"; + pinctrl-0 =3D <&pinctrl_lpi2c2>; + pinctrl-1 =3D <&pinctrl_lpi2c2>; + status =3D "okay"; + + pmic@25 { + compatible =3D "nxp,pca9451a"; + reg =3D <0x25>; + interrupt-parent =3D <&gpio2>; + interrupts =3D <15 IRQ_TYPE_LEVEL_LOW>; + nxp,wdog_b-warm-reset; + + regulators { + buck1: BUCK1 { + regulator-name =3D "BUCK1"; + regulator-min-microvolt =3D <600000>; + regulator-max-microvolt =3D <2187500>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay =3D <3125>; + }; + + buck2: BUCK2 { + regulator-name =3D "BUCK2"; + regulator-min-microvolt =3D <600000>; + regulator-max-microvolt =3D <2187500>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay =3D <3125>; + }; + + buck4: BUCK4{ + regulator-name =3D "BUCK4"; + regulator-min-microvolt =3D <600000>; + regulator-max-microvolt =3D <3400000>; + regulator-boot-on; + regulator-always-on; + }; + + buck5: BUCK5{ + regulator-name =3D "BUCK5"; + regulator-min-microvolt =3D <600000>; + regulator-max-microvolt =3D <3400000>; + regulator-boot-on; + regulator-always-on; + }; + + buck6: BUCK6 { + regulator-name =3D "BUCK6"; + regulator-min-microvolt =3D <600000>; + regulator-max-microvolt =3D <3400000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo1: LDO1 { + regulator-name =3D "LDO1"; + regulator-min-microvolt =3D <1600000>; + regulator-max-microvolt =3D <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo2: LDO2 { + regulator-name =3D "LDO2"; + regulator-min-microvolt =3D <800000>; + regulator-max-microvolt =3D <1150000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo3: LDO3 { + regulator-name =3D "LDO3"; + regulator-min-microvolt =3D <800000>; + regulator-max-microvolt =3D <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo4: LDO4 { + regulator-name =3D "LDO4"; + regulator-min-microvolt =3D <800000>; + regulator-max-microvolt =3D <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo5: LDO5 { + regulator-name =3D "LDO5"; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <3300000>; + regulator-boot-on; + regulator-always-on; + }; + }; + }; +}; + +&usdhc1 { + pinctrl-names =3D "default", "state_100mhz", "state_200mhz"; + pinctrl-0 =3D <&pinctrl_usdhc1>; + pinctrl-1 =3D <&pinctrl_usdhc1>; + pinctrl-2 =3D <&pinctrl_usdhc1>; + bus-width =3D <8>; + non-removable; + status =3D "okay"; +}; + +&usdhc2 {/*SD Card*/ + pinctrl-names =3D "default", "state_100mhz", "state_200mhz"; + pinctrl-0 =3D <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; + pinctrl-1 =3D <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; + pinctrl-2 =3D <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; + cd-gpios =3D <&gpio3 00 GPIO_ACTIVE_LOW>; + bus-width =3D <4>; + no-1-8-v; + max-frequency =3D <25000000>; + status =3D "okay"; +}; + +&iomuxc { + pinctrl_eqos: eqosgrp { + fsl,pins =3D < + MX93_PAD_ENET1_MDC__ENET_QOS_MDC 0x53e + MX93_PAD_ENET1_MDIO__ENET_QOS_MDIO 0x53e + MX93_PAD_ENET1_RD0__ENET_QOS_RGMII_RD0 0x53e + MX93_PAD_ENET1_RD1__ENET_QOS_RGMII_RD1 0x53e + MX93_PAD_ENET1_RD2__ENET_QOS_RGMII_RD2 0x53e + MX93_PAD_ENET1_RD3__ENET_QOS_RGMII_RD3 0x53e + MX93_PAD_ENET1_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK 0x53e + MX93_PAD_ENET1_RX_CTL__ENET_QOS_RGMII_RX_CTL 0x53e + MX93_PAD_ENET1_TD0__ENET_QOS_RGMII_TD0 0x53e + MX93_PAD_ENET1_TD1__ENET_QOS_RGMII_TD1 0x53e + MX93_PAD_ENET1_TD2__ENET_QOS_RGMII_TD2 0x53e + MX93_PAD_ENET1_TD3__ENET_QOS_RGMII_TD3 0x53e + MX93_PAD_ENET1_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK 0x53e + MX93_PAD_ENET1_TX_CTL__ENET_QOS_RGMII_TX_CTL 0x53e + >; + }; + + pinctrl_fec: fecgrp { + fsl,pins =3D < + MX93_PAD_ENET2_MDC__ENET1_MDC 0x57e + MX93_PAD_ENET2_MDIO__ENET1_MDIO 0x57e + MX93_PAD_ENET2_RD0__ENET1_RGMII_RD0 0x57e + MX93_PAD_ENET2_RD1__ENET1_RGMII_RD1 0x57e + MX93_PAD_ENET2_RD2__ENET1_RGMII_RD2 0x57e + MX93_PAD_ENET2_RD3__ENET1_RGMII_RD3 0x57e + MX93_PAD_ENET2_RXC__ENET1_RGMII_RXC 0x5fe + MX93_PAD_ENET2_RX_CTL__ENET1_RGMII_RX_CTL 0x57e + MX93_PAD_ENET2_TD0__ENET1_RGMII_TD0 0x57e + MX93_PAD_ENET2_TD1__ENET1_RGMII_TD1 0x57e + MX93_PAD_ENET2_TD2__ENET1_RGMII_TD2 0x57e + MX93_PAD_ENET2_TD3__ENET1_RGMII_TD3 0x57e + MX93_PAD_ENET2_TXC__ENET1_RGMII_TXC 0x5fe + MX93_PAD_ENET2_TX_CTL__ENET1_RGMII_TX_CTL 0x57e + >; + }; + + pinctrl_lpi2c2: lpi2c2grp { + fsl,pins =3D < + MX93_PAD_I2C2_SCL__LPI2C2_SCL 0x40000b9e + MX93_PAD_I2C2_SDA__LPI2C2_SDA 0x40000b9e + >; + }; + + pinctrl_usdhc1: usdhc1grp { + fsl,pins =3D < + MX93_PAD_SD1_CLK__USDHC1_CLK 0x15fe + MX93_PAD_SD1_CMD__USDHC1_CMD 0x13fe + MX93_PAD_SD1_DATA0__USDHC1_DATA0 0x13fe + MX93_PAD_SD1_DATA1__USDHC1_DATA1 0x13fe + MX93_PAD_SD1_DATA2__USDHC1_DATA2 0x13fe + MX93_PAD_SD1_DATA3__USDHC1_DATA3 0x13fe + MX93_PAD_SD1_DATA4__USDHC1_DATA4 0x13fe + MX93_PAD_SD1_DATA5__USDHC1_DATA5 0x13fe + MX93_PAD_SD1_DATA6__USDHC1_DATA6 0x13fe + MX93_PAD_SD1_DATA7__USDHC1_DATA7 0x13fe + MX93_PAD_SD1_STROBE__USDHC1_STROBE 0x15fe + >; + }; + + pinctrl_usdhc2: usdhc2grp { + fsl,pins =3D < + MX93_PAD_SD2_CLK__USDHC2_CLK 0x170e + MX93_PAD_SD2_CMD__USDHC2_CMD 0x130e + MX93_PAD_SD2_DATA0__USDHC2_DATA0 0x130e + MX93_PAD_SD2_DATA1__USDHC2_DATA1 0x130e + MX93_PAD_SD2_DATA2__USDHC2_DATA2 0x130e + MX93_PAD_SD2_DATA3__USDHC2_DATA3 0x130e + MX93_PAD_SD2_VSELECT__USDHC2_VSELECT 0x51e + >; + }; + + pinctrl_usdhc2_gpio: usdhc2gpiogrp { + fsl,pins =3D < + MX93_PAD_SD2_CD_B__GPIO3_IO00 0x31e + >; + }; +}; --=20 2.34.1 From nobody Sun May 19 13:54:39 2024 Received: from smtpcmd0757.aruba.it (smtpcmd0757.aruba.it [62.149.156.57]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 3784B14B09E for ; Fri, 26 Apr 2024 15:30:44 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=62.149.156.57 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1714145448; cv=none; b=K1FaW4UIcA/cXSPHHIa46L868OEOKH5qZ2qKkAcm+7pZyU/pE8DzJ3ogBm8YaQ/nuPkis124dwJHJd4xrrWc1PJc4XJU/tP3bPiupw1fwW3NrjrWyPjPmIU5teFsgBNc2qOz3Otn8UOw/w3HJtR2qVH6aPA8QwfHOWjDe7E3SiY= ARC-Message-Signature: i=1; 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Fri, 26 Apr 2024 17:27:35 +0200 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=aruba.it; s=a1; t=1714145255; bh=Ax6/DOMKEDbCj4WJgNuv60PEhjHWl1MnM+TaNC/LV4Y=; h=From:To:Subject:Date:MIME-Version; b=ii0tHDDdsha4fS/VxA42QIcTWABD2TtaWwktgNtNry0AUCE/fSF3xP8uYYUc8rBhA 8gpijjVlSYY0TuQT5qICfyFVUz0mGnf6/IRAfMvtkO7/cjuwki6rcd9RJRMNbkQ555 ZpaNjNUQVZ3BE/iOTXbvwtxmze/ReI+zyc0YZhFplUiGk6d6j1bZmca2VkjIUYEMN+ KGbrFBxc8Oh0F4EtBIj6zj/9OL3Gphe9xCZbK2FrMqJ7osaQmVijOzbBgZr2jb4pdF nRmQpQfzSaYZBpnBWwcSjjl8MZyaly3qli/kzJ1Rr6gydeN9MLYwxRLk+lQcbYgx0O sMrMyDXubrTCQ== From: Fabio Aiuto To: Shawn Guo , Sascha Hauer , Krzysztof Kozlowski , Rob Herring , Conor Dooley Cc: devicetree@vger.kernel.org, imx@lists.linux.dev, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Fabio Aiuto , Matteo Lisi , Mirko Ardinghi , Peng Fan , Michael Trimarchi Subject: [PATCH v6 3/3] arm64: dts: imx93: Add Engicam i.Core MX93 EDIMM 2.0 Starter Kit Date: Fri, 26 Apr 2024 17:27:30 +0200 Message-Id: <20240426152730.9806-4-fabio.aiuto@engicam.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240426152730.9806-1-fabio.aiuto@engicam.com> References: <20240426152730.9806-1-fabio.aiuto@engicam.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CMAE-Envelope: MS4xfMTfbUipsuTo9QC65IIra2IWaM0mKsJfDj9zfbXQmRjufylmEzNJehgnSko4fi+/+BklfTDOJ8LsUk2/bUpOsPb7YOFVGeZ36PasM9ez9ca6oOdHZWYN Qu6GRIl9Aioj+r92vdjYSw02tovkYLTCr/Uj0q3/I87puWx81o8r0xWWkWKOoe+ajIhcwGNlqzWQ2ERHiG01ljdLWsiTKbEjXhbV9AWWHrzsMYcBhyrX8yYn +QI94yZcd9bof/abYhaF9jES9QyUNmIjq/UHz03A/7o6WDkucBAqjLyw4U12uvb9gu/LTRnqaDO6EDX8uGZS1YsMsuYcmBZCqIkIX4e+s5hGgVZCwOicqtOG mXfvTvnXzJxr7Gkbzzv6RD0EAY7Ag2SUfUIkFwxTf/XxJbLL4D2MTjaiLWL/r9B7XXgszswhqGwx6hwSiMZyno3VhVS5zxRinQxBXXBiTXzen9EdwfvqyQ4a LkM/GaGV8I4ToiQNDsxfBmxl64+vpEDbjZomZ2Mbo33ZGhI5Lx9dkmEoWxOGpAE0ZFzzg3RbLaBbEo0trW9STCQYKNMBFogd29ii8OEK8COAv7qwxLqa32W+ 8m8XcEciW6kHgEyv1DN76LJ4whHZ2/XoRw/uRYuTuaxMEOWHy3nfqBp8669Y0EDQ9C+PWrUFHqFwmMcmKvGbhpwl Content-Type: text/plain; charset="utf-8" i.Core MX93 is a NXP i.MX93 based SoM by Enigcam which needs to be mounted on top of Engicam baseboards. Add support for EDIMM 2.0 Starter Kit hosting i.Core MX93. Starter Kit main features: 2x LVDS interfaces HDMI output Audio out Mic in Micro SD card slot USB 3.0 A port 3x USB 2.0 A port Gb Ethernet 2x CAN bus, 3x UART interfaces SIM card slot M.2 KEY_B slot Cc: Matteo Lisi Cc: Mirko Ardinghi Reviewed-by: Peng Fan Reviewed-by: Michael Trimarchi Signed-off-by: Fabio Aiuto --- v5 ---> v6: - added property in lpuart5 node - removed unused sai1 node - move Cc tag to Reviewed-by tag v4 ---> v5: - done some property reorder, indentation fixes, node rename, drop/add new lines - added Reviewed-by tag v3 ---> v4: - drop wl_reg_on regulator in favor of mmc-pwrseq-simple - add Cc tag v2 ---> v3: - fixed dtschema warnings - removed regulator-always-on on bt_reg_on - fixed clock rate assignment on sgtl5000 node - fixed indentation issue v1 ---> v2: - fixed indentation issue - fixed missing space issue - improved naming of regulator nodes - removed unneeded include arch/arm64/boot/dts/freescale/Makefile | 1 + .../dts/freescale/imx93-icore-mx93-edimm2.dts | 324 ++++++++++++++++++ 2 files changed, 325 insertions(+) create mode 100644 arch/arm64/boot/dts/freescale/imx93-icore-mx93-edimm2.d= ts diff --git a/arch/arm64/boot/dts/freescale/Makefile b/arch/arm64/boot/dts/f= reescale/Makefile index 045250d0a040..d26c0a458a44 100644 --- a/arch/arm64/boot/dts/freescale/Makefile +++ b/arch/arm64/boot/dts/freescale/Makefile @@ -226,6 +226,7 @@ dtb-$(CONFIG_ARCH_MXC) +=3D imx8qxp-mek.dtb dtb-$(CONFIG_ARCH_MXC) +=3D imx8qxp-tqma8xqp-mba8xx.dtb dtb-$(CONFIG_ARCH_MXC) +=3D imx8ulp-evk.dtb dtb-$(CONFIG_ARCH_MXC) +=3D imx93-11x11-evk.dtb +dtb-$(CONFIG_ARCH_MXC) +=3D imx93-icore-mx93-edimm2.dtb dtb-$(CONFIG_ARCH_MXC) +=3D imx93-phyboard-segin.dtb dtb-$(CONFIG_ARCH_MXC) +=3D imx93-tqma9352-mba93xxca.dtb dtb-$(CONFIG_ARCH_MXC) +=3D imx93-tqma9352-mba93xxla.dtb diff --git a/arch/arm64/boot/dts/freescale/imx93-icore-mx93-edimm2.dts b/ar= ch/arm64/boot/dts/freescale/imx93-icore-mx93-edimm2.dts new file mode 100644 index 000000000000..149707d84165 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx93-icore-mx93-edimm2.dts @@ -0,0 +1,324 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2022 NXP + * Copyright 2024 Engicam s.r.l. + */ + +/dts-v1/; + +#include "imx93-icore-mx93.dtsi" + +/ { + model =3D "Engicam i.Core MX93 - EDIMM 2 Starterkit"; + compatible =3D "engicam,icore-mx93-edimm2", "engicam,icore-mx93", + "fsl,imx93"; + + aliases { + rtc1 =3D &bbnsm_rtc; + }; + + chosen { + stdout-path =3D &lpuart1; + }; + + bt_reg_on: regulator-btregon { + compatible =3D "regulator-gpio"; + regulator-name =3D "BT_REG_ON"; + regulator-min-microvolt =3D <100000>; + regulator-max-microvolt =3D <3300000>; + states =3D <3300000 0x1>, <100000 0x0>; + gpios =3D <&gpio2 19 GPIO_ACTIVE_HIGH>; + }; + + reg_1v8_sgtl: regulator-1v8-sgtl { + compatible =3D "regulator-fixed"; + regulator-name =3D "1v8_sgtl"; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + regulator-always-on; + }; + + reg_3v3_avdd_sgtl: regulator-3v3-avdd-sgtl { + compatible =3D "regulator-fixed"; + regulator-name =3D "3v3_avdd_sgtl"; + regulator-min-microvolt =3D <3300000>; + regulator-max-microvolt =3D <3300000>; + regulator-always-on; + }; + + reg_3v3_sgtl: regulator-3v3-sgtl { + compatible =3D "regulator-fixed"; + regulator-name =3D "3v3_sgtl"; + regulator-min-microvolt =3D <3300000>; + regulator-max-microvolt =3D <3300000>; + regulator-always-on; + }; + + reserved-memory { + #address-cells =3D <2>; + #size-cells =3D <2>; + ranges; + + linux,cma { + compatible =3D "shared-dma-pool"; + reusable; + alloc-ranges =3D <0 0x80000000 0 0x40000000>; + size =3D <0 0x10000000>; + linux,cma-default; + }; + + rsc_table: rsc-table@2021f000 { + reg =3D <0 0x2021f000 0 0x1000>; + no-map; + }; + + vdevbuffer: vdevbuffer@a4020000 { + compatible =3D "shared-dma-pool"; + reg =3D <0 0xa4020000 0 0x100000>; + no-map; + }; + + vdev0vring0: vdev0vring0@a4000000 { + reg =3D <0 0xa4000000 0 0x8000>; + no-map; + }; + + vdev0vring1: vdev0vring1@a4008000 { + reg =3D <0 0xa4008000 0 0x8000>; + no-map; + }; + + vdev1vring0: vdev1vring0@a4000000 { + reg =3D <0 0xa4010000 0 0x8000>; + no-map; + }; + + vdev1vring1: vdev1vring1@a4018000 { + reg =3D <0 0xa4018000 0 0x8000>; + no-map; + }; + }; + + sound { + compatible =3D "simple-audio-card"; + simple-audio-card,name =3D "imx93-sgtl5000"; + simple-audio-card,format =3D "i2s"; + simple-audio-card,bitclock-master =3D <&dailink_master>; + simple-audio-card,frame-master =3D <&dailink_master>; + /*simple-audio-card,mclk-fs =3D <1>;*/ + + simple-audio-card,cpu { + sound-dai =3D <&sai3>; + }; + + dailink_master: simple-audio-card,codec { + sound-dai =3D <&sgtl5000>; + clocks =3D <&clk IMX93_CLK_SAI3_IPG>; + }; + }; + + usdhc3_pwrseq: usdhc3-pwrseq { + compatible =3D "mmc-pwrseq-simple"; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_usdhc3_pwrseq>; + reset-gpios =3D <&gpio2 22 GPIO_ACTIVE_LOW>; + }; +}; + +&cm33 { + mbox-names =3D "tx", "rx", "rxdb"; + mboxes =3D <&mu1 0 1>, + <&mu1 1 1>, + <&mu1 3 1>; + memory-region =3D <&vdevbuffer>, <&vdev0vring0>, <&vdev0vring1>, + <&vdev1vring0>, <&vdev1vring1>, <&rsc_table>; + status =3D "okay"; +}; + +&flexcan1 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_flexcan1>; + fsl,stop-mode =3D <&aonmix_ns_gpr 0x10 4>; + status =3D "okay"; +}; + +&flexcan2 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_flexcan2>; + fsl,stop-mode =3D <&aonmix_ns_gpr 0x10 4>; + status =3D "okay"; +}; + +&lpi2c1 { + #address-cells =3D <1>; + #size-cells =3D <0>; + clock-frequency =3D <400000>; + pinctrl-names =3D "default", "sleep"; + pinctrl-0 =3D <&pinctrl_lpi2c1>; + pinctrl-1 =3D <&pinctrl_lpi2c1>; + status =3D "okay"; + + sgtl5000: audio-codec@a { + compatible =3D "fsl,sgtl5000"; + reg =3D <0x0a>; + #sound-dai-cells =3D <0>; + clocks =3D <&clk IMX93_CLK_SAI3_GATE>; + VDDA-supply =3D <®_3v3_avdd_sgtl>; + VDDIO-supply =3D <®_3v3_sgtl>; + VDDD-supply =3D <®_1v8_sgtl>; + status =3D "okay"; + }; + + pcf8523: rtc@68 { + compatible =3D "nxp,pcf8523"; + reg =3D <0x68>; + }; +}; + +&lpuart1 { /* console */ + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_uart1>; + status =3D "okay"; +}; + +&lpuart5 { /* RS485 */ + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_uart5>; + uart-has-rtscts; + status =3D "okay"; +}; + +&lpuart8 { /* RS232 */ + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_uart8>; + status =3D "okay"; +}; + +&micfil { + #sound-dai-cells =3D <0>; + assigned-clocks =3D <&clk IMX93_CLK_PDM>; + assigned-clock-parents =3D <&clk IMX93_CLK_AUDIO_PLL>; + assigned-clock-rates =3D <196608000>; + status =3D "okay"; +}; + +&mu1 { + status =3D "okay"; +}; + +&mu2 { + status =3D "okay"; +}; + +&sai3 { + #sound-dai-cells =3D <0>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_sai3>; + assigned-clocks =3D <&clk IMX93_CLK_SAI3>; + assigned-clock-parents =3D <&clk IMX93_CLK_AUDIO_PLL>; + assigned-clock-rates =3D <24576000>; + fsl,sai-mclk-direction-output; + status =3D "okay"; +}; + +&usdhc3 { /* WiFi */ + #address-cells =3D <1>; + #size-cells =3D <0>; + pinctrl-names =3D "default", "state_100mhz", "state_200mhz"; + pinctrl-0 =3D <&pinctrl_usdhc3>; + pinctrl-1 =3D <&pinctrl_usdhc3>; + pinctrl-2 =3D <&pinctrl_usdhc3>; + mmc-pwrseq =3D <&usdhc3_pwrseq>; + bus-width =3D <4>; + no-1-8-v; + non-removable; + max-frequency =3D <25000000>; + status =3D "okay"; + + brcmf: bcrmf@1 { + compatible =3D "brcm,bcm4329-fmac"; + reg =3D <1>; + }; +}; + +&wdog3 { + status =3D "okay"; +}; + +&iomuxc { + pinctrl_bluetooth: bluetoothgrp { + fsl,pins =3D < + MX93_PAD_GPIO_IO19__GPIO2_IO19 0x31e /* BT_REG_ON */ + >; + }; + + pinctrl_flexcan1: flexcan1grp { + fsl,pins =3D < + MX93_PAD_PDM_CLK__CAN1_TX 0x139e + MX93_PAD_PDM_BIT_STREAM0__CAN1_RX 0x139e + >; + }; + + pinctrl_flexcan2: flexcan2grp { + fsl,pins =3D < + MX93_PAD_GPIO_IO25__CAN2_TX 0x139e + MX93_PAD_GPIO_IO27__CAN2_RX 0x139e + >; + }; + + pinctrl_lpi2c1: lpi2c1grp { + fsl,pins =3D < + MX93_PAD_I2C1_SCL__LPI2C1_SCL 0x40000b9e + MX93_PAD_I2C1_SDA__LPI2C1_SDA 0x40000b9e + >; + }; + + pinctrl_sai3: sai3grp { + fsl,pins =3D < + MX93_PAD_GPIO_IO26__SAI3_TX_SYNC 0x31e + MX93_PAD_GPIO_IO16__SAI3_TX_BCLK 0x31e + MX93_PAD_GPIO_IO17__SAI3_MCLK 0x31e + MX93_PAD_GPIO_IO21__SAI3_TX_DATA00 0x31e + MX93_PAD_GPIO_IO20__SAI3_RX_DATA00 0x31e + >; + }; + + pinctrl_uart1: uart1grp { + fsl,pins =3D < + MX93_PAD_UART1_RXD__LPUART1_RX 0x31e + MX93_PAD_UART1_TXD__LPUART1_TX 0x31e + >; + }; + + pinctrl_uart5: uart5grp { + fsl,pins =3D < + MX93_PAD_GPIO_IO01__LPUART5_RX 0x31e + MX93_PAD_GPIO_IO00__LPUART5_TX 0x31e + MX93_PAD_GPIO_IO02__LPUART5_CTS_B 0x31e + >; + }; + + pinctrl_uart8: uart8grp { + fsl,pins =3D < + MX93_PAD_GPIO_IO13__LPUART8_RX 0x31e + MX93_PAD_GPIO_IO12__LPUART8_TX 0x31e + >; + }; + + pinctrl_usdhc3: usdhc3grp { + fsl,pins =3D < + MX93_PAD_SD3_CLK__USDHC3_CLK 0x17fe + MX93_PAD_SD3_CMD__USDHC3_CMD 0x13fe + MX93_PAD_SD3_DATA0__USDHC3_DATA0 0x13fe + MX93_PAD_SD3_DATA1__USDHC3_DATA1 0x13fe + MX93_PAD_SD3_DATA2__USDHC3_DATA2 0x13fe + MX93_PAD_SD3_DATA3__USDHC3_DATA3 0x13fe + >; + }; + + pinctrl_usdhc3_pwrseq: usdhc3pwrseqgrp { + fsl,pins =3D < + MX93_PAD_GPIO_IO22__GPIO2_IO22 0x31e /* WL_REG_ON */ + >; + }; +}; --=20 2.34.1