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charset="utf-8" Add dedicated google,gs101-ufs compatible for Google Tensor gs101 SoC. Signed-off-by: Peter Griffin Reviewed-by: Rob Herring (Arm) --- .../bindings/ufs/samsung,exynos-ufs.yaml | 38 +++++++++++++++++-- 1 file changed, 35 insertions(+), 3 deletions(-) diff --git a/Documentation/devicetree/bindings/ufs/samsung,exynos-ufs.yaml = b/Documentation/devicetree/bindings/ufs/samsung,exynos-ufs.yaml index b2b509b3944d..720879820f66 100644 --- a/Documentation/devicetree/bindings/ufs/samsung,exynos-ufs.yaml +++ b/Documentation/devicetree/bindings/ufs/samsung,exynos-ufs.yaml @@ -12,12 +12,10 @@ maintainers: description: | Each Samsung UFS host controller instance should have its own node. =20 -allOf: - - $ref: ufs-common.yaml - properties: compatible: enum: + - google,gs101-ufs - samsung,exynos7-ufs - samsung,exynosautov9-ufs - samsung,exynosautov9-ufs-vh @@ -38,14 +36,24 @@ properties: - const: ufsp =20 clocks: + minItems: 2 items: - description: ufs link core clock - description: unipro main clock + - description: fmp clock + - description: ufs aclk clock + - description: ufs pclk clock + - description: sysreg clock =20 clock-names: + minItems: 2 items: - const: core_clk - const: sclk_unipro_main + - const: fmp + - const: aclk + - const: pclk + - const: sysreg =20 phys: maxItems: 1 @@ -72,6 +80,30 @@ required: - clocks - clock-names =20 +allOf: + - $ref: ufs-common.yaml + - if: + properties: + compatible: + contains: + const: google,gs101-ufs + + then: + properties: + clocks: + minItems: 6 + + clock-names: + minItems: 6 + + else: + properties: + clocks: + maxItems: 2 + + clock-names: + maxItems: 2 + unevaluatedProperties: false =20 examples: --=20 2.44.0.769.g3c40516874-goog From nobody Fri Dec 19 14:06:25 2025 Received: from mail-wr1-f48.google.com (mail-wr1-f48.google.com [209.85.221.48]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D4156145FE7 for ; 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Fri, 26 Apr 2024 05:20:11 -0700 (PDT) Received: from gpeter-l.lan ([2a0d:3344:2e8:8510:63cc:9bae:f542:50e4]) by smtp.gmail.com with ESMTPSA id q2-20020adff942000000b00346bda84bf9sm22478146wrr.78.2024.04.26.05.20.09 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 26 Apr 2024 05:20:10 -0700 (PDT) From: Peter Griffin To: alim.akhtar@samsung.com, avri.altman@wdc.com, bvanassche@acm.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, James.Bottomley@HansenPartnership.com, martin.petersen@oracle.com Cc: linux-scsi@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org, linux-kernel@vger.kernel.org, tudor.ambarus@linaro.org, andre.draszik@linaro.org, saravanak@google.com, willmcvicker@google.com, kernel-team@android.com, Peter Griffin , Krzysztof Kozlowski Subject: [PATCH v3 2/6] scsi: ufs: host: ufs-exynos: Add EXYNOS_UFS_OPT_UFSPR_SECURE option Date: Fri, 26 Apr 2024 13:20:00 +0100 Message-ID: <20240426122004.2249178-3-peter.griffin@linaro.org> X-Mailer: git-send-email 2.44.0.769.g3c40516874-goog In-Reply-To: <20240426122004.2249178-1-peter.griffin@linaro.org> References: <20240426122004.2249178-1-peter.griffin@linaro.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" This option is intended to be set on platforms whose ufspr registers are only accessible via smc call (such as gs101). Signed-off-by: Peter Griffin Acked-by: Krzysztof Kozlowski Tested-by: Will McVicker --- drivers/ufs/host/ufs-exynos.c | 4 +++- drivers/ufs/host/ufs-exynos.h | 1 + 2 files changed, 4 insertions(+), 1 deletion(-) diff --git a/drivers/ufs/host/ufs-exynos.c b/drivers/ufs/host/ufs-exynos.c index e8d3302f6df0..66e52c3607e2 100644 --- a/drivers/ufs/host/ufs-exynos.c +++ b/drivers/ufs/host/ufs-exynos.c @@ -1186,7 +1186,9 @@ static int exynos_ufs_init(struct ufs_hba *hba) if (ret) goto out; exynos_ufs_specify_phy_time_attr(ufs); - exynos_ufs_config_smu(ufs); + + if (!(ufs->opts & EXYNOS_UFS_OPT_UFSPR_SECURE)) + exynos_ufs_config_smu(ufs); =20 hba->host->dma_alignment =3D SZ_4K - 1; return 0; diff --git a/drivers/ufs/host/ufs-exynos.h b/drivers/ufs/host/ufs-exynos.h index a4bd6646d7f1..0fc21b6bbfcd 100644 --- a/drivers/ufs/host/ufs-exynos.h +++ b/drivers/ufs/host/ufs-exynos.h @@ -221,6 +221,7 @@ struct exynos_ufs { #define EXYNOS_UFS_OPT_BROKEN_RX_SEL_IDX BIT(3) #define EXYNOS_UFS_OPT_USE_SW_HIBERN8_TIMER BIT(4) #define EXYNOS_UFS_OPT_SKIP_CONFIG_PHY_ATTR BIT(5) +#define EXYNOS_UFS_OPT_UFSPR_SECURE BIT(6) }; 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charset="utf-8" This option is intended to be set for SoCs that have HCI_V2P1_CTRL register and can select their tick source via IA_TICK_SEL bit. Source clock selection for timer tick 0x0 =3D Bus clock (aclk) 0x1 =3D Function clock (mclk) Signed-off-by: Peter Griffin Acked-by: Krzysztof Kozlowski Tested-by: Will McVicker --- drivers/ufs/host/ufs-exynos.c | 9 +++++++++ drivers/ufs/host/ufs-exynos.h | 1 + 2 files changed, 10 insertions(+) diff --git a/drivers/ufs/host/ufs-exynos.c b/drivers/ufs/host/ufs-exynos.c index 66e52c3607e2..66093a905986 100644 --- a/drivers/ufs/host/ufs-exynos.c +++ b/drivers/ufs/host/ufs-exynos.c @@ -50,6 +50,8 @@ #define HCI_ERR_EN_N_LAYER 0x80 #define HCI_ERR_EN_T_LAYER 0x84 #define HCI_ERR_EN_DME_LAYER 0x88 +#define HCI_V2P1_CTRL 0x8C +#define IA_TICK_SEL BIT(16) #define HCI_CLKSTOP_CTRL 0xB0 #define REFCLKOUT_STOP BIT(4) #define MPHY_APBCLK_STOP BIT(3) @@ -1005,6 +1007,13 @@ static void exynos_ufs_fit_aggr_timeout(struct exyno= s_ufs *ufs) { u32 val; =20 + /* Select function clock (mclk) for timer tick */ + if (ufs->opts & EXYNOS_UFS_OPT_TIMER_TICK_SELECT) { + val =3D hci_readl(ufs, HCI_V2P1_CTRL); + val |=3D IA_TICK_SEL; + hci_writel(ufs, val, HCI_V2P1_CTRL); + } + val =3D exynos_ufs_calc_time_cntr(ufs, IATOVAL_NSEC / CNTR_DIV_VAL); hci_writel(ufs, val & CNT_VAL_1US_MASK, HCI_1US_TO_CNT_VAL); } diff --git a/drivers/ufs/host/ufs-exynos.h b/drivers/ufs/host/ufs-exynos.h index 0fc21b6bbfcd..acf07cc54684 100644 --- a/drivers/ufs/host/ufs-exynos.h +++ b/drivers/ufs/host/ufs-exynos.h @@ -222,6 +222,7 @@ struct exynos_ufs { #define EXYNOS_UFS_OPT_USE_SW_HIBERN8_TIMER BIT(4) #define EXYNOS_UFS_OPT_SKIP_CONFIG_PHY_ATTR BIT(5) #define EXYNOS_UFS_OPT_UFSPR_SECURE BIT(6) +#define EXYNOS_UFS_OPT_TIMER_TICK_SELECT BIT(7) }; =20 #define for_each_ufs_rx_lane(ufs, i) \ --=20 2.44.0.769.g3c40516874-goog From nobody Fri Dec 19 14:06:25 2025 Received: from mail-wr1-f43.google.com (mail-wr1-f43.google.com [209.85.221.43]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id CFDE6146D64 for ; Fri, 26 Apr 2024 12:20:15 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; 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Fri, 26 Apr 2024 05:20:14 -0700 (PDT) Received: from gpeter-l.lan ([2a0d:3344:2e8:8510:63cc:9bae:f542:50e4]) by smtp.gmail.com with ESMTPSA id q2-20020adff942000000b00346bda84bf9sm22478146wrr.78.2024.04.26.05.20.12 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 26 Apr 2024 05:20:14 -0700 (PDT) From: Peter Griffin To: alim.akhtar@samsung.com, avri.altman@wdc.com, bvanassche@acm.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, James.Bottomley@HansenPartnership.com, martin.petersen@oracle.com Cc: linux-scsi@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org, linux-kernel@vger.kernel.org, tudor.ambarus@linaro.org, andre.draszik@linaro.org, saravanak@google.com, willmcvicker@google.com, kernel-team@android.com, Peter Griffin , Krzysztof Kozlowski Subject: [PATCH v3 4/6] scsi: ufs: host: ufs-exynos: allow max frequencies up to 267Mhz Date: Fri, 26 Apr 2024 13:20:02 +0100 Message-ID: <20240426122004.2249178-5-peter.griffin@linaro.org> X-Mailer: git-send-email 2.44.0.769.g3c40516874-goog In-Reply-To: <20240426122004.2249178-1-peter.griffin@linaro.org> References: <20240426122004.2249178-1-peter.griffin@linaro.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Platforms such as Tensor gs101 the pclk frequency is 267Mhz. Increase PCLK_AVAIL_MAX so we don't fail the frequency check. Signed-off-by: Peter Griffin Acked-by: Krzysztof Kozlowski Tested-by: Will McVicker --- drivers/ufs/host/ufs-exynos.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/ufs/host/ufs-exynos.h b/drivers/ufs/host/ufs-exynos.h index acf07cc54684..7acc13914100 100644 --- a/drivers/ufs/host/ufs-exynos.h +++ b/drivers/ufs/host/ufs-exynos.h @@ -116,7 +116,7 @@ struct exynos_ufs; #define PA_HIBERN8TIME_VAL 0x20 =20 #define PCLK_AVAIL_MIN 70000000 -#define PCLK_AVAIL_MAX 167000000 +#define PCLK_AVAIL_MAX 267000000 =20 struct exynos_ufs_uic_attr { /* TX Attributes */ --=20 2.44.0.769.g3c40516874-goog From nobody Fri Dec 19 14:06:25 2025 Received: from mail-wr1-f45.google.com (mail-wr1-f45.google.com [209.85.221.45]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A6F33147C63 for ; Fri, 26 Apr 2024 12:20:17 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; 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Fri, 26 Apr 2024 05:20:16 -0700 (PDT) Received: from gpeter-l.lan ([2a0d:3344:2e8:8510:63cc:9bae:f542:50e4]) by smtp.gmail.com with ESMTPSA id q2-20020adff942000000b00346bda84bf9sm22478146wrr.78.2024.04.26.05.20.14 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 26 Apr 2024 05:20:15 -0700 (PDT) From: Peter Griffin To: alim.akhtar@samsung.com, avri.altman@wdc.com, bvanassche@acm.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, James.Bottomley@HansenPartnership.com, martin.petersen@oracle.com Cc: linux-scsi@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org, linux-kernel@vger.kernel.org, tudor.ambarus@linaro.org, andre.draszik@linaro.org, saravanak@google.com, willmcvicker@google.com, kernel-team@android.com, Peter Griffin , Krzysztof Kozlowski Subject: [PATCH v3 5/6] scsi: ufs: host: ufs-exynos: add some pa_dbg_ register offsets into drvdata Date: Fri, 26 Apr 2024 13:20:03 +0100 Message-ID: <20240426122004.2249178-6-peter.griffin@linaro.org> X-Mailer: git-send-email 2.44.0.769.g3c40516874-goog In-Reply-To: <20240426122004.2249178-1-peter.griffin@linaro.org> References: <20240426122004.2249178-1-peter.griffin@linaro.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" This allows these registers to be at different offsets or not exist at all on some SoCs variants. Signed-off-by: Peter Griffin Acked-by: Krzysztof Kozlowski Tested-by: Will McVicker --- drivers/ufs/host/ufs-exynos.c | 38 ++++++++++++++++++++++++----------- drivers/ufs/host/ufs-exynos.h | 6 +++++- 2 files changed, 31 insertions(+), 13 deletions(-) diff --git a/drivers/ufs/host/ufs-exynos.c b/drivers/ufs/host/ufs-exynos.c index 66093a905986..c086630a96e8 100644 --- a/drivers/ufs/host/ufs-exynos.c +++ b/drivers/ufs/host/ufs-exynos.c @@ -308,8 +308,9 @@ static int exynosauto_ufs_post_pwr_change(struct exynos= _ufs *ufs, =20 static int exynos7_ufs_pre_link(struct exynos_ufs *ufs) { + struct exynos_ufs_uic_attr *attr =3D ufs->drv_data->uic_attr; + u32 val =3D attr->pa_dbg_opt_suite1_val; struct ufs_hba *hba =3D ufs->hba; - u32 val =3D ufs->drv_data->uic_attr->pa_dbg_option_suite; int i; =20 exynos_ufs_enable_ov_tm(hba); @@ -326,12 +327,13 @@ static int exynos7_ufs_pre_link(struct exynos_ufs *uf= s) UIC_ARG_MIB_SEL(TX_HIBERN8_CONTROL, i), 0x0); ufshcd_dme_set(hba, UIC_ARG_MIB(PA_DBG_TXPHY_CFGUPDT), 0x1); udelay(1); - ufshcd_dme_set(hba, UIC_ARG_MIB(PA_DBG_OPTION_SUITE), val | (1 << 12)); + ufshcd_dme_set(hba, UIC_ARG_MIB(attr->pa_dbg_opt_suite1_off), + val | (1 << 12)); ufshcd_dme_set(hba, UIC_ARG_MIB(PA_DBG_SKIP_RESET_PHY), 0x1); ufshcd_dme_set(hba, UIC_ARG_MIB(PA_DBG_SKIP_LINE_RESET), 0x1); ufshcd_dme_set(hba, UIC_ARG_MIB(PA_DBG_LINE_RESET_REQ), 0x1); udelay(1600); - ufshcd_dme_set(hba, UIC_ARG_MIB(PA_DBG_OPTION_SUITE), val); + ufshcd_dme_set(hba, UIC_ARG_MIB(attr->pa_dbg_opt_suite1_off), val); =20 return 0; } @@ -923,14 +925,19 @@ static int exynos_ufs_phy_init(struct exynos_ufs *ufs) =20 static void exynos_ufs_config_unipro(struct exynos_ufs *ufs) { + struct exynos_ufs_uic_attr *attr =3D ufs->drv_data->uic_attr; struct ufs_hba *hba =3D ufs->hba; =20 - ufshcd_dme_set(hba, UIC_ARG_MIB(PA_DBG_CLK_PERIOD), - DIV_ROUND_UP(NSEC_PER_SEC, ufs->mclk_rate)); + if (attr->pa_dbg_clk_period_off) + ufshcd_dme_set(hba, UIC_ARG_MIB(attr->pa_dbg_clk_period_off), + DIV_ROUND_UP(NSEC_PER_SEC, ufs->mclk_rate)); + ufshcd_dme_set(hba, UIC_ARG_MIB(PA_TXTRAILINGCLOCKS), ufs->drv_data->uic_attr->tx_trailingclks); - ufshcd_dme_set(hba, UIC_ARG_MIB(PA_DBG_OPTION_SUITE), - ufs->drv_data->uic_attr->pa_dbg_option_suite); + + if (attr->pa_dbg_opt_suite1_off) + ufshcd_dme_set(hba, UIC_ARG_MIB(attr->pa_dbg_opt_suite1_off), + attr->pa_dbg_opt_suite1_val); } =20 static void exynos_ufs_config_intr(struct exynos_ufs *ufs, u32 errs, u8 in= dex) @@ -1488,10 +1495,11 @@ static int exynosauto_ufs_vh_init(struct ufs_hba *h= ba) =20 static int fsd_ufs_pre_link(struct exynos_ufs *ufs) { - int i; + struct exynos_ufs_uic_attr *attr =3D ufs->drv_data->uic_attr; struct ufs_hba *hba =3D ufs->hba; + int i; =20 - ufshcd_dme_set(hba, UIC_ARG_MIB(PA_DBG_CLK_PERIOD), + ufshcd_dme_set(hba, UIC_ARG_MIB(attr->pa_dbg_clk_period_off), DIV_ROUND_UP(NSEC_PER_SEC, ufs->mclk_rate)); ufshcd_dme_set(hba, UIC_ARG_MIB(0x201), 0x12); ufshcd_dme_set(hba, UIC_ARG_MIB(0x200), 0x40); @@ -1515,7 +1523,9 @@ static int fsd_ufs_pre_link(struct exynos_ufs *ufs) =20 ufshcd_dme_set(hba, UIC_ARG_MIB(0x200), 0x0); ufshcd_dme_set(hba, UIC_ARG_MIB(PA_DBG_AUTOMODE_THLD), 0x4E20); - ufshcd_dme_set(hba, UIC_ARG_MIB(PA_DBG_OPTION_SUITE), 0x2e820183); + + ufshcd_dme_set(hba, UIC_ARG_MIB(attr->pa_dbg_opt_suite1_off), + 0x2e820183); ufshcd_dme_set(hba, UIC_ARG_MIB(PA_LOCAL_TX_LCC_ENABLE), 0x0); =20 exynos_ufs_establish_connt(ufs); @@ -1651,7 +1661,9 @@ static struct exynos_ufs_uic_attr exynos7_uic_attr = =3D { .rx_hs_g1_prep_sync_len_cap =3D PREP_LEN(0xf), .rx_hs_g2_prep_sync_len_cap =3D PREP_LEN(0xf), .rx_hs_g3_prep_sync_len_cap =3D PREP_LEN(0xf), - .pa_dbg_option_suite =3D 0x30103, + .pa_dbg_clk_period_off =3D PA_DBG_CLK_PERIOD, + .pa_dbg_opt_suite1_val =3D 0x30103, + .pa_dbg_opt_suite1_off =3D PA_DBG_OPTION_SUITE, }; =20 static const struct exynos_ufs_drv_data exynosauto_ufs_drvs =3D { @@ -1725,7 +1737,9 @@ static struct exynos_ufs_uic_attr fsd_uic_attr =3D { .rx_hs_g1_prep_sync_len_cap =3D PREP_LEN(0xf), .rx_hs_g2_prep_sync_len_cap =3D PREP_LEN(0xf), .rx_hs_g3_prep_sync_len_cap =3D PREP_LEN(0xf), - .pa_dbg_option_suite =3D 0x2E820183, + .pa_dbg_clk_period_off =3D PA_DBG_CLK_PERIOD, + .pa_dbg_opt_suite1_val =3D 0x2E820183, + .pa_dbg_opt_suite1_off =3D PA_DBG_OPTION_SUITE, }; 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Fri, 26 Apr 2024 05:20:17 -0700 (PDT) Received: from gpeter-l.lan ([2a0d:3344:2e8:8510:63cc:9bae:f542:50e4]) by smtp.gmail.com with ESMTPSA id q2-20020adff942000000b00346bda84bf9sm22478146wrr.78.2024.04.26.05.20.16 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 26 Apr 2024 05:20:17 -0700 (PDT) From: Peter Griffin To: alim.akhtar@samsung.com, avri.altman@wdc.com, bvanassche@acm.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, James.Bottomley@HansenPartnership.com, martin.petersen@oracle.com Cc: linux-scsi@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org, linux-kernel@vger.kernel.org, tudor.ambarus@linaro.org, andre.draszik@linaro.org, saravanak@google.com, willmcvicker@google.com, kernel-team@android.com, Peter Griffin , Krzysztof Kozlowski Subject: [PATCH v3 6/6] scsi: ufs: host: ufs-exynos: Add support for Tensor gs101 SoC Date: Fri, 26 Apr 2024 13:20:04 +0100 Message-ID: <20240426122004.2249178-7-peter.griffin@linaro.org> X-Mailer: git-send-email 2.44.0.769.g3c40516874-goog In-Reply-To: <20240426122004.2249178-1-peter.griffin@linaro.org> References: <20240426122004.2249178-1-peter.griffin@linaro.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add a dedicated compatible and drv_data with associated hooks for gs101 SoC found on Pixel 6. Note we make use of the previously added EXYNOS_UFS_OPT_UFSPR_SECURE option, to skip initialisation of UFSPR registers as these are only accessible via SMC call. EXYNOS_UFS_OPT_TIMER_TICK_SELECT option is also set to select tick source. This has been done so as not to effect any existing platforms. DBG_OPTION_SUITE on gs101 has different address offsets to other SoCs so these register offsets now come from uic_attr struct. Signed-off-by: Peter Griffin Acked-by: Krzysztof Kozlowski Tested-by: Will McVicker --- drivers/ufs/host/ufs-exynos.c | 146 ++++++++++++++++++++++++++++++++++ drivers/ufs/host/ufs-exynos.h | 14 ++++ 2 files changed, 160 insertions(+) diff --git a/drivers/ufs/host/ufs-exynos.c b/drivers/ufs/host/ufs-exynos.c index c086630a96e8..d66dccdc82db 100644 --- a/drivers/ufs/host/ufs-exynos.c +++ b/drivers/ufs/host/ufs-exynos.c @@ -61,6 +61,7 @@ #define CLK_STOP_MASK (REFCLKOUT_STOP | REFCLK_STOP |\ UNIPRO_MCLK_STOP | MPHY_APBCLK_STOP|\ UNIPRO_PCLK_STOP) +/* HCI_MISC is also known as HCI_FORCE_HCS */ #define HCI_MISC 0xB4 #define REFCLK_CTRL_EN BIT(7) #define UNIPRO_PCLK_CTRL_EN BIT(6) @@ -138,6 +139,9 @@ enum { /* * UNIPRO registers */ +#define UNIPRO_DME_POWERMODE_REQ_LOCALL2TIMER0 0x7888 +#define UNIPRO_DME_POWERMODE_REQ_LOCALL2TIMER1 0x788c +#define UNIPRO_DME_POWERMODE_REQ_LOCALL2TIMER2 0x7890 #define UNIPRO_DME_POWERMODE_REQ_REMOTEL2TIMER0 0x78B8 #define UNIPRO_DME_POWERMODE_REQ_REMOTEL2TIMER1 0x78BC #define UNIPRO_DME_POWERMODE_REQ_REMOTEL2TIMER2 0x78C0 @@ -938,6 +942,10 @@ static void exynos_ufs_config_unipro(struct exynos_ufs= *ufs) if (attr->pa_dbg_opt_suite1_off) ufshcd_dme_set(hba, UIC_ARG_MIB(attr->pa_dbg_opt_suite1_off), attr->pa_dbg_opt_suite1_val); + + if (attr->pa_dbg_opt_suite2_off) + ufshcd_dme_set(hba, UIC_ARG_MIB(attr->pa_dbg_opt_suite2_off), + attr->pa_dbg_opt_suite2_val); } =20 static void exynos_ufs_config_intr(struct exynos_ufs *ufs, u32 errs, u8 in= dex) @@ -1589,6 +1597,96 @@ static int fsd_ufs_pre_pwr_change(struct exynos_ufs = *ufs, return 0; } =20 +static inline u32 get_mclk_period_unipro_18(struct exynos_ufs *ufs) +{ + return (16 * 1000 * 1000000UL / ufs->mclk_rate); +} + +static int gs101_ufs_pre_link(struct exynos_ufs *ufs) +{ + struct ufs_hba *hba =3D ufs->hba; + int i; + u32 tx_line_reset_period, rx_line_reset_period; + + rx_line_reset_period =3D (RX_LINE_RESET_TIME * ufs->mclk_rate) + / NSEC_PER_MSEC; + tx_line_reset_period =3D (TX_LINE_RESET_TIME * ufs->mclk_rate) + / NSEC_PER_MSEC; + + unipro_writel(ufs, get_mclk_period_unipro_18(ufs), COMP_CLK_PERIOD); + + ufshcd_dme_set(hba, UIC_ARG_MIB(0x200), 0x40); + + for_each_ufs_rx_lane(ufs, i) { + ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(VND_RX_CLK_PRD, i), + DIV_ROUND_UP(NSEC_PER_SEC, ufs->mclk_rate)); + ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(VND_RX_CLK_PRD_EN, i), 0x0); + ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(VND_RX_LINERESET_VALUE2, i), + (rx_line_reset_period >> 16) & 0xFF); + ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(VND_RX_LINERESET_VALUE1, i), + (rx_line_reset_period >> 8) & 0xFF); + ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(VND_RX_LINERESET_VALUE0, i), + (rx_line_reset_period) & 0xFF); + ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x2f, i), 0x69); + ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x84, i), 0x1); + ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x25, i), 0xf6); + } + + for_each_ufs_tx_lane(ufs, i) { + ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(VND_TX_CLK_PRD, i), + DIV_ROUND_UP(NSEC_PER_SEC, ufs->mclk_rate)); + ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(VND_TX_CLK_PRD_EN, i), + 0x02); + ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(VND_TX_LINERESET_PVALUE2, i), + (tx_line_reset_period >> 16) & 0xFF); + ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(VND_TX_LINERESET_PVALUE1, i), + (tx_line_reset_period >> 8) & 0xFF); + ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(VND_TX_LINERESET_PVALUE0, i), + (tx_line_reset_period) & 0xFF); + ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x04, i), 1); + ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x7F, i), 0); + } + + ufshcd_dme_set(hba, UIC_ARG_MIB(0x200), 0x0); + ufshcd_dme_set(hba, UIC_ARG_MIB(PA_LOCAL_TX_LCC_ENABLE), 0x0); + ufshcd_dme_set(hba, UIC_ARG_MIB(N_DEVICEID), 0x0); + ufshcd_dme_set(hba, UIC_ARG_MIB(N_DEVICEID_VALID), 0x1); + ufshcd_dme_set(hba, UIC_ARG_MIB(T_PEERDEVICEID), 0x1); + ufshcd_dme_set(hba, UIC_ARG_MIB(T_CONNECTIONSTATE), CPORT_CONNECTED); + ufshcd_dme_set(hba, UIC_ARG_MIB(0xA006), 0x8000); + + return 0; +} + +static int gs101_ufs_post_link(struct exynos_ufs *ufs) +{ + struct ufs_hba *hba =3D ufs->hba; + + exynos_ufs_enable_dbg_mode(hba); + ufshcd_dme_set(hba, UIC_ARG_MIB(PA_SAVECONFIGTIME), 0x3e8); + exynos_ufs_disable_dbg_mode(hba); + + return 0; +} + +static int gs101_ufs_pre_pwr_change(struct exynos_ufs *ufs, + struct ufs_pa_layer_attr *pwr) +{ + struct ufs_hba *hba =3D ufs->hba; + + ufshcd_dme_set(hba, UIC_ARG_MIB(PA_PWRMODEUSERDATA0), 12000); + ufshcd_dme_set(hba, UIC_ARG_MIB(PA_PWRMODEUSERDATA1), 32000); + ufshcd_dme_set(hba, UIC_ARG_MIB(PA_PWRMODEUSERDATA2), 16000); + unipro_writel(ufs, 8064, UNIPRO_DME_POWERMODE_REQ_LOCALL2TIMER0); + unipro_writel(ufs, 28224, UNIPRO_DME_POWERMODE_REQ_LOCALL2TIMER1); + unipro_writel(ufs, 20160, UNIPRO_DME_POWERMODE_REQ_LOCALL2TIMER2); + unipro_writel(ufs, 12000, UNIPRO_DME_POWERMODE_REQ_REMOTEL2TIMER0); + unipro_writel(ufs, 32000, UNIPRO_DME_POWERMODE_REQ_REMOTEL2TIMER1); + unipro_writel(ufs, 16000, UNIPRO_DME_POWERMODE_REQ_REMOTEL2TIMER2); + + return 0; +} + static const struct ufs_hba_variant_ops ufs_hba_exynos_ops =3D { .name =3D "exynos_ufs", .init =3D exynos_ufs_init, @@ -1715,6 +1813,34 @@ static const struct exynos_ufs_drv_data exynos_ufs_d= rvs =3D { .post_pwr_change =3D exynos7_ufs_post_pwr_change, }; =20 +static struct exynos_ufs_uic_attr gs101_uic_attr =3D { + .tx_trailingclks =3D 0xff, + .tx_dif_p_nsec =3D 3000000, /* unit: ns */ + .tx_dif_n_nsec =3D 1000000, /* unit: ns */ + .tx_high_z_cnt_nsec =3D 20000, /* unit: ns */ + .tx_base_unit_nsec =3D 100000, /* unit: ns */ + .tx_gran_unit_nsec =3D 4000, /* unit: ns */ + .tx_sleep_cnt =3D 1000, /* unit: ns */ + .tx_min_activatetime =3D 0xa, + .rx_filler_enable =3D 0x2, + .rx_dif_p_nsec =3D 1000000, /* unit: ns */ + .rx_hibern8_wait_nsec =3D 4000000, /* unit: ns */ + .rx_base_unit_nsec =3D 100000, /* unit: ns */ + .rx_gran_unit_nsec =3D 4000, /* unit: ns */ + .rx_sleep_cnt =3D 1280, /* unit: ns */ + .rx_stall_cnt =3D 320, /* unit: ns */ + .rx_hs_g1_sync_len_cap =3D SYNC_LEN_COARSE(0xf), + .rx_hs_g2_sync_len_cap =3D SYNC_LEN_COARSE(0xf), + .rx_hs_g3_sync_len_cap =3D SYNC_LEN_COARSE(0xf), + .rx_hs_g1_prep_sync_len_cap =3D PREP_LEN(0xf), + .rx_hs_g2_prep_sync_len_cap =3D PREP_LEN(0xf), + .rx_hs_g3_prep_sync_len_cap =3D PREP_LEN(0xf), + .pa_dbg_opt_suite1_val =3D 0x90913C1C, + .pa_dbg_opt_suite1_off =3D PA_GS101_DBG_OPTION_SUITE1, + .pa_dbg_opt_suite2_val =3D 0xE01C115F, + .pa_dbg_opt_suite2_off =3D PA_GS101_DBG_OPTION_SUITE2, +}; + static struct exynos_ufs_uic_attr fsd_uic_attr =3D { .tx_trailingclks =3D 0x10, .tx_dif_p_nsec =3D 3000000, /* unit: ns */ @@ -1758,7 +1884,27 @@ static const struct exynos_ufs_drv_data fsd_ufs_drvs= =3D { .pre_pwr_change =3D fsd_ufs_pre_pwr_change, }; =20 +static const struct exynos_ufs_drv_data gs101_ufs_drvs =3D { + .uic_attr =3D &gs101_uic_attr, + .quirks =3D UFSHCD_QUIRK_PRDT_BYTE_GRAN | + UFSHCI_QUIRK_SKIP_RESET_INTR_AGGR | + UFSHCI_QUIRK_BROKEN_REQ_LIST_CLR | + UFSHCD_QUIRK_BROKEN_OCS_FATAL_ERROR | + UFSHCI_QUIRK_SKIP_MANUAL_WB_FLUSH_CTRL | + UFSHCD_QUIRK_SKIP_DEF_UNIPRO_TIMEOUT_SETTING, + .opts =3D EXYNOS_UFS_OPT_BROKEN_AUTO_CLK_CTRL | + EXYNOS_UFS_OPT_SKIP_CONFIG_PHY_ATTR | + EXYNOS_UFS_OPT_UFSPR_SECURE | + EXYNOS_UFS_OPT_TIMER_TICK_SELECT, + .drv_init =3D exynosauto_ufs_drv_init, + .pre_link =3D gs101_ufs_pre_link, + .post_link =3D gs101_ufs_post_link, + .pre_pwr_change =3D gs101_ufs_pre_pwr_change, +}; + static const struct of_device_id exynos_ufs_of_match[] =3D { + { .compatible =3D "google,gs101-ufs", + .data =3D &gs101_ufs_drvs }, { .compatible =3D "samsung,exynos7-ufs", .data =3D &exynos_ufs_drvs }, { .compatible =3D "samsung,exynosautov9-ufs", diff --git a/drivers/ufs/host/ufs-exynos.h b/drivers/ufs/host/ufs-exynos.h index f30423223474..1646c4a9bb08 100644 --- a/drivers/ufs/host/ufs-exynos.h +++ b/drivers/ufs/host/ufs-exynos.h @@ -9,6 +9,12 @@ #ifndef _UFS_EXYNOS_H_ #define _UFS_EXYNOS_H_ =20 +/* + * Component registers + */ + +#define COMP_CLK_PERIOD 0x44 + /* * UNIPRO registers */ @@ -29,6 +35,14 @@ #define PA_DBG_OPTION_SUITE 0x9564 #define PA_DBG_OPTION_SUITE_DYN 0x9565 =20 +/* + * Note: GS101_DBG_OPTION offsets below differ from the TRM + * but match the downstream driver. Following the TRM + * results in non-functioning UFS. + */ +#define PA_GS101_DBG_OPTION_SUITE1 0x956a +#define PA_GS101_DBG_OPTION_SUITE2 0x956d + /* * MIBs for Transport Layer debug registers */ --=20 2.44.0.769.g3c40516874-goog