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charset="utf-8" Document the Inter-Processor Communication Controller on the SDX75 Platform. Signed-off-by: Rohit Agarwal Acked-by: Rob Herring (Arm) --- Documentation/devicetree/bindings/mailbox/qcom-ipcc.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/mailbox/qcom-ipcc.yaml b/Doc= umentation/devicetree/bindings/mailbox/qcom-ipcc.yaml index 8f004868aad9..05e4e1d51713 100644 --- a/Documentation/devicetree/bindings/mailbox/qcom-ipcc.yaml +++ b/Documentation/devicetree/bindings/mailbox/qcom-ipcc.yaml @@ -28,6 +28,7 @@ properties: - qcom,sa8775p-ipcc - qcom,sc7280-ipcc - qcom,sc8280xp-ipcc + - qcom,sdx75-ipcc - qcom,sm6350-ipcc - qcom,sm6375-ipcc - qcom,sm8250-ipcc --=20 2.25.1 From nobody Sun May 19 13:54:38 2024 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 36DE213A3EB; Fri, 26 Apr 2024 05:53:37 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; 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charset="utf-8" Document the qcom,sdx75-tcsr compatible. Signed-off-by: Rohit Agarwal Acked-by: Rob Herring (Arm) --- Documentation/devicetree/bindings/mfd/qcom,tcsr.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/mfd/qcom,tcsr.yaml b/Documen= tation/devicetree/bindings/mfd/qcom,tcsr.yaml index b97d77015335..c6bd14ec5aa0 100644 --- a/Documentation/devicetree/bindings/mfd/qcom,tcsr.yaml +++ b/Documentation/devicetree/bindings/mfd/qcom,tcsr.yaml @@ -28,6 +28,7 @@ properties: - qcom,sdm845-tcsr - qcom,sdx55-tcsr - qcom,sdx65-tcsr + - qcom,sdx75-tcsr - qcom,sm4450-tcsr - qcom,sm6115-tcsr - qcom,sm8150-tcsr --=20 2.25.1 From nobody Sun May 19 13:54:38 2024 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 1F48513A3F2; Fri, 26 Apr 2024 05:53:37 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.168.131 ARC-Seal: i=1; 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charset="utf-8" Document the Always-On Subsystem side channel on the SDX75 Platform. Signed-off-by: Rohit Agarwal Acked-by: Rob Herring (Arm) --- Documentation/devicetree/bindings/soc/qcom/qcom,aoss-qmp.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/soc/qcom/qcom,aoss-qmp.yaml = b/Documentation/devicetree/bindings/soc/qcom/qcom,aoss-qmp.yaml index b4478f417edc..7afdb60edb22 100644 --- a/Documentation/devicetree/bindings/soc/qcom/qcom,aoss-qmp.yaml +++ b/Documentation/devicetree/bindings/soc/qcom/qcom,aoss-qmp.yaml @@ -31,6 +31,7 @@ properties: - qcom,sc7280-aoss-qmp - qcom,sc8180x-aoss-qmp - qcom,sc8280xp-aoss-qmp + - qcom,sdx75-aoss-qmp - qcom,sdm845-aoss-qmp - qcom,sm6350-aoss-qmp - qcom,sm8150-aoss-qmp --=20 2.25.1 From nobody Sun May 19 13:54:38 2024 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id DB33B13A89C; Fri, 26 Apr 2024 05:53:39 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; 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charset="utf-8" Add IPCC devicetree node to Qcom's SDX75 platform. Signed-off-by: Rohit Agarwal --- arch/arm64/boot/dts/qcom/sdx75.dtsi | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sdx75.dtsi b/arch/arm64/boot/dts/qcom= /sdx75.dtsi index 7dbdf8ca6de6..aae4b9ef2bb6 100644 --- a/arch/arm64/boot/dts/qcom/sdx75.dtsi +++ b/arch/arm64/boot/dts/qcom/sdx75.dtsi @@ -441,6 +441,15 @@ gcc: clock-controller@80000 { #power-domain-cells =3D <1>; }; =20 + ipcc: mailbox@408000 { + compatible =3D "qcom,sdx75-ipcc", "qcom,ipcc"; + reg =3D <0 0x00408000 0 0x1000>; + interrupts =3D ; + interrupt-controller; + #interrupt-cells =3D <3>; + #mbox-cells =3D <2>; + }; + qupv3_id_0: geniqup@9c0000 { compatible =3D "qcom,geni-se-qup"; reg =3D <0x0 0x009c0000 0x0 0x2000>; --=20 2.25.1 From nobody Sun May 19 13:54:38 2024 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id AB03913A3FF; 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charset="utf-8" Add TCSR register space devicetree node for accessing different status registers. Signed-off-by: Rohit Agarwal --- arch/arm64/boot/dts/qcom/sdx75.dtsi | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sdx75.dtsi b/arch/arm64/boot/dts/qcom= /sdx75.dtsi index aae4b9ef2bb6..f3f30bbcb37d 100644 --- a/arch/arm64/boot/dts/qcom/sdx75.dtsi +++ b/arch/arm64/boot/dts/qcom/sdx75.dtsi @@ -547,6 +547,11 @@ tcsr_mutex: hwlock@1f40000 { #hwlock-cells =3D <1>; }; =20 + tcsr: syscon@1fc0000 { + compatible =3D "qcom,sdx75-tcsr", "syscon"; + reg =3D <0x0 0x01fc0000 0x0 0x30000>; + }; + usb: usb@a6f8800 { compatible =3D "qcom,sdx75-dwc3", "qcom,dwc3"; reg =3D <0x0 0x0a6f8800 0x0 0x400>; --=20 2.25.1 From nobody Sun May 19 13:54:38 2024 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 0702C13A40D; Fri, 26 Apr 2024 05:53:38 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; 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Fri, 26 Apr 2024 05:53:34 +0000 (GMT) Received: from pps.filterd (APBLRPPMTA01.qualcomm.com [127.0.0.1]) by APBLRPPMTA01.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTP id 43Q5rTVU002267; Fri, 26 Apr 2024 05:53:30 GMT Received: from pps.reinject (localhost [127.0.0.1]) by APBLRPPMTA01.qualcomm.com (PPS) with ESMTPS id 3xm6smm8sv-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Fri, 26 Apr 2024 05:53:30 +0000 Received: from APBLRPPMTA01.qualcomm.com (APBLRPPMTA01.qualcomm.com [127.0.0.1]) by pps.reinject (8.17.1.5/8.17.1.5) with ESMTP id 43Q5rU1g002317; Fri, 26 Apr 2024 05:53:30 GMT Received: from hu-devc-hyd-u20-c-new.qualcomm.com (hu-rohiagar-hyd.qualcomm.com [10.147.246.70]) by APBLRPPMTA01.qualcomm.com (PPS) with ESMTPS id 43Q5rUIP002316 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Fri, 26 Apr 2024 05:53:30 +0000 Received: by hu-devc-hyd-u20-c-new.qualcomm.com (Postfix, from userid 3970568) id 9C9D220FFA; Fri, 26 Apr 2024 11:23:29 +0530 (+0530) From: Rohit Agarwal To: andersson@kernel.org, konrad.dybcio@linaro.org, manivannan.sadhasivam@linaro.org, jassisinghbrar@gmail.com, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, lee@kernel.org Cc: linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, kernel@quicinc.com, Rohit Agarwal Subject: [PATCH 6/6] arm64: dts: qcom: sdx75: Add AOSS node Date: Fri, 26 Apr 2024 11:23:26 +0530 Message-Id: <20240426055326.3141727-7-quic_rohiagar@quicinc.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20240426055326.3141727-1-quic_rohiagar@quicinc.com> References: <20240426055326.3141727-1-quic_rohiagar@quicinc.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-QCInternal: smtphost X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: BQA0EkTmXJP2GKNKjdhARbfvKoSCLIyP X-Proofpoint-GUID: BQA0EkTmXJP2GKNKjdhARbfvKoSCLIyP X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1011,Hydra:6.0.650,FMLib:17.11.176.26 definitions=2024-04-26_06,2024-04-25_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 impostorscore=0 mlxscore=0 lowpriorityscore=0 bulkscore=0 malwarescore=0 adultscore=0 clxscore=1015 priorityscore=1501 phishscore=0 mlxlogscore=720 suspectscore=0 spamscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2404010003 definitions=main-2404260034 Content-Type: text/plain; charset="utf-8" Add AOSS channel devicetree node for Qcom's SDX75 SoC. Signed-off-by: Rohit Agarwal --- arch/arm64/boot/dts/qcom/sdx75.dtsi | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sdx75.dtsi b/arch/arm64/boot/dts/qcom= /sdx75.dtsi index f3f30bbcb37d..96e3eec57008 100644 --- a/arch/arm64/boot/dts/qcom/sdx75.dtsi +++ b/arch/arm64/boot/dts/qcom/sdx75.dtsi @@ -11,6 +11,7 @@ #include #include #include +#include #include #include #include @@ -641,6 +642,17 @@ pdc: interrupt-controller@b220000 { interrupt-controller; }; =20 + aoss_qmp: power-controller@c310000 { + compatible =3D "qcom,sdx75-aoss-qmp", "qcom,aoss-qmp"; + reg =3D <0 0x0c310000 0 0x1000>; + interrupt-parent =3D <&ipcc>; + interrupts-extended =3D <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_= QMP + IRQ_TYPE_EDGE_RISING>; + mboxes =3D <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP>; + + #clock-cells =3D <0>; + }; + spmi_bus: spmi@c400000 { compatible =3D "qcom,spmi-pmic-arb"; reg =3D <0x0 0x0c400000 0x0 0x3000>, --=20 2.25.1