From nobody Mon Feb 9 22:59:54 2026 Received: from forward500a.mail.yandex.net (forward500a.mail.yandex.net [178.154.239.80]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 24A6038394; Thu, 25 Apr 2024 18:34:30 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=178.154.239.80 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1714070073; cv=none; b=Y1AxMstO8pWkO2UZodH8hAs4pFhUSUZ1pRs2Aw2PZTIbmsev1Karx0GUnSLam3Re/aIDhQNz0YeNLvQaOIwN00mK50CpCfrw/ZcRtC2hW7kVm2I01Yrxh4zmn6DQDBmYNskkzZEZijDw/NuAwh1g7ygHEBx84sI+BUUHrEJHIzg= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1714070073; c=relaxed/simple; bh=eU757TTOhrp3nqCrS3IG22krPVIGPyJJiFw7dCBBFJg=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=t3iYTiET2lJzUVd3aYlhYLU5vsKJsx3fc/WKEMdIX0gpIpi5PzJHclCU0VY4ATiZX+QGcB+3SOvTKncMJb3HuRIiiaVqEp/4cgiszy2CChNBsxjvHJWnPgyW6qMwR/qmlk1pnzMUPbFpro9q2NAGXXtWAELuQ0kMwlMe1GPnJUI= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=ya.ru; spf=pass smtp.mailfrom=ya.ru; dkim=pass (1024-bit key) header.d=ya.ru header.i=@ya.ru header.b=tguj/VwK; arc=none smtp.client-ip=178.154.239.80 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=ya.ru Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=ya.ru Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=ya.ru header.i=@ya.ru header.b="tguj/VwK" Received: from mail-nwsmtp-smtp-production-main-52.vla.yp-c.yandex.net (mail-nwsmtp-smtp-production-main-52.vla.yp-c.yandex.net [IPv6:2a02:6b8:c1f:5408:0:640:72fa:0]) by forward500a.mail.yandex.net (Yandex) with ESMTPS id 836EB611D7; Thu, 25 Apr 2024 21:34:22 +0300 (MSK) Received: by mail-nwsmtp-smtp-production-main-52.vla.yp-c.yandex.net (smtp/Yandex) with ESMTPSA id sXRDEK0m5mI0-Jqe0LEmc; Thu, 25 Apr 2024 21:34:21 +0300 X-Yandex-Fwd: 1 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ya.ru; s=mail; t=1714070061; bh=wcQC09O7wivdpBoR+Y+aDE9+dxGqTZ9it4Rg80L4qPk=; h=Message-ID:Date:In-Reply-To:Cc:Subject:References:To:From; b=tguj/VwKnyJmeA/ni/M2qq4XMxyL+McxCiv39pvI25NUv4TaQkW/0yuwzh93mIjtB Pxi+Qb3rmvvk+APMupEEZU6y3v+BoYpEnyw9Wuxv05vCXCnjj59qet9t5fgjQ06tWm L0LPiIc8ADuhFqoCfVFTU6c3TnZ2MzpH15smksdw= Authentication-Results: mail-nwsmtp-smtp-production-main-52.vla.yp-c.yandex.net; dkim=pass header.i=@ya.ru From: Konstantin Pugin To: Cc: krzk@kernel.org, conor@kernel.org, lkp@intel.com, vz@mleia.com, robh@kernel.org, jcmvbkbc@gmail.com, nicolas.ferre@microchip.com, manikanta.guntupalli@amd.com, corbet@lwn.net, ychuang3@nuvoton.com, u.kleine-koenig@pengutronix.de, Maarten.Brock@sttls.nl, Konstantin Pugin , Andy Shevchenko , Greg Kroah-Hartman , Jiri Slaby , Andy Shevchenko , Herve Codina , =?UTF-8?q?Ilpo=20J=C3=A4rvinen?= , Anup Patel , Hugo Villeneuve , Lech Perczak , linux-kernel@vger.kernel.org, linux-serial@vger.kernel.org Subject: [PATCH v9 3/3] serial: sc16is7xx: add support for EXAR XR20M1172 UART Date: Thu, 25 Apr 2024 21:32:35 +0300 Message-ID: <20240425183251.174412-4-rilian.la.te@ya.ru> X-Mailer: git-send-email 2.44.0 In-Reply-To: <20240425183251.174412-1-rilian.la.te@ya.ru> References: <20240425183251.174412-1-rilian.la.te@ya.ru> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Konstantin Pugin XR20M1172 register set is mostly compatible with SC16IS762, but it supports for additional division rates with special DLD register. Reviewed-by: Andy Shevchenko Signed-off-by: Konstantin Pugin --- drivers/tty/serial/Kconfig | 3 +- drivers/tty/serial/sc16is7xx.c | 61 ++++++++++++++++++++++++++++-- drivers/tty/serial/sc16is7xx.h | 1 + drivers/tty/serial/sc16is7xx_i2c.c | 1 + drivers/tty/serial/sc16is7xx_spi.c | 1 + 5 files changed, 62 insertions(+), 5 deletions(-) diff --git a/drivers/tty/serial/Kconfig b/drivers/tty/serial/Kconfig index 4fdd7857ef4d..9d0438cfe147 100644 --- a/drivers/tty/serial/Kconfig +++ b/drivers/tty/serial/Kconfig @@ -1029,7 +1029,7 @@ config SERIAL_SC16IS7XX_CORE select SERIAL_SC16IS7XX_SPI if SPI_MASTER select SERIAL_SC16IS7XX_I2C if I2C help - Core driver for NXP SC16IS7xx UARTs. + Core driver for NXP SC16IS7xx and compatible UARTs. Supported ICs are: =20 SC16IS740 @@ -1038,6 +1038,7 @@ config SERIAL_SC16IS7XX_CORE SC16IS752 SC16IS760 SC16IS762 + XR20M1172 (Exar) =20 The driver supports both I2C and SPI interfaces. =20 diff --git a/drivers/tty/serial/sc16is7xx.c b/drivers/tty/serial/sc16is7xx.c index dfcc804f558f..2b40600243a9 100644 --- a/drivers/tty/serial/sc16is7xx.c +++ b/drivers/tty/serial/sc16is7xx.c @@ -10,6 +10,7 @@ #undef DEFAULT_SYMBOL_NAMESPACE #define DEFAULT_SYMBOL_NAMESPACE SERIAL_NXP_SC16IS7XX =20 +#include #include #include #include @@ -68,6 +69,7 @@ /* Special Register set: Only if ((LCR[7] =3D=3D 1) && (LCR !=3D 0xBF)) */ #define SC16IS7XX_DLL_REG (0x00) /* Divisor Latch Low */ #define SC16IS7XX_DLH_REG (0x01) /* Divisor Latch High */ +#define XR20M117X_DLD_REG (0x02) /* Divisor Fractional (requires EFR[4] = =3D 1) */ =20 /* Enhanced Register set: Only if (LCR =3D=3D 0xBF) */ #define SC16IS7XX_EFR_REG (0x02) /* Enhanced Features */ @@ -221,6 +223,20 @@ #define SC16IS7XX_TCR_RX_HALT(words) ((((words) / 4) & 0x0f) << 0) #define SC16IS7XX_TCR_RX_RESUME(words) ((((words) / 4) & 0x0f) << 4) =20 +/* + * Divisor Fractional Register bits (EXAR extension). + * EXAR hardware is mostly compatible with SC16IS7XX, but supports additio= nal feature: + * 4x and 8x divisor, instead of default 16x. It has a special register to= program it. + * Bits 0 to 3 is fractional divisor, it used to set value of last 16 bits= of + * uartclk * (16 / divisor) / baud, in case of default it will be uartclk = / baud. + * Bits 4 and 5 used as switches, and should not be set to 1 simultaneousl= y. + */ + +#define XR20M117X_DLD_16X 0 +#define XR20M117X_DLD_DIV_MASK GENMASK(3, 0) +#define XR20M117X_DLD_8X BIT(4) +#define XR20M117X_DLD_4X BIT(5) + /* * TLR register bits * If TLR[3:0] or TLR[7:4] are logical 0, the selectable trigger levels vi= a the @@ -523,6 +539,13 @@ const struct sc16is7xx_devtype sc16is762_devtype =3D { }; EXPORT_SYMBOL_GPL(sc16is762_devtype); =20 +const struct sc16is7xx_devtype xr20m1172_devtype =3D { + .name =3D "XR20M1172", + .nr_gpio =3D 8, + .nr_uart =3D 2, +}; +EXPORT_SYMBOL_GPL(xr20m1172_devtype); + static bool sc16is7xx_regmap_volatile(struct device *dev, unsigned int reg) { switch (reg) { @@ -555,18 +578,43 @@ static bool sc16is7xx_regmap_noinc(struct device *dev= , unsigned int reg) return reg =3D=3D SC16IS7XX_RHR_REG; } =20 +static bool sc16is7xx_has_dld(struct device *dev) +{ + struct sc16is7xx_port *s =3D dev_get_drvdata(dev); + + if (s->devtype =3D=3D &xr20m1172_devtype) + return true; + return false; +} + static int sc16is7xx_set_baud(struct uart_port *port, int baud) { struct sc16is7xx_one *one =3D to_sc16is7xx_one(port, port); - u8 lcr; + unsigned long clk =3D port->uartclk, div, div16; + bool has_dld =3D sc16is7xx_has_dld(port->dev); + u8 dld_mode =3D XR20M117X_DLD_16X; u8 prescaler =3D 0; - unsigned long clk =3D port->uartclk, div =3D clk / 16 / baud; + u8 divisor =3D 16; + u8 lcr; + + if (has_dld && DIV_ROUND_CLOSEST(clk, baud) < 16) + divisor =3D rounddown_pow_of_two(DIV_ROUND_CLOSEST(clk, baud)); + + div16 =3D (clk * 16) / divisor / baud; + div =3D div16 / 16; =20 if (div >=3D BIT(16)) { prescaler =3D SC16IS7XX_MCR_CLKSEL_BIT; div /=3D 4; } =20 + /* Count additional divisor for EXAR devices */ + if (divisor =3D=3D 8) + dld_mode =3D XR20M117X_DLD_8X; + if (divisor =3D=3D 4) + dld_mode =3D XR20M117X_DLD_4X; + dld_mode |=3D FIELD_PREP(XR20M117X_DLD_DIV_MASK, div16); + /* Enable enhanced features */ sc16is7xx_efr_lock(port); sc16is7xx_port_update(port, SC16IS7XX_EFR_REG, @@ -587,12 +635,14 @@ static int sc16is7xx_set_baud(struct uart_port *port,= int baud) regcache_cache_bypass(one->regmap, true); sc16is7xx_port_write(port, SC16IS7XX_DLH_REG, div / 256); sc16is7xx_port_write(port, SC16IS7XX_DLL_REG, div % 256); + if (has_dld) + sc16is7xx_port_write(port, XR20M117X_DLD_REG, dld_mode); regcache_cache_bypass(one->regmap, false); =20 /* Restore LCR and access to general register set */ sc16is7xx_port_write(port, SC16IS7XX_LCR_REG, lcr); =20 - return DIV_ROUND_CLOSEST(clk / 16, div); + return DIV_ROUND_CLOSEST(clk / divisor, div); } =20 static void sc16is7xx_handle_rx(struct uart_port *port, unsigned int rxlen, @@ -1002,6 +1052,8 @@ static void sc16is7xx_set_termios(struct uart_port *p= ort, const struct ktermios *old) { struct sc16is7xx_one *one =3D to_sc16is7xx_one(port, port); + bool has_dld =3D sc16is7xx_has_dld(port->dev); + u8 divisor =3D has_dld ? 4 : 16; unsigned int lcr, flow =3D 0; int baud; unsigned long flags; @@ -1084,7 +1136,7 @@ static void sc16is7xx_set_termios(struct uart_port *p= ort, /* Get baud rate generator configuration */ baud =3D uart_get_baud_rate(port, termios, old, port->uartclk / 16 / 4 / 0xffff, - port->uartclk / 16); + port->uartclk / divisor); =20 /* Setup baudrate generator */ baud =3D sc16is7xx_set_baud(port, baud); @@ -1684,6 +1736,7 @@ void sc16is7xx_remove(struct device *dev) EXPORT_SYMBOL_GPL(sc16is7xx_remove); =20 const struct of_device_id __maybe_unused sc16is7xx_dt_ids[] =3D { + { .compatible =3D "exar,xr20m1172", .data =3D &xr20m1172_devtype, }, { .compatible =3D "nxp,sc16is740", .data =3D &sc16is74x_devtype, }, { .compatible =3D "nxp,sc16is741", .data =3D &sc16is74x_devtype, }, { .compatible =3D "nxp,sc16is750", .data =3D &sc16is750_devtype, }, diff --git a/drivers/tty/serial/sc16is7xx.h b/drivers/tty/serial/sc16is7xx.h index afb784eaee45..eb2e3bc86f15 100644 --- a/drivers/tty/serial/sc16is7xx.h +++ b/drivers/tty/serial/sc16is7xx.h @@ -28,6 +28,7 @@ extern const struct sc16is7xx_devtype sc16is750_devtype; extern const struct sc16is7xx_devtype sc16is752_devtype; extern const struct sc16is7xx_devtype sc16is760_devtype; extern const struct sc16is7xx_devtype sc16is762_devtype; +extern const struct sc16is7xx_devtype xr20m1172_devtype; =20 const char *sc16is7xx_regmap_name(u8 port_id); =20 diff --git a/drivers/tty/serial/sc16is7xx_i2c.c b/drivers/tty/serial/sc16is= 7xx_i2c.c index 3ed47c306d85..839de902821b 100644 --- a/drivers/tty/serial/sc16is7xx_i2c.c +++ b/drivers/tty/serial/sc16is7xx_i2c.c @@ -46,6 +46,7 @@ static const struct i2c_device_id sc16is7xx_i2c_id_table[= ] =3D { { "sc16is752", (kernel_ulong_t)&sc16is752_devtype, }, { "sc16is760", (kernel_ulong_t)&sc16is760_devtype, }, { "sc16is762", (kernel_ulong_t)&sc16is762_devtype, }, + { "xr20m1172", (kernel_ulong_t)&xr20m1172_devtype, }, { } }; MODULE_DEVICE_TABLE(i2c, sc16is7xx_i2c_id_table); diff --git a/drivers/tty/serial/sc16is7xx_spi.c b/drivers/tty/serial/sc16is= 7xx_spi.c index 73df36f8a7fd..2b278282dbd0 100644 --- a/drivers/tty/serial/sc16is7xx_spi.c +++ b/drivers/tty/serial/sc16is7xx_spi.c @@ -69,6 +69,7 @@ static const struct spi_device_id sc16is7xx_spi_id_table[= ] =3D { { "sc16is752", (kernel_ulong_t)&sc16is752_devtype, }, { "sc16is760", (kernel_ulong_t)&sc16is760_devtype, }, { "sc16is762", (kernel_ulong_t)&sc16is762_devtype, }, + { "xr20m1172", (kernel_ulong_t)&xr20m1172_devtype, }, { } }; MODULE_DEVICE_TABLE(spi, sc16is7xx_spi_id_table); --=20 2.44.0