From nobody Sat Jul 11 15:40:01 2026 Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.19]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id CD54216D9B8; Wed, 24 Apr 2024 18:14:46 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=192.198.163.19 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1713982488; cv=none; b=RCfNXC+0bdirx6/K7ryCVnh0TAg5gBVX/2xBFbaVwkyVy/NCjFisUxUhu5C7lJWIa/quJ8pa6MjR/+dL11x5X1KfVproi+c6eM7XXBKGRNSvxHFtXEf169ZzNTRh+3g9+q81aBOuC1sGyf8T6321riAk1oJlClhaovJEWmfBhyY= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1713982488; c=relaxed/simple; bh=/rcxfZFq/If/iTRicqHHlhcazvtiWYDXEQfNN+mI/L8=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=OFbl8zyx4H4dAZdJmJizi3DQOZu8l11/9ApBHjPSgh9UcsuU7wBOg16+UTUD4hIMS4+DwDaogNb4SamDFUthzNh8/5YhCgZqanWKYgzFkIWwpjP58HnU0GVvw1g77AW+4L/nb+VTbSaxfgu1Nm2x2xAQPiKicsTwQwhzQybTIEA= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com; spf=pass smtp.mailfrom=intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=nV1Mcb4r; arc=none smtp.client-ip=192.198.163.19 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="nV1Mcb4r" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1713982487; x=1745518487; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=/rcxfZFq/If/iTRicqHHlhcazvtiWYDXEQfNN+mI/L8=; b=nV1Mcb4rcCUmK8JD4aUajHq93x1lVE3COeCEbrisPgO/n2hBHFELmL8O 73GBjiV5RftFAGvOxbrj+pmFJCK8JG7VelSPYQJo9ncuRWrvDUF1lYPIe PAUor+qu6fDQCUhDepd6tlTnLAD86hwCtDYVDfPCfJWH37Bhvl7MYX8+z yPD4pEfpnX6VD5cd0GYIX3bxujGPsfKuU9kA0Vp3o0acKWjYyHJMRE5hJ ZtVGUMCgS95+6yHKmsi/9jAJOjOaPivsBhIzB4yo1016wbs4fhvmjXE+6 +Yy6vfxrShS0wxo8PdBbACJ6kOXHKcZmY7GiGHWdFXZz7+ASaSpmYPxO/ w==; X-CSE-ConnectionGUID: LWIis1T5R9azUSBFzohPzg== X-CSE-MsgGUID: NZlkd1huSr2VQg3dXkS9tw== X-IronPort-AV: E=McAfee;i="6600,9927,11054"; a="9503359" X-IronPort-AV: E=Sophos;i="6.07,226,1708416000"; d="scan'208";a="9503359" Received: from orviesa010.jf.intel.com ([10.64.159.150]) by fmvoesa113.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 24 Apr 2024 11:14:45 -0700 X-CSE-ConnectionGUID: Mfu24fcYRIKkqr0c4/Ro3g== X-CSE-MsgGUID: vyJyAnfjRqG8FTeojm3WLw== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.07,226,1708416000"; d="scan'208";a="24683647" Received: from agluck-desk3.sc.intel.com ([172.25.222.105]) by orviesa010-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 24 Apr 2024 11:14:45 -0700 From: Tony Luck To: Borislav Petkov , Peter Huewe , Jarkko Sakkinen Cc: Jason Gunthorpe , linux-integrity@vger.kernel.org, linux-kernel@vger.kernel.org, patches@lists.linux.dev, Tony Luck Subject: [PATCH v4 01/71] tpm: Switch to new Intel CPU model defines Date: Wed, 24 Apr 2024 11:14:44 -0700 Message-ID: <20240424181444.41174-1-tony.luck@intel.com> X-Mailer: git-send-email 2.44.0 In-Reply-To: <20240424181245.41141-1-tony.luck@intel.com> References: <20240424181245.41141-1-tony.luck@intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" New CPU #defines encode vendor and family as well as model. Signed-off-by: Tony Luck Reviewed-by: Jarkko Sakkinen Acked-by: Hans de Goede --- drivers/char/tpm/tpm.h | 2 +- drivers/char/tpm/tpm_tis_core.h | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/char/tpm/tpm.h b/drivers/char/tpm/tpm.h index 61445f1dc46d..7b38ce007bdc 100644 --- a/drivers/char/tpm/tpm.h +++ b/drivers/char/tpm/tpm.h @@ -28,7 +28,7 @@ #include =20 #ifdef CONFIG_X86 -#include +#include #endif =20 #define TPM_MINOR 224 /* officially assigned */ diff --git a/drivers/char/tpm/tpm_tis_core.h b/drivers/char/tpm/tpm_tis_cor= e.h index 13e99cf65efe..c940fd18988e 100644 --- a/drivers/char/tpm/tpm_tis_core.h +++ b/drivers/char/tpm/tpm_tis_core.h @@ -210,7 +210,7 @@ static inline int tpm_tis_verify_crc(struct tpm_tis_dat= a *data, size_t len, static inline bool is_bsw(void) { #ifdef CONFIG_X86 - return ((boot_cpu_data.x86_model =3D=3D INTEL_FAM6_ATOM_AIRMONT) ? 1 : 0); + return ((boot_cpu_data.x86_vfm =3D=3D INTEL_ATOM_AIRMONT) ? 1 : 0); #else return false; #endif --=20 2.44.0 From nobody Sat Jul 11 15:40:01 2026 Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.19]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 3C6F116D9D8; Wed, 24 Apr 2024 18:14:48 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=192.198.163.19 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1713982490; cv=none; b=MPinb3uPWD99aAz/n2QtKDcrrnsM1iKuqMjTZU8T3Iki3mjWtmm/4F5YOtVPm5qH9I3mXO2gCEg+kA127RigVV/WkhhcdCEfZ7bNKdt096pWAbEmk5XpCI5mBS7/DClEjtH/rKWNcD+JeaRyfxXukTAsr1fAk5HJjgED8hv4BdY= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1713982490; c=relaxed/simple; bh=yQ5L+dbNHtvkAp/pj5zzra7nuxWzgvQKIkDpzo8Sudc=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=DtVkeZqv2gDfdJDwSyY7LitSTwwyt1OK3Tjik3Mrm66zjjeZVlhmFlaqLP+8L6dLV/E0attbJuW3F9uEAdMg1wJ7RNZfSlEChv1xexfycgPFwctZ08UN6ND2qffygZStsa3zwzmK+f6H4OGGtIuMvmUVVjpNrwU0ruQBZySTENc= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com; spf=pass smtp.mailfrom=intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=j2YH92De; arc=none smtp.client-ip=192.198.163.19 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="j2YH92De" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1713982488; x=1745518488; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=yQ5L+dbNHtvkAp/pj5zzra7nuxWzgvQKIkDpzo8Sudc=; b=j2YH92DerdBsb3j2CULYHy6xGiznmxpCkIUbkRTODj0lmdYCglH8fuG7 ZbSH8mm0KJvCtFL092gbtwibGfqA17bPjSQHCULZdtGYHFiG1ujcZFPPE UMWxSwlRfKOJB9wV5Ih6HATNUOJ+8EFJ+LISiYhLRhzzgqBI0r8g3KVc3 Kdk+KR0iLDEWdjzO58FFddm5KlctBZrLqFow9264sKloLbT/Ej+RPx8Fg YQF2DwK+TKe+3fTLUkId0JT1by2aCFYLGxpqe5GceyVg8K5hBQAwdyB8r 2BJiZnwxdzIUebt0MpMw9pTR0if7FSugLCXOhdW87DL/HjJh1Hl5njGH4 Q==; X-CSE-ConnectionGUID: Y05e2gROSh66M3N7mTXVlA== X-CSE-MsgGUID: vspZE9jjSHqK3qMPnpoRbA== X-IronPort-AV: E=McAfee;i="6600,9927,11054"; a="9503368" X-IronPort-AV: E=Sophos;i="6.07,226,1708416000"; d="scan'208";a="9503368" Received: from orviesa010.jf.intel.com ([10.64.159.150]) by fmvoesa113.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 24 Apr 2024 11:14:46 -0700 X-CSE-ConnectionGUID: mb43gOObTESWrDtc6+X6xA== X-CSE-MsgGUID: NiRwbu/jRtevqmqHDB1oEg== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.07,226,1708416000"; d="scan'208";a="24683653" Received: from agluck-desk3.sc.intel.com ([172.25.222.105]) by orviesa010-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 24 Apr 2024 11:14:46 -0700 From: Tony Luck To: Borislav Petkov , Jithu Joseph , Hans de Goede , =?UTF-8?q?Ilpo=20J=C3=A4rvinen?= Cc: Ashok Raj , Tony Luck , platform-driver-x86@vger.kernel.org, linux-kernel@vger.kernel.org, patches@lists.linux.dev Subject: [PATCH v4 02/71] platform/x86/intel/ifs: Switch to new Intel CPU model defines Date: Wed, 24 Apr 2024 11:14:45 -0700 Message-ID: <20240424181445.41193-1-tony.luck@intel.com> X-Mailer: git-send-email 2.44.0 In-Reply-To: <20240424181245.41141-1-tony.luck@intel.com> References: <20240424181245.41141-1-tony.luck@intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" New CPU #defines encode vendor and family as well as model. Signed-off-by: Tony Luck Reviewed-by: Jithu Joseph Acked-by: Hans de Goede Reviewed-by: Kuppuswamy Sathyanarayanan --- drivers/platform/x86/intel/ifs/core.c | 15 +++++++-------- 1 file changed, 7 insertions(+), 8 deletions(-) diff --git a/drivers/platform/x86/intel/ifs/core.c b/drivers/platform/x86/i= ntel/ifs/core.c index 7b11198d85a1..33412a584836 100644 --- a/drivers/platform/x86/intel/ifs/core.c +++ b/drivers/platform/x86/intel/ifs/core.c @@ -11,16 +11,15 @@ =20 #include "ifs.h" =20 -#define X86_MATCH(model, array_gen) \ - X86_MATCH_VENDOR_FAM_MODEL_FEATURE(INTEL, 6, \ - INTEL_FAM6_##model, X86_FEATURE_CORE_CAPABILITIES, array_gen) +#define X86_MATCH(vfm, array_gen) \ + X86_MATCH_VFM_FEATURE(vfm, X86_FEATURE_CORE_CAPABILITIES, array_gen) =20 static const struct x86_cpu_id ifs_cpu_ids[] __initconst =3D { - X86_MATCH(SAPPHIRERAPIDS_X, ARRAY_GEN0), - X86_MATCH(EMERALDRAPIDS_X, ARRAY_GEN0), - X86_MATCH(GRANITERAPIDS_X, ARRAY_GEN0), - X86_MATCH(GRANITERAPIDS_D, ARRAY_GEN0), - X86_MATCH(ATOM_CRESTMONT_X, ARRAY_GEN1), + X86_MATCH(INTEL_SAPPHIRERAPIDS_X, ARRAY_GEN0), + X86_MATCH(INTEL_EMERALDRAPIDS_X, ARRAY_GEN0), + X86_MATCH(INTEL_GRANITERAPIDS_X, ARRAY_GEN0), + X86_MATCH(INTEL_GRANITERAPIDS_D, ARRAY_GEN0), + X86_MATCH(INTEL_ATOM_CRESTMONT_X, ARRAY_GEN1), {} }; MODULE_DEVICE_TABLE(x86cpu, ifs_cpu_ids); --=20 2.44.0 From nobody Sat Jul 11 15:40:01 2026 Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.19]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 6A57A16D9DE; Wed, 24 Apr 2024 18:14:48 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=192.198.163.19 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1713982489; cv=none; b=S+sQv/c8BuhGYbsRWk1cHmUwYB7SOGr4shr9ZbxxR0OtpTKeK+u1P6Evd5PhMuhprbzDYx+V3QVNYrhVCsZrAsRjHkiG0aqEvwGuwST+HDbxAdzXSVtq5pwwdgDzpLi700KiX1Kt0cm7XfCxLZBLmY9pE60YrxsEJwlCBO5BPmE= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1713982489; c=relaxed/simple; bh=kkF0kOmubRaABW0Hf14QsZUk5Z9XWIfvaI1+06NWDic=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=CvGXdUGon7srow/BJ9ONwhHD46OZ2VC0Fo66rHDUG2ywPqY4Axy/uD7Io4paJIqRWZG9gq10sNpRYBvWldAY5awQ128Vh5PMRZVj/7hWn8DLty2lTv2NVyPpdbNWTC7pCPBfcl92yopuy1cVz+Fd9FwZM+IcelpY0vBwY/t6h6U= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com; spf=pass smtp.mailfrom=intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=VT/bioXR; arc=none smtp.client-ip=192.198.163.19 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="VT/bioXR" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1713982488; x=1745518488; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=kkF0kOmubRaABW0Hf14QsZUk5Z9XWIfvaI1+06NWDic=; b=VT/bioXRfEpqWYyn8QbY6SY5XgZlTbkDuNok+q/MDdgwbn+zxovExB08 l3xWnAEcDxDHLMGe2ho65VLUij47MUR2QbT6CXf4GB89VvFyLviE85bjH 7xbSCHDXuRD1+BVdM0Sp3HyJ/7+4hbn49auGFUrzJw2dRUAgeI2+Ga4wf gd4yyXlA4tt0gkPY63B6IT5DRrfTOdPKQFPLSDYYWUsmW5IKt65zQnFTZ WKIYs+ONXPShIYZ7Rjo731rBcgzSSPcSRfPqFfUbVRnFZ9AND6F7MPKuy KyyoLpdo0dAWMgg7gjZ/Tn/lPLIoDpQP94P7C+/4gNz65zp+CJvmPvKMB g==; X-CSE-ConnectionGUID: Qg8ZnJioQYafVr9/be98aA== X-CSE-MsgGUID: gpsBp6dvTlOB1dQkNH1QdQ== X-IronPort-AV: E=McAfee;i="6600,9927,11054"; a="9503378" X-IronPort-AV: E=Sophos;i="6.07,226,1708416000"; d="scan'208";a="9503378" Received: from orviesa010.jf.intel.com ([10.64.159.150]) by fmvoesa113.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 24 Apr 2024 11:14:47 -0700 X-CSE-ConnectionGUID: yRuNC9RIQPOiq37fhZbzPg== X-CSE-MsgGUID: z01KKwbxTIKkzN3BFVKWSQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.07,226,1708416000"; d="scan'208";a="24683658" Received: from agluck-desk3.sc.intel.com ([172.25.222.105]) by orviesa010-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 24 Apr 2024 11:14:47 -0700 From: Tony Luck To: Borislav Petkov , Thomas Gleixner , Ingo Molnar , Dave Hansen , x86@kernel.org Cc: Sean Christopherson , Paolo Bonzini , "H. Peter Anvin" , kvm@vger.kernel.org, linux-kernel@vger.kernel.org, patches@lists.linux.dev, Tony Luck Subject: [PATCH v4 03/71] KVM: x86/pmu: Switch to new Intel CPU model defines Date: Wed, 24 Apr 2024 11:14:46 -0700 Message-ID: <20240424181446.41212-1-tony.luck@intel.com> X-Mailer: git-send-email 2.44.0 In-Reply-To: <20240424181245.41141-1-tony.luck@intel.com> References: <20240424181245.41141-1-tony.luck@intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" New CPU #defines encode vendor and family as well as model. Signed-off-by: Tony Luck Acked-by: Sean Christopherson Acked-by: Hans de Goede --- arch/x86/kvm/pmu.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/x86/kvm/pmu.c b/arch/x86/kvm/pmu.c index c397b28e3d1b..2faa67a4bfb6 100644 --- a/arch/x86/kvm/pmu.c +++ b/arch/x86/kvm/pmu.c @@ -34,16 +34,16 @@ EXPORT_SYMBOL_GPL(kvm_pmu_eventsel); =20 /* Precise Distribution of Instructions Retired (PDIR) */ static const struct x86_cpu_id vmx_pebs_pdir_cpu[] =3D { - X86_MATCH_INTEL_FAM6_MODEL(ICELAKE_D, NULL), - X86_MATCH_INTEL_FAM6_MODEL(ICELAKE_X, NULL), + X86_MATCH_VFM(INTEL_ICELAKE_D, NULL), + X86_MATCH_VFM(INTEL_ICELAKE_X, NULL), /* Instruction-Accurate PDIR (PDIR++) */ - X86_MATCH_INTEL_FAM6_MODEL(SAPPHIRERAPIDS_X, NULL), + X86_MATCH_VFM(INTEL_SAPPHIRERAPIDS_X, NULL), {} }; =20 /* Precise Distribution (PDist) */ static const struct x86_cpu_id vmx_pebs_pdist_cpu[] =3D { - X86_MATCH_INTEL_FAM6_MODEL(SAPPHIRERAPIDS_X, NULL), + X86_MATCH_VFM(INTEL_SAPPHIRERAPIDS_X, NULL), {} }; =20 --=20 2.44.0 From nobody Sat Jul 11 15:40:01 2026 Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.19]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 317E916DEAF; Wed, 24 Apr 2024 18:14:49 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=192.198.163.19 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1713982490; cv=none; b=mbwcrLJojwreVkCjhlfV0rT4neD27JXvJXi9XMiamcOx3Z8kBCQm2yblpZ9Fur1LK889Q6mG1MB9jADzB4WN/++4h8z51xW3zgzSgVhEopZ+2N9rWZSS9c+oLak9owIAHe2N+eBo9AJgETg3oNiqsQ1X/dR6UhjAeMiZZTEpYsk= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1713982490; c=relaxed/simple; bh=DTmj/yYZ5S3zG9s0UR1lWeqfV7XL+xXwEY+aB15HzFA=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=YvrXqCkv9nZGmXY/yx+ztBmyOedfURy0Mxu2r6wt7EFXeORPaesp56WQRCdoQGaM9KAsVU/UGmBoV12+8Qte0D9K0PKnbeuT0IN61kG/Wrwh52cnssqSSCk9AzfwkCQkF8cnC0VtA8HSudJGTfEVIVBXzoMvhYk9zjU9nsv5Fbc= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com; spf=pass smtp.mailfrom=intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=b3CBYKil; arc=none smtp.client-ip=192.198.163.19 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="b3CBYKil" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1713982489; x=1745518489; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=DTmj/yYZ5S3zG9s0UR1lWeqfV7XL+xXwEY+aB15HzFA=; b=b3CBYKilboprpZlWgzdqD9tQA4AP6fVl0WRLarLasUSCMg9QKrvPfIYz m8pugqBFi0x2+W3SUeU7/J2qBb/F9SCh2yWle26XQznBAcgLkjkEDixBB WMKaAenJ9j4tdnmk2mJCMoJiDnvnjF7LbtLQY12ek8xZkEj+XtwQydGdQ D0EJsAAAGPsUXOnDdafZyQwP0xLCels9GdCkAc4sRQx/uTvJLMOILXpAq 2vGcFW4PXXtyJ8d1c5X/Fi4fag74nIKg+UgJQDb/tT1dqIyrvSSvOS2eK q/GcqVSYdfJ6/PdSZe7PIXRBvuK8Yid8C7BgMciF/0Fkc1H2pqNu103Cm A==; X-CSE-ConnectionGUID: ABbjj0LRT9KRNRChC0+mUQ== X-CSE-MsgGUID: iZOF3LVsTk6u2BRYDysHCw== X-IronPort-AV: E=McAfee;i="6600,9927,11054"; a="9503390" X-IronPort-AV: E=Sophos;i="6.07,226,1708416000"; d="scan'208";a="9503390" Received: from orviesa010.jf.intel.com ([10.64.159.150]) by fmvoesa113.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 24 Apr 2024 11:14:48 -0700 X-CSE-ConnectionGUID: 8YGYbTfMQSmqKIpYGLP9mg== X-CSE-MsgGUID: iJt3JCwTSSe45nPXccqmjw== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.07,226,1708416000"; d="scan'208";a="24683664" Received: from agluck-desk3.sc.intel.com ([172.25.222.105]) by orviesa010-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 24 Apr 2024 11:14:48 -0700 From: Tony Luck To: Borislav Petkov , Thomas Gleixner , Ingo Molnar , Dave Hansen , x86@kernel.org Cc: Sean Christopherson , Paolo Bonzini , "H. Peter Anvin" , kvm@vger.kernel.org, linux-kernel@vger.kernel.org, patches@lists.linux.dev, Tony Luck Subject: [PATCH v4 04/71] KVM: VMX: Switch to new Intel CPU model defines Date: Wed, 24 Apr 2024 11:14:47 -0700 Message-ID: <20240424181447.41231-1-tony.luck@intel.com> X-Mailer: git-send-email 2.44.0 In-Reply-To: <20240424181245.41141-1-tony.luck@intel.com> References: <20240424181245.41141-1-tony.luck@intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" New CPU #defines encode vendor and family as well as model. Signed-off-by: Tony Luck Acked-by: Sean Christopherson Acked-by: Hans de Goede --- arch/x86/kvm/vmx/vmx.c | 20 +++++++++----------- 1 file changed, 9 insertions(+), 11 deletions(-) diff --git a/arch/x86/kvm/vmx/vmx.c b/arch/x86/kvm/vmx/vmx.c index c37a89eda90f..2c747f2642c6 100644 --- a/arch/x86/kvm/vmx/vmx.c +++ b/arch/x86/kvm/vmx/vmx.c @@ -2518,17 +2518,15 @@ static bool cpu_has_sgx(void) */ static bool cpu_has_perf_global_ctrl_bug(void) { - if (boot_cpu_data.x86 =3D=3D 0x6) { - switch (boot_cpu_data.x86_model) { - case INTEL_FAM6_NEHALEM_EP: /* AAK155 */ - case INTEL_FAM6_NEHALEM: /* AAP115 */ - case INTEL_FAM6_WESTMERE: /* AAT100 */ - case INTEL_FAM6_WESTMERE_EP: /* BC86,AAY89,BD102 */ - case INTEL_FAM6_NEHALEM_EX: /* BA97 */ - return true; - default: - break; - } + switch (boot_cpu_data.x86_vfm) { + case INTEL_NEHALEM_EP: /* AAK155 */ + case INTEL_NEHALEM: /* AAP115 */ + case INTEL_WESTMERE: /* AAT100 */ + case INTEL_WESTMERE_EP: /* BC86,AAY89,BD102 */ + case INTEL_NEHALEM_EX: /* BA97 */ + return true; + default: + break; } =20 return false; --=20 2.44.0 From nobody Sat Jul 11 15:40:01 2026 Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.18]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C6AD516D9D9; Wed, 24 Apr 2024 18:14:49 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=192.198.163.18 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1713982491; cv=none; b=kpGOCNCq1aX1JmJRGKsbYcB6Kmf2RGPraYSCuLIQ70vfM9nE6NPwxD0AQGnwR/Jv8P73V7xNn2dczUL1IbIbrPTO78IXiD8wDYHHYFKY2I6knNcfzAFIonrgnQrBHiDt9o5ODNNecLX+BOZ2fdqpYTrbE3np5rpGr+LQ+XyIv3o= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1713982491; c=relaxed/simple; bh=qqh/VHYxTuSJACNe+DTpuXgw37TddvW3ou6MW1MJcG0=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=K5SY6UKYgTR3VpFeKuBt39SY0kt44S0k3Pa7CI7jGe1zQXNN+NbuEFpZ2yCgHRKy6qvUQy3huBVmbKeEfZymxWWQNTKd6sBmdk7KqY3HRiunHl5GPFAZ1WuKjJfEgHWDwZYGe4dBhi7p/OUbNwKSI+0anjl38MygxqQytQzJBQs= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com; spf=pass smtp.mailfrom=intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=Bm66JzdO; arc=none smtp.client-ip=192.198.163.18 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="Bm66JzdO" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1713982489; x=1745518489; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=qqh/VHYxTuSJACNe+DTpuXgw37TddvW3ou6MW1MJcG0=; b=Bm66JzdO1i2kieT4Ve/xbE+xYCeXhTF40qz7EBZ+2WMnzxITxwTe4d1N htyclF55WISg8bnsf4CEcLsfeko3VFRLW6JoQtRclz9rnlLPEB2DHVjm+ NWUCgmqxDpWn7276q1NLIbSLJb3REvRQd7tZWyeNKi75pWQu6jEaV7/3K 32wooXG/TNeZZOdMOTTl1QW8xmWBTvm026Vo7fzCYCcoWmCaBxL/SRsRH QAkGcBlN5TMpKb0/cUD6tsG0/yoyydgPBwlqq4kdAdUBDZwUdO4ube6Q4 3cbyT2jSewDRNSKLtydcASrYm9tFYG8dz5hMGy1trINAmPoSJpC1bpWHD w==; X-CSE-ConnectionGUID: iwMu7bIIQqmxOjJ5AV4LIw== X-CSE-MsgGUID: vqzDdE0jS6ySzZDBtRhCgw== X-IronPort-AV: E=McAfee;i="6600,9927,11054"; a="9481749" X-IronPort-AV: E=Sophos;i="6.07,226,1708416000"; d="scan'208";a="9481749" Received: from fmviesa005.fm.intel.com ([10.60.135.145]) by fmvoesa112.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 24 Apr 2024 11:14:49 -0700 X-CSE-ConnectionGUID: w/FG+NFSS2O32W04eODo/A== X-CSE-MsgGUID: TyV1YTNzQUOZ4tB6OMugag== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.07,226,1708416000"; d="scan'208";a="29262548" Received: from agluck-desk3.sc.intel.com ([172.25.222.105]) by fmviesa005-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 24 Apr 2024 11:14:49 -0700 From: Tony Luck To: Borislav Petkov , linux-kernel@vger.kernel.org Cc: "Rafael J. Wysocki" , Len Brown , linux-acpi@vger.kernel.org, patches@lists.linux.dev, Tony Luck , "Rafael J . Wysocki" Subject: [PATCH v4 05/71] ACPI: LPSS: Switch to new Intel CPU model defines Date: Wed, 24 Apr 2024 11:14:48 -0700 Message-ID: <20240424181448.41250-1-tony.luck@intel.com> X-Mailer: git-send-email 2.44.0 In-Reply-To: <20240424181245.41141-1-tony.luck@intel.com> References: <20240424181245.41141-1-tony.luck@intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" New CPU #defines encode vendor and family as well as model. Signed-off-by: Tony Luck Acked-by: Rafael J. Wysocki Acked-by: Hans de Goede --- drivers/acpi/acpi_lpss.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/acpi/acpi_lpss.c b/drivers/acpi/acpi_lpss.c index 04e273167e92..e7b57dcce146 100644 --- a/drivers/acpi/acpi_lpss.c +++ b/drivers/acpi/acpi_lpss.c @@ -337,8 +337,8 @@ static const struct lpss_device_desc bsw_spi_dev_desc = =3D { }; =20 static const struct x86_cpu_id lpss_cpu_ids[] =3D { - X86_MATCH_INTEL_FAM6_MODEL(ATOM_SILVERMONT, NULL), - X86_MATCH_INTEL_FAM6_MODEL(ATOM_AIRMONT, NULL), + X86_MATCH_VFM(INTEL_ATOM_SILVERMONT, NULL), + X86_MATCH_VFM(INTEL_ATOM_AIRMONT, NULL), {} }; =20 --=20 2.44.0 From nobody Sat Jul 11 15:40:01 2026 Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.18]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id EDF3F16E888; Wed, 24 Apr 2024 18:14:50 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=192.198.163.18 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1713982492; cv=none; b=ruKynOssVe8wGVpQeN46NkGDWNvtH08zA27M+mhgcktqS3cKr/ckXGZ1FYWO3ddJ7w0cG7R9rilj6PvDThvNmZ2U/w3vYcEwnfzV7RpwO5pjZVyTLOqLbtD/Qo2LqC4MlEaCDAirvc9zAaywP1ZyVFMd0tnNSMzWG4PjB96XHJU= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1713982492; c=relaxed/simple; bh=khsp430wCZF85FG8u7FCOLvv9K3w859TzG0TQy2mIZU=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=f8npXbw9fa0NcnJEdmULqDGknqow6ebHVJNLwwH8DqW5YOsArSOWfnXOqycJo9ICs3iWz1uHVergVl3wDwJR48uoji+dwDjjjJi+xAmha8woNeQjKS/872r9Ic5l7xmgZodAnnaqpngQsAFtIgjkarPfCIKdfN48O747ksCUaBs= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com; spf=pass smtp.mailfrom=intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=C9ZJIpcv; arc=none smtp.client-ip=192.198.163.18 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="C9ZJIpcv" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1713982491; x=1745518491; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=khsp430wCZF85FG8u7FCOLvv9K3w859TzG0TQy2mIZU=; b=C9ZJIpcv5dnzUt8fzmw8Rt9cy9TcqD8x36qtZQ+Jx0cnEgkWg+Xk76Sw LBRsB2SDQGrg7zyc19o3OWzkcX7eaMT/+jQF/FXixik3tIaMqApkc53lG PEBAQC5uD9yQClUE53EFpzxKz3eVoB6mbL5ZSlxUiw9fHPOgSShpbi12Z orJpUBwvXzDa8IS5Yb00YxC/nn3R5+wb/T1RGIYW0L3DtvsEcddUXTe9Q +JpP0hp5ZUjbhl5liNlKxeei69opYZ3pFSbU1vNGsj6kZX2Jl4BnmrQck 6uwpNGDdU1tFXuMSwU8GsQ2woJUgxb8IMaGp2/4JZ8mRR/tBPYKXSzeaZ A==; X-CSE-ConnectionGUID: Kap8YXqORs2mBzVRJpUhhg== X-CSE-MsgGUID: GVt4/XxqS5++bKsdiB4j6A== X-IronPort-AV: E=McAfee;i="6600,9927,11054"; a="9481756" X-IronPort-AV: E=Sophos;i="6.07,226,1708416000"; d="scan'208";a="9481756" Received: from fmviesa005.fm.intel.com ([10.60.135.145]) by fmvoesa112.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 24 Apr 2024 11:14:50 -0700 X-CSE-ConnectionGUID: ArE35bv8SxStrrmql8SDQw== X-CSE-MsgGUID: PiYV0wPNTq6UdpwkazL6kQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.07,226,1708416000"; d="scan'208";a="29262553" Received: from agluck-desk3.sc.intel.com ([172.25.222.105]) by fmviesa005-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 24 Apr 2024 11:14:50 -0700 From: Tony Luck To: Borislav Petkov , linux-kernel@vger.kernel.org Cc: "Rafael J. Wysocki" , Len Brown , Hans de Goede , Mika Westerberg , Raag Jadav , Marius Hoch , Tony Luck , Michal Wilczynski , linux-acpi@vger.kernel.org, patches@lists.linux.dev, "Rafael J . Wysocki" Subject: [PATCH v4 06/71] ACPI: x86: Switch to new Intel CPU model defines Date: Wed, 24 Apr 2024 11:14:49 -0700 Message-ID: <20240424181450.41270-1-tony.luck@intel.com> X-Mailer: git-send-email 2.44.0 In-Reply-To: <20240424181245.41141-1-tony.luck@intel.com> References: <20240424181245.41141-1-tony.luck@intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" New CPU #defines encode vendor and family as well as model. Signed-off-by: Tony Luck Acked-by: Rafael J. Wysocki Acked-by: Hans de Goede --- drivers/acpi/x86/utils.c | 42 ++++++++++++++++++++-------------------- 1 file changed, 21 insertions(+), 21 deletions(-) diff --git a/drivers/acpi/x86/utils.c b/drivers/acpi/x86/utils.c index 90c3d2eab9e9..2d8203f7bd98 100644 --- a/drivers/acpi/x86/utils.c +++ b/drivers/acpi/x86/utils.c @@ -45,37 +45,37 @@ struct override_status_id { unsigned long long status; }; =20 -#define ENTRY(status, hid, uid, path, cpu_model, dmi...) { \ +#define ENTRY(status, hid, uid, path, cpu_vfm, dmi...) { \ { { hid, }, {} }, \ - { X86_MATCH_INTEL_FAM6_MODEL(cpu_model, NULL), {} }, \ + { X86_MATCH_VFM(cpu_vfm, NULL), {} }, \ { { .matches =3D dmi }, {} }, \ uid, \ path, \ status, \ } =20 -#define PRESENT_ENTRY_HID(hid, uid, cpu_model, dmi...) \ - ENTRY(ACPI_STA_DEFAULT, hid, uid, NULL, cpu_model, dmi) +#define PRESENT_ENTRY_HID(hid, uid, cpu_vfm, dmi...) \ + ENTRY(ACPI_STA_DEFAULT, hid, uid, NULL, cpu_vfm, dmi) =20 -#define NOT_PRESENT_ENTRY_HID(hid, uid, cpu_model, dmi...) \ - ENTRY(0, hid, uid, NULL, cpu_model, dmi) +#define NOT_PRESENT_ENTRY_HID(hid, uid, cpu_vfm, dmi...) \ + ENTRY(0, hid, uid, NULL, cpu_vfm, dmi) =20 -#define PRESENT_ENTRY_PATH(path, cpu_model, dmi...) \ - ENTRY(ACPI_STA_DEFAULT, "", NULL, path, cpu_model, dmi) +#define PRESENT_ENTRY_PATH(path, cpu_vfm, dmi...) \ + ENTRY(ACPI_STA_DEFAULT, "", NULL, path, cpu_vfm, dmi) =20 -#define NOT_PRESENT_ENTRY_PATH(path, cpu_model, dmi...) \ - ENTRY(0, "", NULL, path, cpu_model, dmi) +#define NOT_PRESENT_ENTRY_PATH(path, cpu_vfm, dmi...) \ + ENTRY(0, "", NULL, path, cpu_vfm, dmi) =20 static const struct override_status_id override_status_ids[] =3D { /* * Bay / Cherry Trail PWM directly poked by GPU driver in win10, * but Linux uses a separate PWM driver, harmless if not used. */ - PRESENT_ENTRY_HID("80860F09", "1", ATOM_SILVERMONT, {}), - PRESENT_ENTRY_HID("80862288", "1", ATOM_AIRMONT, {}), + PRESENT_ENTRY_HID("80860F09", "1", INTEL_ATOM_SILVERMONT, {}), + PRESENT_ENTRY_HID("80862288", "1", INTEL_ATOM_AIRMONT, {}), =20 /* The Xiaomi Mi Pad 2 uses PWM2 for touchkeys backlight control */ - PRESENT_ENTRY_HID("80862289", "2", ATOM_AIRMONT, { + PRESENT_ENTRY_HID("80862289", "2", INTEL_ATOM_AIRMONT, { DMI_MATCH(DMI_SYS_VENDOR, "Xiaomi Inc"), DMI_MATCH(DMI_PRODUCT_NAME, "Mipad2"), }), @@ -84,18 +84,18 @@ static const struct override_status_id override_status_= ids[] =3D { * The INT0002 device is necessary to clear wakeup interrupt sources * on Cherry Trail devices, without it we get nobody cared IRQ msgs. */ - PRESENT_ENTRY_HID("INT0002", "1", ATOM_AIRMONT, {}), + PRESENT_ENTRY_HID("INT0002", "1", INTEL_ATOM_AIRMONT, {}), /* * On the Dell Venue 11 Pro 7130 and 7139, the DSDT hides * the touchscreen ACPI device until a certain time * after _SB.PCI0.GFX0.LCD.LCD1._ON gets called has passed * *and* _STA has been called at least 3 times since. */ - PRESENT_ENTRY_HID("SYNA7500", "1", HASWELL_L, { + PRESENT_ENTRY_HID("SYNA7500", "1", INTEL_HASWELL_L, { DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."), DMI_MATCH(DMI_PRODUCT_NAME, "Venue 11 Pro 7130"), }), - PRESENT_ENTRY_HID("SYNA7500", "1", HASWELL_L, { + PRESENT_ENTRY_HID("SYNA7500", "1", INTEL_HASWELL_L, { DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."), DMI_MATCH(DMI_PRODUCT_NAME, "Venue 11 Pro 7139"), }), @@ -112,19 +112,19 @@ static const struct override_status_id override_statu= s_ids[] =3D { * was copy-pasted from the GPD win, so it has a disabled KIOX000A * node which we should not enable, thus we also check the BIOS date. */ - PRESENT_ENTRY_HID("KIOX000A", "1", ATOM_AIRMONT, { + PRESENT_ENTRY_HID("KIOX000A", "1", INTEL_ATOM_AIRMONT, { DMI_MATCH(DMI_BOARD_VENDOR, "AMI Corporation"), DMI_MATCH(DMI_BOARD_NAME, "Default string"), DMI_MATCH(DMI_PRODUCT_NAME, "Default string"), DMI_MATCH(DMI_BIOS_DATE, "02/21/2017") }), - PRESENT_ENTRY_HID("KIOX000A", "1", ATOM_AIRMONT, { + PRESENT_ENTRY_HID("KIOX000A", "1", INTEL_ATOM_AIRMONT, { DMI_MATCH(DMI_BOARD_VENDOR, "AMI Corporation"), DMI_MATCH(DMI_BOARD_NAME, "Default string"), DMI_MATCH(DMI_PRODUCT_NAME, "Default string"), DMI_MATCH(DMI_BIOS_DATE, "03/20/2017") }), - PRESENT_ENTRY_HID("KIOX000A", "1", ATOM_AIRMONT, { + PRESENT_ENTRY_HID("KIOX000A", "1", INTEL_ATOM_AIRMONT, { DMI_MATCH(DMI_BOARD_VENDOR, "AMI Corporation"), DMI_MATCH(DMI_BOARD_NAME, "Default string"), DMI_MATCH(DMI_PRODUCT_NAME, "Default string"), @@ -137,7 +137,7 @@ static const struct override_status_id override_status_= ids[] =3D { * method sets a GPIO causing the PCI wifi card to turn off. * See above remark about uniqueness of the DMI match. */ - NOT_PRESENT_ENTRY_PATH("\\_SB_.PCI0.SDHB.BRC1", ATOM_AIRMONT, { + NOT_PRESENT_ENTRY_PATH("\\_SB_.PCI0.SDHB.BRC1", INTEL_ATOM_AIRMONT, { DMI_EXACT_MATCH(DMI_BOARD_VENDOR, "AMI Corporation"), DMI_EXACT_MATCH(DMI_BOARD_NAME, "Default string"), DMI_EXACT_MATCH(DMI_BOARD_SERIAL, "Default string"), @@ -149,7 +149,7 @@ static const struct override_status_id override_status_= ids[] =3D { * as both ACCL0001 and MAGN0001. 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Wysocki" , Viresh Kumar Cc: Srinivas Pandruvada , Len Brown , linux-pm@vger.kernel.org, linux-kernel@vger.kernel.org, patches@lists.linux.dev, Tony Luck , "Rafael J . Wysocki" Subject: [PATCH v4 07/71] cpufreq: intel_pstate: Switch to new Intel CPU model defines Date: Wed, 24 Apr 2024 11:14:50 -0700 Message-ID: <20240424181450.41289-1-tony.luck@intel.com> X-Mailer: git-send-email 2.44.0 In-Reply-To: <20240424181245.41141-1-tony.luck@intel.com> References: <20240424181245.41141-1-tony.luck@intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" New CPU #defines encode vendor and family as well as model. Signed-off-by: Tony Luck Acked-by: Rafael J. Wysocki Acked-by: Hans de Goede --- drivers/cpufreq/intel_pstate.c | 90 +++++++++++++++++----------------- 1 file changed, 44 insertions(+), 46 deletions(-) diff --git a/drivers/cpufreq/intel_pstate.c b/drivers/cpufreq/intel_pstate.c index dbbf299f4219..685ec80e0af5 100644 --- a/drivers/cpufreq/intel_pstate.c +++ b/drivers/cpufreq/intel_pstate.c @@ -2402,52 +2402,51 @@ static const struct pstate_funcs knl_funcs =3D { .get_val =3D core_get_val, }; =20 -#define X86_MATCH(model, policy) \ - X86_MATCH_VENDOR_FAM_MODEL_FEATURE(INTEL, 6, INTEL_FAM6_##model, \ - X86_FEATURE_APERFMPERF, &policy) +#define X86_MATCH(vfm, policy) \ + X86_MATCH_VFM_FEATURE(vfm, X86_FEATURE_APERFMPERF, &policy) =20 static const struct x86_cpu_id intel_pstate_cpu_ids[] =3D { - X86_MATCH(SANDYBRIDGE, core_funcs), - X86_MATCH(SANDYBRIDGE_X, core_funcs), - X86_MATCH(ATOM_SILVERMONT, silvermont_funcs), - X86_MATCH(IVYBRIDGE, core_funcs), - X86_MATCH(HASWELL, core_funcs), - X86_MATCH(BROADWELL, core_funcs), - X86_MATCH(IVYBRIDGE_X, core_funcs), - X86_MATCH(HASWELL_X, core_funcs), - X86_MATCH(HASWELL_L, core_funcs), - X86_MATCH(HASWELL_G, core_funcs), - X86_MATCH(BROADWELL_G, core_funcs), - X86_MATCH(ATOM_AIRMONT, airmont_funcs), - X86_MATCH(SKYLAKE_L, core_funcs), - X86_MATCH(BROADWELL_X, core_funcs), - X86_MATCH(SKYLAKE, core_funcs), - X86_MATCH(BROADWELL_D, core_funcs), - X86_MATCH(XEON_PHI_KNL, knl_funcs), - X86_MATCH(XEON_PHI_KNM, knl_funcs), - X86_MATCH(ATOM_GOLDMONT, core_funcs), - X86_MATCH(ATOM_GOLDMONT_PLUS, core_funcs), - X86_MATCH(SKYLAKE_X, core_funcs), - X86_MATCH(COMETLAKE, core_funcs), - X86_MATCH(ICELAKE_X, core_funcs), - X86_MATCH(TIGERLAKE, core_funcs), - X86_MATCH(SAPPHIRERAPIDS_X, core_funcs), - X86_MATCH(EMERALDRAPIDS_X, core_funcs), + X86_MATCH(INTEL_SANDYBRIDGE, core_funcs), + X86_MATCH(INTEL_SANDYBRIDGE_X, core_funcs), + X86_MATCH(INTEL_ATOM_SILVERMONT, silvermont_funcs), + X86_MATCH(INTEL_IVYBRIDGE, core_funcs), + X86_MATCH(INTEL_HASWELL, core_funcs), + X86_MATCH(INTEL_BROADWELL, core_funcs), + X86_MATCH(INTEL_IVYBRIDGE_X, core_funcs), + X86_MATCH(INTEL_HASWELL_X, core_funcs), + X86_MATCH(INTEL_HASWELL_L, core_funcs), + X86_MATCH(INTEL_HASWELL_G, core_funcs), + X86_MATCH(INTEL_BROADWELL_G, core_funcs), + X86_MATCH(INTEL_ATOM_AIRMONT, airmont_funcs), + X86_MATCH(INTEL_SKYLAKE_L, core_funcs), + X86_MATCH(INTEL_BROADWELL_X, core_funcs), + X86_MATCH(INTEL_SKYLAKE, core_funcs), + X86_MATCH(INTEL_BROADWELL_D, core_funcs), + X86_MATCH(INTEL_XEON_PHI_KNL, knl_funcs), + X86_MATCH(INTEL_XEON_PHI_KNM, knl_funcs), + X86_MATCH(INTEL_ATOM_GOLDMONT, core_funcs), + X86_MATCH(INTEL_ATOM_GOLDMONT_PLUS, core_funcs), + X86_MATCH(INTEL_SKYLAKE_X, core_funcs), + X86_MATCH(INTEL_COMETLAKE, core_funcs), + X86_MATCH(INTEL_ICELAKE_X, core_funcs), + X86_MATCH(INTEL_TIGERLAKE, core_funcs), + X86_MATCH(INTEL_SAPPHIRERAPIDS_X, core_funcs), + X86_MATCH(INTEL_EMERALDRAPIDS_X, core_funcs), {} }; MODULE_DEVICE_TABLE(x86cpu, intel_pstate_cpu_ids); =20 static const struct x86_cpu_id intel_pstate_cpu_oob_ids[] __initconst =3D { - X86_MATCH(BROADWELL_D, core_funcs), - X86_MATCH(BROADWELL_X, core_funcs), - X86_MATCH(SKYLAKE_X, core_funcs), - X86_MATCH(ICELAKE_X, core_funcs), - X86_MATCH(SAPPHIRERAPIDS_X, core_funcs), + X86_MATCH(INTEL_BROADWELL_D, core_funcs), + X86_MATCH(INTEL_BROADWELL_X, core_funcs), + X86_MATCH(INTEL_SKYLAKE_X, core_funcs), + X86_MATCH(INTEL_ICELAKE_X, core_funcs), + X86_MATCH(INTEL_SAPPHIRERAPIDS_X, core_funcs), {} }; =20 static const struct x86_cpu_id intel_pstate_cpu_ee_disable_ids[] =3D { - X86_MATCH(KABYLAKE, core_funcs), + X86_MATCH(INTEL_KABYLAKE, core_funcs), {} }; =20 @@ -3386,14 +3385,13 @@ static inline void intel_pstate_request_control_fro= m_smm(void) {} =20 #define INTEL_PSTATE_HWP_BROADWELL 0x01 =20 -#define X86_MATCH_HWP(model, hwp_mode) \ - X86_MATCH_VENDOR_FAM_MODEL_FEATURE(INTEL, 6, INTEL_FAM6_##model, \ - X86_FEATURE_HWP, hwp_mode) +#define X86_MATCH_HWP(vfm, hwp_mode) \ + X86_MATCH_VFM_FEATURE(vfm, X86_FEATURE_HWP, hwp_mode) =20 static const struct x86_cpu_id hwp_support_ids[] __initconst =3D { - X86_MATCH_HWP(BROADWELL_X, INTEL_PSTATE_HWP_BROADWELL), - X86_MATCH_HWP(BROADWELL_D, INTEL_PSTATE_HWP_BROADWELL), - X86_MATCH_HWP(ANY, 0), + X86_MATCH_HWP(INTEL_BROADWELL_X, INTEL_PSTATE_HWP_BROADWELL), + X86_MATCH_HWP(INTEL_BROADWELL_D, INTEL_PSTATE_HWP_BROADWELL), + X86_MATCH_HWP(INTEL_ANY, 0), {} }; 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a="9481772" X-IronPort-AV: E=Sophos;i="6.07,226,1708416000"; d="scan'208";a="9481772" Received: from fmviesa005.fm.intel.com ([10.60.135.145]) by fmvoesa112.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 24 Apr 2024 11:14:52 -0700 X-CSE-ConnectionGUID: B9T8sCJCTnK+A/+999me2Q== X-CSE-MsgGUID: 3qZu2DuTROGPe+WOfIcg6Q== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.07,226,1708416000"; d="scan'208";a="29262568" Received: from agluck-desk3.sc.intel.com ([172.25.222.105]) by fmviesa005-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 24 Apr 2024 11:14:51 -0700 From: Tony Luck To: Borislav Petkov , "Rafael J. Wysocki" , Viresh Kumar Cc: linux-pm@vger.kernel.org, linux-kernel@vger.kernel.org, patches@lists.linux.dev, Tony Luck , "Rafael J . Wysocki" Subject: [PATCH v4 08/71] cpufreq: Switch to new Intel CPU model defines Date: Wed, 24 Apr 2024 11:14:51 -0700 Message-ID: <20240424181451.41308-1-tony.luck@intel.com> X-Mailer: git-send-email 2.44.0 In-Reply-To: <20240424181245.41141-1-tony.luck@intel.com> References: <20240424181245.41141-1-tony.luck@intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" New CPU #defines encode vendor and family as well as model. Signed-off-by: Tony Luck Acked-by: Rafael J. Wysocki Acked-by: Hans de Goede --- drivers/cpufreq/speedstep-centrino.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/drivers/cpufreq/speedstep-centrino.c b/drivers/cpufreq/speedst= ep-centrino.c index 75b10ecdb60f..ddd6f53bfd2a 100644 --- a/drivers/cpufreq/speedstep-centrino.c +++ b/drivers/cpufreq/speedstep-centrino.c @@ -520,10 +520,10 @@ static struct cpufreq_driver centrino_driver =3D { * or ASCII model IDs. */ static const struct x86_cpu_id centrino_ids[] =3D { - X86_MATCH_VENDOR_FAM_MODEL_FEATURE(INTEL, 6, 9, X86_FEATURE_EST, NULL), - X86_MATCH_VENDOR_FAM_MODEL_FEATURE(INTEL, 6, 13, X86_FEATURE_EST, NULL), - X86_MATCH_VENDOR_FAM_MODEL_FEATURE(INTEL, 15, 3, X86_FEATURE_EST, NULL), - X86_MATCH_VENDOR_FAM_MODEL_FEATURE(INTEL, 15, 4, X86_FEATURE_EST, NULL), + X86_MATCH_VFM_FEATURE(IFM( 6, 9), X86_FEATURE_EST, NULL), + X86_MATCH_VFM_FEATURE(IFM( 6, 13), X86_FEATURE_EST, NULL), + X86_MATCH_VFM_FEATURE(IFM(15, 3), X86_FEATURE_EST, NULL), + X86_MATCH_VFM_FEATURE(IFM(15, 4), X86_FEATURE_EST, NULL), {} }; =20 --=20 2.44.0 From nobody Sat Jul 11 15:40:01 2026 Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.18]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 08B5316F26C; Wed, 24 Apr 2024 18:14:52 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=192.198.163.18 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1713982494; cv=none; b=kJ3ByCi04TkEQIA1Za75fmgZ7sp/PiqhT0uP+m8x6GQAHhb9XwGsK2nK2ivkfXRCL2JHQ7yIAGoE32j39gZMyLLXa0x1XV7uKxDpxn0hvz02ocogkmpxvT/4WQoifgiBs072+NepJoujkVbdJu+vjyYw49lQOBYmM3G98WNZkkk= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1713982494; c=relaxed/simple; bh=HtLk67VJXa/9h9uLwy5bh3ooxVgpgzTrHi5Ns3ks4fg=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=CHfNvI65hW/1HTdBlec1Roew9vzO8eo7UajvNo/rlWLUz9NzWGtd45pIODUdYYM/sMuvV0f+FdxvqVVLQZ3vGnyFXXAM97Mjy+aG0uJMHjQLscublKe+5YCIFQaoK10DY/ZNeyZszjjd5WwdoyKAxVUoyo5P9F/CFmscCO9Idbk= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com; spf=pass smtp.mailfrom=intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=k3RE2vTn; arc=none smtp.client-ip=192.198.163.18 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="k3RE2vTn" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1713982493; x=1745518493; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=HtLk67VJXa/9h9uLwy5bh3ooxVgpgzTrHi5Ns3ks4fg=; b=k3RE2vTnrV/6VJ0fzzbLvbeqEHI4nAvOEEoZ1B3nMUfIUHaSxBosyoOo pmLPhPIWenppcCDQIOZDtQQw5nDJ6IE5/9tihQxF1Ck2Y8GmuSc2vgeL6 qKpKcFyLaHGH3/LJhubeY897alF0gbGe0NjRLB8sP2/jPR3TresC235Il MGxj9n/yls7wfQyHw/575vEChhyGq8L1LlSxbEWGaMu7iE4R8SFhpvRCL 7SS7f+qiE2WpiZ2+ISnP7MBsMdbgABjogleb96bpcYCezvMyLIrw/qYmL ErK7AWi+3YbPw54gPnV+xEeSBj8JwElgY6cX78UWSToP1O7+CaPQoMlON A==; X-CSE-ConnectionGUID: uhpmMAIZRKS++p8DWz4bzw== X-CSE-MsgGUID: gCcaJBh+TjKRvpUHfJxBrA== X-IronPort-AV: E=McAfee;i="6600,9927,11054"; a="9481776" X-IronPort-AV: E=Sophos;i="6.07,226,1708416000"; d="scan'208";a="9481776" Received: from fmviesa005.fm.intel.com ([10.60.135.145]) by fmvoesa112.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 24 Apr 2024 11:14:52 -0700 X-CSE-ConnectionGUID: u0LB/dXXThevxvFn7MqEZw== X-CSE-MsgGUID: EpYMA1HBT5mKNcZakfW05w== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.07,226,1708416000"; d="scan'208";a="29262574" Received: from agluck-desk3.sc.intel.com ([172.25.222.105]) by fmviesa005-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 24 Apr 2024 11:14:52 -0700 From: Tony Luck To: Borislav Petkov , linux-kernel@vger.kernel.org Cc: Jacob Pan , Len Brown , linux-pm@vger.kernel.org, patches@lists.linux.dev, Tony Luck , "Rafael J . Wysocki" Subject: [PATCH v4 09/71] intel_idle: Switch to new Intel CPU model defines Date: Wed, 24 Apr 2024 11:14:51 -0700 Message-ID: <20240424181452.41327-1-tony.luck@intel.com> X-Mailer: git-send-email 2.44.0 In-Reply-To: <20240424181245.41141-1-tony.luck@intel.com> References: <20240424181245.41141-1-tony.luck@intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" New CPU #defines encode vendor and family as well as model. Signed-off-by: Tony Luck Acked-by: Rafael J. Wysocki Acked-by: Hans de Goede --- drivers/idle/intel_idle.c | 116 +++++++++++++++++++------------------- 1 file changed, 58 insertions(+), 58 deletions(-) diff --git a/drivers/idle/intel_idle.c b/drivers/idle/intel_idle.c index e486027f8b07..9aab7abc2ae9 100644 --- a/drivers/idle/intel_idle.c +++ b/drivers/idle/intel_idle.c @@ -1494,53 +1494,53 @@ static const struct idle_cpu idle_cpu_srf __initcon= st =3D { }; =20 static const struct x86_cpu_id intel_idle_ids[] __initconst =3D { - X86_MATCH_INTEL_FAM6_MODEL(NEHALEM_EP, &idle_cpu_nhx), - X86_MATCH_INTEL_FAM6_MODEL(NEHALEM, &idle_cpu_nehalem), - X86_MATCH_INTEL_FAM6_MODEL(NEHALEM_G, &idle_cpu_nehalem), - X86_MATCH_INTEL_FAM6_MODEL(WESTMERE, &idle_cpu_nehalem), - X86_MATCH_INTEL_FAM6_MODEL(WESTMERE_EP, &idle_cpu_nhx), - X86_MATCH_INTEL_FAM6_MODEL(NEHALEM_EX, &idle_cpu_nhx), - X86_MATCH_INTEL_FAM6_MODEL(ATOM_BONNELL, &idle_cpu_atom), - X86_MATCH_INTEL_FAM6_MODEL(ATOM_BONNELL_MID, &idle_cpu_lincroft), - X86_MATCH_INTEL_FAM6_MODEL(WESTMERE_EX, &idle_cpu_nhx), - X86_MATCH_INTEL_FAM6_MODEL(SANDYBRIDGE, &idle_cpu_snb), - X86_MATCH_INTEL_FAM6_MODEL(SANDYBRIDGE_X, &idle_cpu_snx), - X86_MATCH_INTEL_FAM6_MODEL(ATOM_SALTWELL, &idle_cpu_atom), - X86_MATCH_INTEL_FAM6_MODEL(ATOM_SILVERMONT, &idle_cpu_byt), - X86_MATCH_INTEL_FAM6_MODEL(ATOM_SILVERMONT_MID, &idle_cpu_tangier), - X86_MATCH_INTEL_FAM6_MODEL(ATOM_AIRMONT, &idle_cpu_cht), - X86_MATCH_INTEL_FAM6_MODEL(IVYBRIDGE, &idle_cpu_ivb), - X86_MATCH_INTEL_FAM6_MODEL(IVYBRIDGE_X, &idle_cpu_ivt), - X86_MATCH_INTEL_FAM6_MODEL(HASWELL, &idle_cpu_hsw), - X86_MATCH_INTEL_FAM6_MODEL(HASWELL_X, &idle_cpu_hsx), - X86_MATCH_INTEL_FAM6_MODEL(HASWELL_L, &idle_cpu_hsw), - X86_MATCH_INTEL_FAM6_MODEL(HASWELL_G, &idle_cpu_hsw), - X86_MATCH_INTEL_FAM6_MODEL(ATOM_SILVERMONT_D, &idle_cpu_avn), - X86_MATCH_INTEL_FAM6_MODEL(BROADWELL, &idle_cpu_bdw), - X86_MATCH_INTEL_FAM6_MODEL(BROADWELL_G, &idle_cpu_bdw), - X86_MATCH_INTEL_FAM6_MODEL(BROADWELL_X, &idle_cpu_bdx), - X86_MATCH_INTEL_FAM6_MODEL(BROADWELL_D, &idle_cpu_bdx), - X86_MATCH_INTEL_FAM6_MODEL(SKYLAKE_L, &idle_cpu_skl), - X86_MATCH_INTEL_FAM6_MODEL(SKYLAKE, &idle_cpu_skl), - X86_MATCH_INTEL_FAM6_MODEL(KABYLAKE_L, &idle_cpu_skl), - X86_MATCH_INTEL_FAM6_MODEL(KABYLAKE, &idle_cpu_skl), - X86_MATCH_INTEL_FAM6_MODEL(SKYLAKE_X, &idle_cpu_skx), - X86_MATCH_INTEL_FAM6_MODEL(ICELAKE_X, &idle_cpu_icx), - X86_MATCH_INTEL_FAM6_MODEL(ICELAKE_D, &idle_cpu_icx), - X86_MATCH_INTEL_FAM6_MODEL(ALDERLAKE, &idle_cpu_adl), - X86_MATCH_INTEL_FAM6_MODEL(ALDERLAKE_L, &idle_cpu_adl_l), - X86_MATCH_INTEL_FAM6_MODEL(METEORLAKE_L, &idle_cpu_mtl_l), - X86_MATCH_INTEL_FAM6_MODEL(ATOM_GRACEMONT, &idle_cpu_gmt), - X86_MATCH_INTEL_FAM6_MODEL(SAPPHIRERAPIDS_X, &idle_cpu_spr), - X86_MATCH_INTEL_FAM6_MODEL(EMERALDRAPIDS_X, &idle_cpu_spr), - X86_MATCH_INTEL_FAM6_MODEL(XEON_PHI_KNL, &idle_cpu_knl), - X86_MATCH_INTEL_FAM6_MODEL(XEON_PHI_KNM, &idle_cpu_knl), - X86_MATCH_INTEL_FAM6_MODEL(ATOM_GOLDMONT, &idle_cpu_bxt), - X86_MATCH_INTEL_FAM6_MODEL(ATOM_GOLDMONT_PLUS, &idle_cpu_bxt), - X86_MATCH_INTEL_FAM6_MODEL(ATOM_GOLDMONT_D, &idle_cpu_dnv), - X86_MATCH_INTEL_FAM6_MODEL(ATOM_TREMONT_D, &idle_cpu_snr), - X86_MATCH_INTEL_FAM6_MODEL(ATOM_CRESTMONT, &idle_cpu_grr), - X86_MATCH_INTEL_FAM6_MODEL(ATOM_CRESTMONT_X, &idle_cpu_srf), + X86_MATCH_VFM(INTEL_NEHALEM_EP, &idle_cpu_nhx), + X86_MATCH_VFM(INTEL_NEHALEM, &idle_cpu_nehalem), + X86_MATCH_VFM(INTEL_NEHALEM_G, &idle_cpu_nehalem), + X86_MATCH_VFM(INTEL_WESTMERE, &idle_cpu_nehalem), + X86_MATCH_VFM(INTEL_WESTMERE_EP, &idle_cpu_nhx), + X86_MATCH_VFM(INTEL_NEHALEM_EX, &idle_cpu_nhx), + X86_MATCH_VFM(INTEL_ATOM_BONNELL, &idle_cpu_atom), + X86_MATCH_VFM(INTEL_ATOM_BONNELL_MID, &idle_cpu_lincroft), + X86_MATCH_VFM(INTEL_WESTMERE_EX, &idle_cpu_nhx), + X86_MATCH_VFM(INTEL_SANDYBRIDGE, &idle_cpu_snb), + X86_MATCH_VFM(INTEL_SANDYBRIDGE_X, &idle_cpu_snx), + X86_MATCH_VFM(INTEL_ATOM_SALTWELL, &idle_cpu_atom), + X86_MATCH_VFM(INTEL_ATOM_SILVERMONT, &idle_cpu_byt), + X86_MATCH_VFM(INTEL_ATOM_SILVERMONT_MID, &idle_cpu_tangier), + X86_MATCH_VFM(INTEL_ATOM_AIRMONT, &idle_cpu_cht), + X86_MATCH_VFM(INTEL_IVYBRIDGE, &idle_cpu_ivb), + X86_MATCH_VFM(INTEL_IVYBRIDGE_X, &idle_cpu_ivt), + X86_MATCH_VFM(INTEL_HASWELL, &idle_cpu_hsw), + X86_MATCH_VFM(INTEL_HASWELL_X, &idle_cpu_hsx), + X86_MATCH_VFM(INTEL_HASWELL_L, &idle_cpu_hsw), + X86_MATCH_VFM(INTEL_HASWELL_G, &idle_cpu_hsw), + X86_MATCH_VFM(INTEL_ATOM_SILVERMONT_D, &idle_cpu_avn), + X86_MATCH_VFM(INTEL_BROADWELL, &idle_cpu_bdw), + X86_MATCH_VFM(INTEL_BROADWELL_G, &idle_cpu_bdw), + X86_MATCH_VFM(INTEL_BROADWELL_X, &idle_cpu_bdx), + X86_MATCH_VFM(INTEL_BROADWELL_D, &idle_cpu_bdx), + X86_MATCH_VFM(INTEL_SKYLAKE_L, &idle_cpu_skl), + X86_MATCH_VFM(INTEL_SKYLAKE, &idle_cpu_skl), + X86_MATCH_VFM(INTEL_KABYLAKE_L, &idle_cpu_skl), + X86_MATCH_VFM(INTEL_KABYLAKE, &idle_cpu_skl), + X86_MATCH_VFM(INTEL_SKYLAKE_X, &idle_cpu_skx), + X86_MATCH_VFM(INTEL_ICELAKE_X, &idle_cpu_icx), + X86_MATCH_VFM(INTEL_ICELAKE_D, &idle_cpu_icx), + X86_MATCH_VFM(INTEL_ALDERLAKE, &idle_cpu_adl), + X86_MATCH_VFM(INTEL_ALDERLAKE_L, &idle_cpu_adl_l), + X86_MATCH_VFM(INTEL_METEORLAKE_L, &idle_cpu_mtl_l), + X86_MATCH_VFM(INTEL_ATOM_GRACEMONT, &idle_cpu_gmt), + X86_MATCH_VFM(INTEL_SAPPHIRERAPIDS_X, &idle_cpu_spr), + X86_MATCH_VFM(INTEL_EMERALDRAPIDS_X, &idle_cpu_spr), + X86_MATCH_VFM(INTEL_XEON_PHI_KNL, &idle_cpu_knl), + X86_MATCH_VFM(INTEL_XEON_PHI_KNM, &idle_cpu_knl), + X86_MATCH_VFM(INTEL_ATOM_GOLDMONT, &idle_cpu_bxt), + X86_MATCH_VFM(INTEL_ATOM_GOLDMONT_PLUS, &idle_cpu_bxt), + X86_MATCH_VFM(INTEL_ATOM_GOLDMONT_D, &idle_cpu_dnv), + X86_MATCH_VFM(INTEL_ATOM_TREMONT_D, &idle_cpu_snr), + X86_MATCH_VFM(INTEL_ATOM_CRESTMONT, &idle_cpu_grr), + X86_MATCH_VFM(INTEL_ATOM_CRESTMONT_X, &idle_cpu_srf), {} }; =20 @@ -1990,27 +1990,27 @@ static void __init intel_idle_init_cstates_icpu(str= uct cpuidle_driver *drv) { int cstate; =20 - switch (boot_cpu_data.x86_model) { - case INTEL_FAM6_IVYBRIDGE_X: + switch (boot_cpu_data.x86_vfm) { + case INTEL_IVYBRIDGE_X: ivt_idle_state_table_update(); break; - case INTEL_FAM6_ATOM_GOLDMONT: - case INTEL_FAM6_ATOM_GOLDMONT_PLUS: + case INTEL_ATOM_GOLDMONT: + case INTEL_ATOM_GOLDMONT_PLUS: bxt_idle_state_table_update(); break; - case INTEL_FAM6_SKYLAKE: + case INTEL_SKYLAKE: sklh_idle_state_table_update(); break; - case INTEL_FAM6_SKYLAKE_X: + case INTEL_SKYLAKE_X: skx_idle_state_table_update(); break; - case INTEL_FAM6_SAPPHIRERAPIDS_X: - case INTEL_FAM6_EMERALDRAPIDS_X: + case INTEL_SAPPHIRERAPIDS_X: + case INTEL_EMERALDRAPIDS_X: spr_idle_state_table_update(); break; - case INTEL_FAM6_ALDERLAKE: - case INTEL_FAM6_ALDERLAKE_L: - case INTEL_FAM6_ATOM_GRACEMONT: + case INTEL_ALDERLAKE: + case INTEL_ALDERLAKE_L: + case INTEL_ATOM_GRACEMONT: adl_idle_state_table_update(); break; } --=20 2.44.0 From nobody Sat Jul 11 15:40:01 2026 Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.18]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 6435916DEBA; Wed, 24 Apr 2024 18:15:08 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=192.198.163.18 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1713982509; cv=none; b=KfvzPBkFNAszVnpD4SHdUHLOH/Q+rj0HOP5jRreGpDTeU3umeQWJor3ASs1jpKfvwjcvCNZAczoLqXy7jNbd8BT+GPHVa0jo1BgN15WUlks5QmyY0E+jlJega1fHuuYXSoYphpo/iRkuNpFtkOEms7mIuY0xJrqwwvx03zaFnag= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1713982509; c=relaxed/simple; bh=Bj1Hh9P4phH3tXz7fAUpe9Zp5qNwRqIfye9t/fF1o6k=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=QGfhcC1RONOVtdatiQUzD45fjQu8YJvkja35MRoabVgUfsHLFDl6dF72DDl5J5u8jINvKfJWBIWKjV9afC6Wp5p4Yvv6cje/gFE7fviZsP8EAIUFZFFctlsCiM1ZwJhTAGpS7us+NPkpfRBYYYNiO7VLCFoPTarft0jmtNQLy3w= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com; spf=pass smtp.mailfrom=intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=V/IL/Mrj; arc=none smtp.client-ip=192.198.163.18 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="V/IL/Mrj" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1713982508; x=1745518508; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=Bj1Hh9P4phH3tXz7fAUpe9Zp5qNwRqIfye9t/fF1o6k=; b=V/IL/MrjOPZ6oaUPfKhcmtLQQdUdtCftRB+MBmtvDZ6T7jc+dK0/1VbS 9VYUUXIP9kv3rUsm+sI/sExcnMizUI/TXBJoYOtvFwhCnEZ2hBjtJnyJw 76VdveesYbkM/J8IXEsDJSMXmEy3lKRuVLXWxGqkHFcM3pkHY6Bqlr3Q4 1qTrX9ewNpxgSseJElFveX/vrz2FVs7Vhg6LsMCI6Xh/2GcI9miIjLS2y vKMbY5lepmIaUW+ydoj8RB9GfvA4dqgZ4piLrwAuIt1XvZPVVdHIyo23+ 74j5djVDw7z7kMtfXuP4op1i4bVW0/V47iHLA5ojLPHjV01NaXTOWDEpw g==; X-CSE-ConnectionGUID: KUKVJKFcSlmf/lqx0pvAPg== X-CSE-MsgGUID: AaVHfvdlR0G7GlvnIML5kQ== X-IronPort-AV: E=McAfee;i="6600,9927,11054"; a="9481784" X-IronPort-AV: E=Sophos;i="6.07,226,1708416000"; d="scan'208";a="9481784" Received: from fmviesa005.fm.intel.com ([10.60.135.145]) by fmvoesa112.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 24 Apr 2024 11:14:53 -0700 X-CSE-ConnectionGUID: g9KL3PctSRGzgFMrYZHuPQ== X-CSE-MsgGUID: 3ViPB0/LTzGJ4dCuXhhMOw== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.07,226,1708416000"; d="scan'208";a="29262578" Received: from agluck-desk3.sc.intel.com ([172.25.222.105]) by fmviesa005-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 24 Apr 2024 11:14:53 -0700 From: Tony Luck To: Borislav Petkov , linux-kernel@vger.kernel.org Cc: Bjorn Helgaas , linux-pci@vger.kernel.org, patches@lists.linux.dev, Tony Luck Subject: [PATCH v4 10/71] PCI: PM: Switch to new Intel CPU model defines Date: Wed, 24 Apr 2024 11:14:52 -0700 Message-ID: <20240424181452.41346-1-tony.luck@intel.com> X-Mailer: git-send-email 2.44.0 In-Reply-To: <20240424181245.41141-1-tony.luck@intel.com> References: <20240424181245.41141-1-tony.luck@intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" New CPU #defines encode vendor and family as well as model. Signed-off-by: Tony Luck Acked-by: Bjorn Helgaas Acked-by: Hans de Goede --- drivers/pci/pci-mid.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/pci/pci-mid.c b/drivers/pci/pci-mid.c index fbfd78127123..bed9f0755271 100644 --- a/drivers/pci/pci-mid.c +++ b/drivers/pci/pci-mid.c @@ -38,8 +38,8 @@ pci_power_t mid_pci_get_power_state(struct pci_dev *pdev) * arch/x86/platform/intel-mid/pwr.c. */ static const struct x86_cpu_id lpss_cpu_ids[] =3D { - X86_MATCH_INTEL_FAM6_MODEL(ATOM_SALTWELL_MID, NULL), - X86_MATCH_INTEL_FAM6_MODEL(ATOM_SILVERMONT_MID, NULL), + X86_MATCH_VFM(INTEL_ATOM_SALTWELL_MID, NULL), + X86_MATCH_VFM(INTEL_ATOM_SILVERMONT_MID, NULL), {} }; =20 --=20 2.44.0 From nobody Sat Jul 11 15:40:01 2026 Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.18]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 9634416DEA8; Wed, 24 Apr 2024 18:15:06 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=192.198.163.18 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1713982508; cv=none; b=tYTact90QnPnM/L6gjkuJvyWrxtKJZv84Nh70lpnkIPaXXgmWbzz2v1njvo0+Kdra0pda+ByZcxH9Fe0Dh+FDFiMRjpL0/fy2KXoGCuj1zQ1eoWC0pBojZT0vtMMTV/ANS3qOLfgR8DKaI+t8CowVXYm7gbokz6F3NJquzlEffk= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1713982508; c=relaxed/simple; bh=nsRNTDx4whD1GLA/xKi0WFK0CbOb/U+ApM/A8sRWWZE=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=ZUdFqcy7aAbKc1D7uH4nUDhxlI1fvE9ouLU3e6Iq9zAIQMGbdrAXKx5bYh75JWjokquQlAN5zvc2+EaARvKHgBzAH50b19DVDIKr64WZVkw44KLDrEHzqes0ZyOokBH7YTDpUMjMVBwYyIZnNHRoBfIPZeFLcOf0WktK78BZJdk= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com; spf=pass smtp.mailfrom=intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=f3LGmM9O; arc=none smtp.client-ip=192.198.163.18 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="f3LGmM9O" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1713982506; x=1745518506; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=nsRNTDx4whD1GLA/xKi0WFK0CbOb/U+ApM/A8sRWWZE=; b=f3LGmM9OPDVxL78trwzGKnVQ9ZEblt+2VeVenpuiKN10zlHk1HY41akX pJmd/dK9NzGt9yCUQx+v2PViqHTD/a9hYPvGMrSjRkXtFw7KOdHxIzWPt Hgb8DprM202s5n1/XUhWrjfO9FJVmvaDnUD7pvA/BAkKrf4cu1taza3Vo 6lS3OH+CP5C7ZGG2m4V1xcOrjE2JpY9je1srsOxeUsZ1hmw7VrdojYaFt PmKBNhPPT+kwjUcM3C45CQf1ouYrel0E27Tpg5ryxm2jxe+MrRUlfJNfq UQ4gWoqE1guQdBxsxQET7FrOB1vRvhyd7hdrVWviA9PYDZZpcF72GZxvO Q==; X-CSE-ConnectionGUID: G7FGiSvbRByksNCtJvwiDw== X-CSE-MsgGUID: gwl9scnYStOn9pBnfpwH4Q== X-IronPort-AV: E=McAfee;i="6600,9927,11054"; a="9481791" X-IronPort-AV: E=Sophos;i="6.07,226,1708416000"; d="scan'208";a="9481791" Received: from fmviesa005.fm.intel.com ([10.60.135.145]) by fmvoesa112.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 24 Apr 2024 11:14:53 -0700 X-CSE-ConnectionGUID: Z+wCELX9QtK75WRHy1XQpQ== X-CSE-MsgGUID: MwxAPzXUSpuAVtimSkBizA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.07,226,1708416000"; d="scan'208";a="29262587" Received: from agluck-desk3.sc.intel.com ([172.25.222.105]) by fmviesa005-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 24 Apr 2024 11:14:53 -0700 From: Tony Luck To: Borislav Petkov , linux-kernel@vger.kernel.org Cc: "Rafael J. Wysocki" , linux-pm@vger.kernel.org, patches@lists.linux.dev, Tony Luck , "Rafael J . Wysocki" Subject: [PATCH v4 11/71] powercap: intel_rapl: Switch to new Intel CPU model defines Date: Wed, 24 Apr 2024 11:14:53 -0700 Message-ID: <20240424181453.41365-1-tony.luck@intel.com> X-Mailer: git-send-email 2.44.0 In-Reply-To: <20240424181245.41141-1-tony.luck@intel.com> References: <20240424181245.41141-1-tony.luck@intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" New CPU #defines encode vendor and family as well as model. Signed-off-by: Tony Luck Acked-by: Rafael J. Wysocki Acked-by: Hans de Goede --- drivers/powercap/intel_rapl_common.c | 118 +++++++++++++-------------- 1 file changed, 59 insertions(+), 59 deletions(-) diff --git a/drivers/powercap/intel_rapl_common.c b/drivers/powercap/intel_= rapl_common.c index a28d54fd5222..59c36ea55712 100644 --- a/drivers/powercap/intel_rapl_common.c +++ b/drivers/powercap/intel_rapl_common.c @@ -1220,65 +1220,65 @@ static const struct rapl_defaults rapl_defaults_amd= =3D { }; =20 static const struct x86_cpu_id rapl_ids[] __initconst =3D { - X86_MATCH_INTEL_FAM6_MODEL(SANDYBRIDGE, &rapl_defaults_core), - X86_MATCH_INTEL_FAM6_MODEL(SANDYBRIDGE_X, &rapl_defaults_core), - - X86_MATCH_INTEL_FAM6_MODEL(IVYBRIDGE, &rapl_defaults_core), - X86_MATCH_INTEL_FAM6_MODEL(IVYBRIDGE_X, &rapl_defaults_core), - - X86_MATCH_INTEL_FAM6_MODEL(HASWELL, &rapl_defaults_core), - X86_MATCH_INTEL_FAM6_MODEL(HASWELL_L, &rapl_defaults_core), - X86_MATCH_INTEL_FAM6_MODEL(HASWELL_G, &rapl_defaults_core), - X86_MATCH_INTEL_FAM6_MODEL(HASWELL_X, &rapl_defaults_hsw_server), - - X86_MATCH_INTEL_FAM6_MODEL(BROADWELL, &rapl_defaults_core), - X86_MATCH_INTEL_FAM6_MODEL(BROADWELL_G, &rapl_defaults_core), - X86_MATCH_INTEL_FAM6_MODEL(BROADWELL_D, &rapl_defaults_core), - X86_MATCH_INTEL_FAM6_MODEL(BROADWELL_X, &rapl_defaults_hsw_server), - - X86_MATCH_INTEL_FAM6_MODEL(SKYLAKE, &rapl_defaults_core), - X86_MATCH_INTEL_FAM6_MODEL(SKYLAKE_L, &rapl_defaults_core), - X86_MATCH_INTEL_FAM6_MODEL(SKYLAKE_X, &rapl_defaults_hsw_server), - X86_MATCH_INTEL_FAM6_MODEL(KABYLAKE_L, &rapl_defaults_core), - X86_MATCH_INTEL_FAM6_MODEL(KABYLAKE, &rapl_defaults_core), - X86_MATCH_INTEL_FAM6_MODEL(CANNONLAKE_L, &rapl_defaults_core), - X86_MATCH_INTEL_FAM6_MODEL(ICELAKE_L, &rapl_defaults_core), - X86_MATCH_INTEL_FAM6_MODEL(ICELAKE, &rapl_defaults_core), - X86_MATCH_INTEL_FAM6_MODEL(ICELAKE_NNPI, &rapl_defaults_core), - X86_MATCH_INTEL_FAM6_MODEL(ICELAKE_X, &rapl_defaults_hsw_server), - X86_MATCH_INTEL_FAM6_MODEL(ICELAKE_D, &rapl_defaults_hsw_server), - X86_MATCH_INTEL_FAM6_MODEL(COMETLAKE_L, &rapl_defaults_core), - X86_MATCH_INTEL_FAM6_MODEL(COMETLAKE, &rapl_defaults_core), - X86_MATCH_INTEL_FAM6_MODEL(TIGERLAKE_L, &rapl_defaults_core), - X86_MATCH_INTEL_FAM6_MODEL(TIGERLAKE, &rapl_defaults_core), - X86_MATCH_INTEL_FAM6_MODEL(ROCKETLAKE, &rapl_defaults_core), - X86_MATCH_INTEL_FAM6_MODEL(ALDERLAKE, &rapl_defaults_core), - X86_MATCH_INTEL_FAM6_MODEL(ALDERLAKE_L, &rapl_defaults_core), - X86_MATCH_INTEL_FAM6_MODEL(ATOM_GRACEMONT, &rapl_defaults_core), - X86_MATCH_INTEL_FAM6_MODEL(RAPTORLAKE, &rapl_defaults_core), - X86_MATCH_INTEL_FAM6_MODEL(RAPTORLAKE_P, &rapl_defaults_core), - X86_MATCH_INTEL_FAM6_MODEL(RAPTORLAKE_S, &rapl_defaults_core), - X86_MATCH_INTEL_FAM6_MODEL(METEORLAKE, &rapl_defaults_core), - X86_MATCH_INTEL_FAM6_MODEL(METEORLAKE_L, &rapl_defaults_core), - X86_MATCH_INTEL_FAM6_MODEL(SAPPHIRERAPIDS_X, &rapl_defaults_spr_server), - X86_MATCH_INTEL_FAM6_MODEL(EMERALDRAPIDS_X, &rapl_defaults_spr_server), - X86_MATCH_INTEL_FAM6_MODEL(LUNARLAKE_M, &rapl_defaults_core), - X86_MATCH_INTEL_FAM6_MODEL(ARROWLAKE, &rapl_defaults_core), - X86_MATCH_INTEL_FAM6_MODEL(LAKEFIELD, &rapl_defaults_core), - - X86_MATCH_INTEL_FAM6_MODEL(ATOM_SILVERMONT, &rapl_defaults_byt), - X86_MATCH_INTEL_FAM6_MODEL(ATOM_AIRMONT, &rapl_defaults_cht), - X86_MATCH_INTEL_FAM6_MODEL(ATOM_SILVERMONT_MID, &rapl_defaults_tng), - X86_MATCH_INTEL_FAM6_MODEL(ATOM_AIRMONT_MID, &rapl_defaults_ann), - X86_MATCH_INTEL_FAM6_MODEL(ATOM_GOLDMONT, &rapl_defaults_core), - X86_MATCH_INTEL_FAM6_MODEL(ATOM_GOLDMONT_PLUS, &rapl_defaults_core), - X86_MATCH_INTEL_FAM6_MODEL(ATOM_GOLDMONT_D, &rapl_defaults_core), - X86_MATCH_INTEL_FAM6_MODEL(ATOM_TREMONT, &rapl_defaults_core), - X86_MATCH_INTEL_FAM6_MODEL(ATOM_TREMONT_D, &rapl_defaults_core), - X86_MATCH_INTEL_FAM6_MODEL(ATOM_TREMONT_L, &rapl_defaults_core), - - X86_MATCH_INTEL_FAM6_MODEL(XEON_PHI_KNL, &rapl_defaults_hsw_server), - X86_MATCH_INTEL_FAM6_MODEL(XEON_PHI_KNM, &rapl_defaults_hsw_server), + X86_MATCH_VFM(INTEL_SANDYBRIDGE, &rapl_defaults_core), + X86_MATCH_VFM(INTEL_SANDYBRIDGE_X, &rapl_defaults_core), + + X86_MATCH_VFM(INTEL_IVYBRIDGE, &rapl_defaults_core), + X86_MATCH_VFM(INTEL_IVYBRIDGE_X, &rapl_defaults_core), + + X86_MATCH_VFM(INTEL_HASWELL, &rapl_defaults_core), + X86_MATCH_VFM(INTEL_HASWELL_L, &rapl_defaults_core), + X86_MATCH_VFM(INTEL_HASWELL_G, &rapl_defaults_core), + X86_MATCH_VFM(INTEL_HASWELL_X, &rapl_defaults_hsw_server), + + X86_MATCH_VFM(INTEL_BROADWELL, &rapl_defaults_core), + X86_MATCH_VFM(INTEL_BROADWELL_G, &rapl_defaults_core), + X86_MATCH_VFM(INTEL_BROADWELL_D, &rapl_defaults_core), + X86_MATCH_VFM(INTEL_BROADWELL_X, &rapl_defaults_hsw_server), + + X86_MATCH_VFM(INTEL_SKYLAKE, &rapl_defaults_core), + X86_MATCH_VFM(INTEL_SKYLAKE_L, &rapl_defaults_core), + X86_MATCH_VFM(INTEL_SKYLAKE_X, &rapl_defaults_hsw_server), + X86_MATCH_VFM(INTEL_KABYLAKE_L, &rapl_defaults_core), + X86_MATCH_VFM(INTEL_KABYLAKE, &rapl_defaults_core), + X86_MATCH_VFM(INTEL_CANNONLAKE_L, &rapl_defaults_core), + X86_MATCH_VFM(INTEL_ICELAKE_L, &rapl_defaults_core), + X86_MATCH_VFM(INTEL_ICELAKE, &rapl_defaults_core), + X86_MATCH_VFM(INTEL_ICELAKE_NNPI, &rapl_defaults_core), + X86_MATCH_VFM(INTEL_ICELAKE_X, &rapl_defaults_hsw_server), + X86_MATCH_VFM(INTEL_ICELAKE_D, &rapl_defaults_hsw_server), + X86_MATCH_VFM(INTEL_COMETLAKE_L, &rapl_defaults_core), + X86_MATCH_VFM(INTEL_COMETLAKE, &rapl_defaults_core), + X86_MATCH_VFM(INTEL_TIGERLAKE_L, &rapl_defaults_core), + X86_MATCH_VFM(INTEL_TIGERLAKE, &rapl_defaults_core), + X86_MATCH_VFM(INTEL_ROCKETLAKE, &rapl_defaults_core), + X86_MATCH_VFM(INTEL_ALDERLAKE, &rapl_defaults_core), + X86_MATCH_VFM(INTEL_ALDERLAKE_L, &rapl_defaults_core), + X86_MATCH_VFM(INTEL_ATOM_GRACEMONT, &rapl_defaults_core), + X86_MATCH_VFM(INTEL_RAPTORLAKE, &rapl_defaults_core), + X86_MATCH_VFM(INTEL_RAPTORLAKE_P, &rapl_defaults_core), + X86_MATCH_VFM(INTEL_RAPTORLAKE_S, &rapl_defaults_core), + X86_MATCH_VFM(INTEL_METEORLAKE, &rapl_defaults_core), + X86_MATCH_VFM(INTEL_METEORLAKE_L, &rapl_defaults_core), + X86_MATCH_VFM(INTEL_SAPPHIRERAPIDS_X, &rapl_defaults_spr_server), + X86_MATCH_VFM(INTEL_EMERALDRAPIDS_X, &rapl_defaults_spr_server), + X86_MATCH_VFM(INTEL_LUNARLAKE_M, &rapl_defaults_core), + X86_MATCH_VFM(INTEL_ARROWLAKE, &rapl_defaults_core), + X86_MATCH_VFM(INTEL_LAKEFIELD, &rapl_defaults_core), + + X86_MATCH_VFM(INTEL_ATOM_SILVERMONT, &rapl_defaults_byt), + X86_MATCH_VFM(INTEL_ATOM_AIRMONT, &rapl_defaults_cht), + X86_MATCH_VFM(INTEL_ATOM_SILVERMONT_MID, &rapl_defaults_tng), + X86_MATCH_VFM(INTEL_ATOM_AIRMONT_MID, &rapl_defaults_ann), + X86_MATCH_VFM(INTEL_ATOM_GOLDMONT, &rapl_defaults_core), + X86_MATCH_VFM(INTEL_ATOM_GOLDMONT_PLUS, &rapl_defaults_core), + X86_MATCH_VFM(INTEL_ATOM_GOLDMONT_D, &rapl_defaults_core), + X86_MATCH_VFM(INTEL_ATOM_TREMONT, &rapl_defaults_core), + X86_MATCH_VFM(INTEL_ATOM_TREMONT_D, &rapl_defaults_core), + X86_MATCH_VFM(INTEL_ATOM_TREMONT_L, &rapl_defaults_core), + + X86_MATCH_VFM(INTEL_XEON_PHI_KNL, &rapl_defaults_hsw_server), + X86_MATCH_VFM(INTEL_XEON_PHI_KNM, &rapl_defaults_hsw_server), =20 X86_MATCH_VENDOR_FAM(AMD, 0x17, &rapl_defaults_amd), X86_MATCH_VENDOR_FAM(AMD, 0x19, &rapl_defaults_amd), --=20 2.44.0 From nobody Sat Jul 11 15:40:01 2026 Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.18]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A042116DEAC; Wed, 24 Apr 2024 18:15:07 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=192.198.163.18 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1713982510; cv=none; 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E=Sophos;i="6.07,226,1708416000"; d="scan'208";a="9481797" Received: from fmviesa005.fm.intel.com ([10.60.135.145]) by fmvoesa112.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 24 Apr 2024 11:14:54 -0700 X-CSE-ConnectionGUID: wIyDnPmwTt2Z7zyczF/3LQ== X-CSE-MsgGUID: OvHxs7oUSmyRwoiBU4H5Yg== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.07,226,1708416000"; d="scan'208";a="29262591" Received: from agluck-desk3.sc.intel.com ([172.25.222.105]) by fmviesa005-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 24 Apr 2024 11:14:54 -0700 From: Tony Luck To: Borislav Petkov , linux-kernel@vger.kernel.org Cc: "Rafael J. Wysocki" , linux-pm@vger.kernel.org, patches@lists.linux.dev, Tony Luck , "Rafael J . Wysocki" Subject: [PATCH v4 12/71] powercap: intel_rapl: Switch to new Intel CPU model defines Date: Wed, 24 Apr 2024 11:14:53 -0700 Message-ID: <20240424181453.41384-1-tony.luck@intel.com> X-Mailer: git-send-email 2.44.0 In-Reply-To: <20240424181245.41141-1-tony.luck@intel.com> References: <20240424181245.41141-1-tony.luck@intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" New CPU #defines encode vendor and family as well as model. Signed-off-by: Tony Luck Acked-by: Rafael J. Wysocki Acked-by: Hans de Goede --- drivers/powercap/intel_rapl_msr.c | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) diff --git a/drivers/powercap/intel_rapl_msr.c b/drivers/powercap/intel_rap= l_msr.c index 35cb152fa9aa..733a36f67fbc 100644 --- a/drivers/powercap/intel_rapl_msr.c +++ b/drivers/powercap/intel_rapl_msr.c @@ -139,14 +139,14 @@ static int rapl_msr_write_raw(int cpu, struct reg_act= ion *ra) =20 /* List of verified CPUs. */ static const struct x86_cpu_id pl4_support_ids[] =3D { - X86_MATCH_INTEL_FAM6_MODEL(TIGERLAKE_L, NULL), - X86_MATCH_INTEL_FAM6_MODEL(ALDERLAKE, NULL), - X86_MATCH_INTEL_FAM6_MODEL(ALDERLAKE_L, NULL), - X86_MATCH_INTEL_FAM6_MODEL(ATOM_GRACEMONT, NULL), - X86_MATCH_INTEL_FAM6_MODEL(RAPTORLAKE, NULL), - X86_MATCH_INTEL_FAM6_MODEL(RAPTORLAKE_P, NULL), - X86_MATCH_INTEL_FAM6_MODEL(METEORLAKE, NULL), - X86_MATCH_INTEL_FAM6_MODEL(METEORLAKE_L, NULL), + X86_MATCH_VFM(INTEL_TIGERLAKE_L, NULL), + X86_MATCH_VFM(INTEL_ALDERLAKE, NULL), + X86_MATCH_VFM(INTEL_ALDERLAKE_L, NULL), + X86_MATCH_VFM(INTEL_ATOM_GRACEMONT, NULL), + X86_MATCH_VFM(INTEL_RAPTORLAKE, NULL), + X86_MATCH_VFM(INTEL_RAPTORLAKE_P, NULL), + X86_MATCH_VFM(INTEL_METEORLAKE, NULL), + X86_MATCH_VFM(INTEL_METEORLAKE_L, NULL), {} }; =20 --=20 2.44.0 From nobody Sat Jul 11 15:40:01 2026 Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.18]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id ADC2E16DEC5; Wed, 24 Apr 2024 18:15:08 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=192.198.163.18 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1713982510; cv=none; b=CZ470SctNwhAKaQfLQ6EtEKfhV1N2XeSXPc5nLY5KGhemX5hdzN8h4DOeY7XvPkBXRL5MMLee9ZOX5YO4ql5OE37V3zfgzd0XlwGhCksOhx06jy3HBQp3OfxxD5ZVLhv2zCTXLwObTHyr2EFxi4AqGoYS71NSqypf32zEWyJ5yA= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1713982510; c=relaxed/simple; bh=7eZ3KCFeL78AbH6r5Dbnh9EHFylKrjKmvHvWxMZrAck=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=uABz70W54W/E29vWr3SIva6icevlCESLEd3ZVBFW4JQxRgRmH13qHVCYBP+Ng5fTQsc/tnT2g1sniisa0zcWeVtOcj0FDWik1pFJY+4wX42e/w4NG8r764vLM65lXjehXiYBxX9eZIrGDxMwnyFNCTZh15TcVb2seFE4ZCLhsWI= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com; spf=pass smtp.mailfrom=intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=CezJ7gAS; arc=none smtp.client-ip=192.198.163.18 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="CezJ7gAS" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1713982508; x=1745518508; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=7eZ3KCFeL78AbH6r5Dbnh9EHFylKrjKmvHvWxMZrAck=; b=CezJ7gASKigrsvMgxSgGDhIyGE19axf/iT0ijVUAry/n6C6civ3blzti DvKnTkAsdzZZs1CNnCzE1qnk3cJdeunEq8TJwBLw9NoE1BvB1+lK+fF/B kSaUVHWmVGPYefNSvkzC/5A0rboCd5vo7DGODGN/WV4AUS+bs+UiW4PNd UFZLQoxb7zLBekzF7CGNVGhYwN/ShEllY1dxRMlTWutkIjkUTxlQtfNeN 3qHHA/eiXOaDH7DINfJjhCPH2O6r4PJi/3U/4IgGd5iSNKXOowBebTRH6 9QptTkW8pLcBk7aTV41Ly8KZDigzkq/TaP3jP5Y5Wq4wit3QpZz3scNvB A==; X-CSE-ConnectionGUID: zal8ltlATqqPdPqz71pQeQ== X-CSE-MsgGUID: eEzAp0vfSuyfykgDyEssXg== X-IronPort-AV: E=McAfee;i="6600,9927,11054"; a="9481805" X-IronPort-AV: E=Sophos;i="6.07,226,1708416000"; d="scan'208";a="9481805" Received: from fmviesa005.fm.intel.com ([10.60.135.145]) by fmvoesa112.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 24 Apr 2024 11:14:55 -0700 X-CSE-ConnectionGUID: B8SdKDfGSY6gXIMIt+bcpg== X-CSE-MsgGUID: amjNfRc4REOPlm9CAg1B7A== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.07,226,1708416000"; d="scan'208";a="29262597" Received: from agluck-desk3.sc.intel.com ([172.25.222.105]) by fmviesa005-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 24 Apr 2024 11:14:56 -0700 From: Tony Luck To: Borislav Petkov , Hans de Goede , =?UTF-8?q?Ilpo=20J=C3=A4rvinen?= Cc: "Rafael J. Wysocki" , Daniel Lezcano , Zhang Rui , Lukasz Luba , Srinivas Pandruvada , Tony Luck , linux-pm@vger.kernel.org, linux-kernel@vger.kernel.org, platform-driver-x86@vger.kernel.org, patches@lists.linux.dev, "Rafael J . Wysocki" Subject: [PATCH v4 13/71] ASoC: Intel: Switch to new Intel CPU model defines Date: Wed, 24 Apr 2024 11:14:55 -0700 Message-ID: <20240424181455.41404-1-tony.luck@intel.com> X-Mailer: git-send-email 2.44.0 In-Reply-To: <20240424181245.41141-1-tony.luck@intel.com> References: <20240424181245.41141-1-tony.luck@intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" New CPU #defines encode vendor and family as well as model. Signed-off-by: Tony Luck Acked-by: Rafael J. Wysocki Acked-by: Hans de Goede --- include/linux/platform_data/x86/soc.h | 12 ++++++------ drivers/thermal/intel/intel_soc_dts_thermal.c | 2 +- 2 files changed, 7 insertions(+), 7 deletions(-) diff --git a/include/linux/platform_data/x86/soc.h b/include/linux/platform= _data/x86/soc.h index a5705189e2ac..f981907a5cb0 100644 --- a/include/linux/platform_data/x86/soc.h +++ b/include/linux/platform_data/x86/soc.h @@ -20,7 +20,7 @@ static inline bool soc_intel_is_##soc(void) \ { \ static const struct x86_cpu_id soc##_cpu_ids[] =3D { \ - X86_MATCH_INTEL_FAM6_MODEL(type, NULL), \ + X86_MATCH_VFM(type, NULL), \ {} \ }; \ const struct x86_cpu_id *id; \ @@ -31,11 +31,11 @@ static inline bool soc_intel_is_##soc(void) \ return false; \ } =20 -SOC_INTEL_IS_CPU(byt, ATOM_SILVERMONT); -SOC_INTEL_IS_CPU(cht, ATOM_AIRMONT); -SOC_INTEL_IS_CPU(apl, ATOM_GOLDMONT); -SOC_INTEL_IS_CPU(glk, ATOM_GOLDMONT_PLUS); -SOC_INTEL_IS_CPU(cml, KABYLAKE_L); +SOC_INTEL_IS_CPU(byt, INTEL_ATOM_SILVERMONT); +SOC_INTEL_IS_CPU(cht, INTEL_ATOM_AIRMONT); +SOC_INTEL_IS_CPU(apl, INTEL_ATOM_GOLDMONT); +SOC_INTEL_IS_CPU(glk, INTEL_ATOM_GOLDMONT_PLUS); +SOC_INTEL_IS_CPU(cml, INTEL_KABYLAKE_L); =20 #undef SOC_INTEL_IS_CPU =20 diff --git a/drivers/thermal/intel/intel_soc_dts_thermal.c b/drivers/therma= l/intel/intel_soc_dts_thermal.c index 9c825c6e1f38..718c6326eaf4 100644 --- a/drivers/thermal/intel/intel_soc_dts_thermal.c +++ b/drivers/thermal/intel/intel_soc_dts_thermal.c @@ -36,7 +36,7 @@ static irqreturn_t soc_irq_thread_fn(int irq, void *dev_d= ata) } =20 static const struct x86_cpu_id soc_thermal_ids[] =3D { - X86_MATCH_INTEL_FAM6_MODEL(ATOM_SILVERMONT, BYT_SOC_DTS_APIC_IRQ), + X86_MATCH_VFM(INTEL_ATOM_SILVERMONT, BYT_SOC_DTS_APIC_IRQ), {} }; MODULE_DEVICE_TABLE(x86cpu, soc_thermal_ids); --=20 2.44.0 From nobody Sat Jul 11 15:40:01 2026 Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.18]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id DEFA116DECC; Wed, 24 Apr 2024 18:15:09 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=192.198.163.18 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1713982511; cv=none; b=renLRuxwQEGwy8ScUCS9fFuAwAvnOEiUnkz7/yTtOCMlOOVcEDsxtuzfgImXr1bpNoR0dcAuLy3g99tKEFvK0GxRGjdjeLb5snmQBjwgfzpLpyFBa/kPMv+M3ho08CcWqNhYSmPFs8c8IEstzRIFnOpBVqZJN1vA7gEFAjjjhkY= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1713982511; c=relaxed/simple; bh=sNx6nxhHZv+F6DxdU5u7m6Mfq8h17NXlRvSdlpt7fxI=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=bdC1zoVLAP0iEQVoqWcuyJxSunXCwKvndaro5LDpznAEEULgVodqI4IT2C8pu/hIb894RgJ9q8OD4Kzs/k4CzWrNr14G5i+FTssdARiug9qG1PrjAwLN1JyP7f52RAqa+WjbosuGAJV1ZRzAOtLMUgMBHlX2CymNkNdHSaldgKY= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com; spf=pass smtp.mailfrom=intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=ZEnXdl/G; arc=none smtp.client-ip=192.198.163.18 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="ZEnXdl/G" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1713982510; x=1745518510; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=sNx6nxhHZv+F6DxdU5u7m6Mfq8h17NXlRvSdlpt7fxI=; b=ZEnXdl/GG6GE6uLABEIZSS4uXYw/1tfz42OunpKl7jOnGw1KLZNippDY 5IAaDGwyIW7Umcj6Eo7ZgMzoWE1pOIxrWU9g229EvPzmvU5s5VNdWD6/N NMU+4VqBcFlDsZKygHtzDFeEY4nZFJUYipXhQsmhutbLD62FWjstwTMFY RtIkIQzwq9VYfkCBQ21J3MjgN0KMyuzvIgfXCpBA76OmWiEZp2KRveDkR ZMZ7ctU4IvTasSSaa2yAwCRkt74rRM2xrEbWg/JE4RPfkbwSv92Ap2CaF gDRo9Rz3IL8go2XdFlgs+5vqIWFV5hPUdBC0OhEBV2K6WSBDqM5ifKcTq g==; X-CSE-ConnectionGUID: uWll+EzDSoCH0gMAoBFDNQ== X-CSE-MsgGUID: hhZ0ZWKGRkGROSuY2SlE0Q== X-IronPort-AV: E=McAfee;i="6600,9927,11054"; a="9481815" X-IronPort-AV: E=Sophos;i="6.07,226,1708416000"; d="scan'208";a="9481815" Received: from fmviesa005.fm.intel.com ([10.60.135.145]) by fmvoesa112.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 24 Apr 2024 11:14:57 -0700 X-CSE-ConnectionGUID: 0AbnEi7OQd+FrmJxDs8yYA== X-CSE-MsgGUID: yAHssfhiSBq62zGao0DWng== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.07,226,1708416000"; d="scan'208";a="29262611" Received: from agluck-desk3.sc.intel.com ([172.25.222.105]) by fmviesa005-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 24 Apr 2024 11:14:57 -0700 From: Tony Luck To: Borislav Petkov , linux-kernel@vger.kernel.org Cc: "Rafael J. Wysocki" , Daniel Lezcano , Zhang Rui , Lukasz Luba , Tony Luck , Hans de Goede , Peter Zijlstra , linux-pm@vger.kernel.org, patches@lists.linux.dev, "Rafael J . Wysocki" Subject: [PATCH v4 14/71] thermal: intel: intel_tcc_cooling: Switch to new Intel CPU model defines Date: Wed, 24 Apr 2024 11:14:56 -0700 Message-ID: <20240424181456.41424-1-tony.luck@intel.com> X-Mailer: git-send-email 2.44.0 In-Reply-To: <20240424181245.41141-1-tony.luck@intel.com> References: <20240424181245.41141-1-tony.luck@intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" New CPU #defines encode vendor and family as well as model. Signed-off-by: Tony Luck Acked-by: Rafael J. Wysocki Acked-by: Hans de Goede --- drivers/thermal/intel/intel_tcc_cooling.c | 30 +++++++++++------------ 1 file changed, 15 insertions(+), 15 deletions(-) diff --git a/drivers/thermal/intel/intel_tcc_cooling.c b/drivers/thermal/in= tel/intel_tcc_cooling.c index 6c392147e6d1..63696e7d7b3c 100644 --- a/drivers/thermal/intel/intel_tcc_cooling.c +++ b/drivers/thermal/intel/intel_tcc_cooling.c @@ -49,21 +49,21 @@ static const struct thermal_cooling_device_ops tcc_cool= ing_ops =3D { }; =20 static const struct x86_cpu_id tcc_ids[] __initconst =3D { - X86_MATCH_INTEL_FAM6_MODEL(SKYLAKE, NULL), - X86_MATCH_INTEL_FAM6_MODEL(SKYLAKE_L, NULL), - X86_MATCH_INTEL_FAM6_MODEL(KABYLAKE, NULL), - X86_MATCH_INTEL_FAM6_MODEL(KABYLAKE_L, NULL), - X86_MATCH_INTEL_FAM6_MODEL(ICELAKE, NULL), - X86_MATCH_INTEL_FAM6_MODEL(ICELAKE_L, NULL), - X86_MATCH_INTEL_FAM6_MODEL(TIGERLAKE, NULL), - X86_MATCH_INTEL_FAM6_MODEL(TIGERLAKE_L, NULL), - X86_MATCH_INTEL_FAM6_MODEL(COMETLAKE, NULL), - X86_MATCH_INTEL_FAM6_MODEL(ALDERLAKE, NULL), - X86_MATCH_INTEL_FAM6_MODEL(ALDERLAKE_L, NULL), - X86_MATCH_INTEL_FAM6_MODEL(ATOM_GRACEMONT, NULL), - X86_MATCH_INTEL_FAM6_MODEL(RAPTORLAKE, NULL), - X86_MATCH_INTEL_FAM6_MODEL(RAPTORLAKE_P, NULL), - X86_MATCH_INTEL_FAM6_MODEL(RAPTORLAKE_S, NULL), + X86_MATCH_VFM(INTEL_SKYLAKE, NULL), + X86_MATCH_VFM(INTEL_SKYLAKE_L, NULL), + X86_MATCH_VFM(INTEL_KABYLAKE, NULL), + X86_MATCH_VFM(INTEL_KABYLAKE_L, NULL), + X86_MATCH_VFM(INTEL_ICELAKE, NULL), + X86_MATCH_VFM(INTEL_ICELAKE_L, NULL), + X86_MATCH_VFM(INTEL_TIGERLAKE, NULL), + X86_MATCH_VFM(INTEL_TIGERLAKE_L, NULL), + X86_MATCH_VFM(INTEL_COMETLAKE, NULL), + X86_MATCH_VFM(INTEL_ALDERLAKE, NULL), + X86_MATCH_VFM(INTEL_ALDERLAKE_L, NULL), + X86_MATCH_VFM(INTEL_ATOM_GRACEMONT, NULL), + X86_MATCH_VFM(INTEL_RAPTORLAKE, NULL), + X86_MATCH_VFM(INTEL_RAPTORLAKE_P, NULL), + X86_MATCH_VFM(INTEL_RAPTORLAKE_S, NULL), {} }; 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X-CSE-ConnectionGUID: vtZoP9TVQFupEMkj08Bodg== X-CSE-MsgGUID: +lMLyfPbRMCuCFXA69aTTQ== X-IronPort-AV: E=McAfee;i="6600,9927,11054"; a="9481824" X-IronPort-AV: E=Sophos;i="6.07,226,1708416000"; d="scan'208";a="9481824" Received: from fmviesa005.fm.intel.com ([10.60.135.145]) by fmvoesa112.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 24 Apr 2024 11:14:57 -0700 X-CSE-ConnectionGUID: 7sh3tqSbSeSfubi3E/olgg== X-CSE-MsgGUID: ry4T80adSoGxDPJ/cPtN6g== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.07,226,1708416000"; d="scan'208";a="29262616" Received: from agluck-desk3.sc.intel.com ([172.25.222.105]) by fmviesa005-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 24 Apr 2024 11:14:58 -0700 From: Tony Luck To: Borislav Petkov , linux-kernel@vger.kernel.org Cc: Len Brown , linux-pm@vger.kernel.org, patches@lists.linux.dev, Tony Luck , "Rafael J . Wysocki" Subject: [PATCH v4 15/71] tools/power/turbostat: Switch to new Intel CPU model defines Date: Wed, 24 Apr 2024 11:14:57 -0700 Message-ID: <20240424181457.41443-1-tony.luck@intel.com> X-Mailer: git-send-email 2.44.0 In-Reply-To: <20240424181245.41141-1-tony.luck@intel.com> References: <20240424181245.41141-1-tony.luck@intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" New CPU #defines encode vendor and family as well as model. N.B. Copied VFM_*() defines here from to avoid an application picking a second internel kernel header file. Signed-off-by: Tony Luck Acked-by: Rafael J. Wysocki Acked-by: Hans de Goede --- tools/power/x86/turbostat/turbostat.c | 161 +++++++++++++++----------- 1 file changed, 93 insertions(+), 68 deletions(-) diff --git a/tools/power/x86/turbostat/turbostat.c b/tools/power/x86/turbos= tat/turbostat.c index 7a334377f92b..68c660c58a13 100644 --- a/tools/power/x86/turbostat/turbostat.c +++ b/tools/power/x86/turbostat/turbostat.c @@ -9,6 +9,30 @@ =20 #define _GNU_SOURCE #include MSRHEADER + +// copied from arch/x86/include/asm/cpu_device_id.h +#define VFM_MODEL_BIT 0 +#define VFM_FAMILY_BIT 8 +#define VFM_VENDOR_BIT 16 +#define VFM_RSVD_BIT 24 + +#define VFM_MODEL_MASK GENMASK(VFM_FAMILY_BIT - 1, VFM_MODEL_BIT) +#define VFM_FAMILY_MASK GENMASK(VFM_VENDOR_BIT - 1, VFM_FAMILY_BIT) +#define VFM_VENDOR_MASK GENMASK(VFM_RSVD_BIT - 1, VFM_VENDOR_BIT) + +#define VFM_MODEL(vfm) (((vfm) & VFM_MODEL_MASK) >> VFM_MODEL_BIT) +#define VFM_FAMILY(vfm) (((vfm) & VFM_FAMILY_MASK) >> VFM_FAMILY_BIT) +#define VFM_VENDOR(vfm) (((vfm) & VFM_VENDOR_MASK) >> VFM_VENDOR_BIT) + +#define VFM_MAKE(_vendor, _family, _model) ( \ + ((_model) << VFM_MODEL_BIT) | \ + ((_family) << VFM_FAMILY_BIT) | \ + ((_vendor) << VFM_VENDOR_BIT) \ +) +// end copied section + +#define X86_VENDOR_INTEL 0 + #include INTEL_FAMILY_HEADER #include #include @@ -300,7 +324,7 @@ struct platform_features { }; =20 struct platform_data { - unsigned int model; + unsigned int vfm; const struct platform_features *features; }; =20 @@ -825,73 +849,73 @@ static const struct platform_features amd_features_wi= th_rapl =3D { }; =20 static const struct platform_data turbostat_pdata[] =3D { - { INTEL_FAM6_NEHALEM, &nhm_features }, - { INTEL_FAM6_NEHALEM_G, &nhm_features }, - { INTEL_FAM6_NEHALEM_EP, &nhm_features }, - { INTEL_FAM6_NEHALEM_EX, &nhx_features }, - { INTEL_FAM6_WESTMERE, &nhm_features }, - { INTEL_FAM6_WESTMERE_EP, &nhm_features }, - { INTEL_FAM6_WESTMERE_EX, &nhx_features }, - { INTEL_FAM6_SANDYBRIDGE, &snb_features }, - { INTEL_FAM6_SANDYBRIDGE_X, &snx_features }, - { INTEL_FAM6_IVYBRIDGE, &ivb_features }, - { INTEL_FAM6_IVYBRIDGE_X, &ivx_features }, - { INTEL_FAM6_HASWELL, &hsw_features }, - { INTEL_FAM6_HASWELL_X, &hsx_features }, - { INTEL_FAM6_HASWELL_L, &hswl_features }, - { INTEL_FAM6_HASWELL_G, &hswg_features }, - { INTEL_FAM6_BROADWELL, &bdw_features }, - { INTEL_FAM6_BROADWELL_G, &bdwg_features }, - { INTEL_FAM6_BROADWELL_X, &bdx_features }, - { INTEL_FAM6_BROADWELL_D, &bdx_features }, - { INTEL_FAM6_SKYLAKE_L, &skl_features }, - { INTEL_FAM6_SKYLAKE, &skl_features }, - { INTEL_FAM6_SKYLAKE_X, &skx_features }, - { INTEL_FAM6_KABYLAKE_L, &skl_features }, - { INTEL_FAM6_KABYLAKE, &skl_features }, - { INTEL_FAM6_COMETLAKE, &skl_features }, - { INTEL_FAM6_COMETLAKE_L, &skl_features }, - { INTEL_FAM6_CANNONLAKE_L, &cnl_features }, - { INTEL_FAM6_ICELAKE_X, &icx_features }, - { INTEL_FAM6_ICELAKE_D, &icx_features }, - { INTEL_FAM6_ICELAKE_L, &cnl_features }, - { INTEL_FAM6_ICELAKE_NNPI, &cnl_features }, - { INTEL_FAM6_ROCKETLAKE, &cnl_features }, - { INTEL_FAM6_TIGERLAKE_L, &cnl_features }, - { INTEL_FAM6_TIGERLAKE, &cnl_features }, - { INTEL_FAM6_SAPPHIRERAPIDS_X, &spr_features }, - { INTEL_FAM6_EMERALDRAPIDS_X, &spr_features }, - { INTEL_FAM6_GRANITERAPIDS_X, &spr_features }, - { INTEL_FAM6_LAKEFIELD, &cnl_features }, - { INTEL_FAM6_ALDERLAKE, &adl_features }, - { INTEL_FAM6_ALDERLAKE_L, &adl_features }, - { INTEL_FAM6_RAPTORLAKE, &adl_features }, - { INTEL_FAM6_RAPTORLAKE_P, &adl_features }, - { INTEL_FAM6_RAPTORLAKE_S, &adl_features }, - { INTEL_FAM6_METEORLAKE, &cnl_features }, - { INTEL_FAM6_METEORLAKE_L, &cnl_features }, - { INTEL_FAM6_ARROWLAKE, &cnl_features }, - { INTEL_FAM6_LUNARLAKE_M, &cnl_features }, - { INTEL_FAM6_ATOM_SILVERMONT, &slv_features }, - { INTEL_FAM6_ATOM_SILVERMONT_D, &slvd_features }, - { INTEL_FAM6_ATOM_AIRMONT, &amt_features }, - { INTEL_FAM6_ATOM_GOLDMONT, &gmt_features }, - { INTEL_FAM6_ATOM_GOLDMONT_D, &gmtd_features }, - { INTEL_FAM6_ATOM_GOLDMONT_PLUS, &gmtp_features }, - { INTEL_FAM6_ATOM_TREMONT_D, &tmtd_features }, - { INTEL_FAM6_ATOM_TREMONT, &tmt_features }, - { INTEL_FAM6_ATOM_TREMONT_L, &tmt_features }, - { INTEL_FAM6_ATOM_GRACEMONT, &adl_features }, - { INTEL_FAM6_ATOM_CRESTMONT_X, &srf_features }, - { INTEL_FAM6_ATOM_CRESTMONT, &grr_features }, - { INTEL_FAM6_XEON_PHI_KNL, &knl_features }, - { INTEL_FAM6_XEON_PHI_KNM, &knl_features }, + { INTEL_NEHALEM, &nhm_features }, + { INTEL_NEHALEM_G, &nhm_features }, + { INTEL_NEHALEM_EP, &nhm_features }, + { INTEL_NEHALEM_EX, &nhx_features }, + { INTEL_WESTMERE, &nhm_features }, + { INTEL_WESTMERE_EP, &nhm_features }, + { INTEL_WESTMERE_EX, &nhx_features }, + { INTEL_SANDYBRIDGE, &snb_features }, + { INTEL_SANDYBRIDGE_X, &snx_features }, + { INTEL_IVYBRIDGE, &ivb_features }, + { INTEL_IVYBRIDGE_X, &ivx_features }, + { INTEL_HASWELL, &hsw_features }, + { INTEL_HASWELL_X, &hsx_features }, + { INTEL_HASWELL_L, &hswl_features }, + { INTEL_HASWELL_G, &hswg_features }, + { INTEL_BROADWELL, &bdw_features }, + { INTEL_BROADWELL_G, &bdwg_features }, + { INTEL_BROADWELL_X, &bdx_features }, + { INTEL_BROADWELL_D, &bdx_features }, + { INTEL_SKYLAKE_L, &skl_features }, + { INTEL_SKYLAKE, &skl_features }, + { INTEL_SKYLAKE_X, &skx_features }, + { INTEL_KABYLAKE_L, &skl_features }, + { INTEL_KABYLAKE, &skl_features }, + { INTEL_COMETLAKE, &skl_features }, + { INTEL_COMETLAKE_L, &skl_features }, + { INTEL_CANNONLAKE_L, &cnl_features }, + { INTEL_ICELAKE_X, &icx_features }, + { INTEL_ICELAKE_D, &icx_features }, + { INTEL_ICELAKE_L, &cnl_features }, + { INTEL_ICELAKE_NNPI, &cnl_features }, + { INTEL_ROCKETLAKE, &cnl_features }, + { INTEL_TIGERLAKE_L, &cnl_features }, + { INTEL_TIGERLAKE, &cnl_features }, + { INTEL_SAPPHIRERAPIDS_X, &spr_features }, + { INTEL_EMERALDRAPIDS_X, &spr_features }, + { INTEL_GRANITERAPIDS_X, &spr_features }, + { INTEL_LAKEFIELD, &cnl_features }, + { INTEL_ALDERLAKE, &adl_features }, + { INTEL_ALDERLAKE_L, &adl_features }, + { INTEL_RAPTORLAKE, &adl_features }, + { INTEL_RAPTORLAKE_P, &adl_features }, + { INTEL_RAPTORLAKE_S, &adl_features }, + { INTEL_METEORLAKE, &cnl_features }, + { INTEL_METEORLAKE_L, &cnl_features }, + { INTEL_ARROWLAKE, &cnl_features }, + { INTEL_LUNARLAKE_M, &cnl_features }, + { INTEL_ATOM_SILVERMONT, &slv_features }, + { INTEL_ATOM_SILVERMONT_D, &slvd_features }, + { INTEL_ATOM_AIRMONT, &amt_features }, + { INTEL_ATOM_GOLDMONT, &gmt_features }, + { INTEL_ATOM_GOLDMONT_D, &gmtd_features }, + { INTEL_ATOM_GOLDMONT_PLUS, &gmtp_features }, + { INTEL_ATOM_TREMONT_D, &tmtd_features }, + { INTEL_ATOM_TREMONT, &tmt_features }, + { INTEL_ATOM_TREMONT_L, &tmt_features }, + { INTEL_ATOM_GRACEMONT, &adl_features }, + { INTEL_ATOM_CRESTMONT_X, &srf_features }, + { INTEL_ATOM_CRESTMONT, &grr_features }, + { INTEL_XEON_PHI_KNL, &knl_features }, + { INTEL_XEON_PHI_KNM, &knl_features }, /* * Missing support for - * INTEL_FAM6_ICELAKE - * INTEL_FAM6_ATOM_SILVERMONT_MID - * INTEL_FAM6_ATOM_AIRMONT_MID - * INTEL_FAM6_ATOM_AIRMONT_NP + * INTEL_ICELAKE + * INTEL_ATOM_SILVERMONT_MID + * INTEL_ATOM_AIRMONT_MID + * INTEL_ATOM_AIRMONT_NP */ { 0, NULL }, }; @@ -916,11 +940,12 @@ void probe_platform_features(unsigned int family, uns= igned int model) return; } =20 - if (!genuine_intel || family !=3D 6) + if (!genuine_intel) return; =20 for (i =3D 0; turbostat_pdata[i].features; i++) { - if (turbostat_pdata[i].model =3D=3D model) { + if (VFM_FAMILY(turbostat_pdata[i].vfm) =3D=3D family && + VFM_MODEL(turbostat_pdata[i].vfm) =3D=3D model) { platform =3D turbostat_pdata[i].features; return; } --=20 2.44.0 From nobody Sat Jul 11 15:40:01 2026 Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.18]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 74835174EE3; Wed, 24 Apr 2024 18:15:10 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=192.198.163.18 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1713982513; cv=none; b=h1k3RnsQ+NKC8eR9IoZHC3B17Iq+USPCxiSnnjTMq82Y1E6rqOPEI3THx8f8QGD1O8LrRGU1W20+1ALRx0xJFtPQeqGSCHl7eXM8UdEXPReSlsFKLS5zAyda840jk6//ahZeo3apZZKrH2aUh1l9xxKcPeprW67S70j5A4oB6JA= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1713982513; c=relaxed/simple; bh=J3/S5BDaJa8W6a3KT1KDi2bLZ8czh8Tc2c5pQvZ+hqQ=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=FfhCDGKXhCEVJ/V8X+FPgtkXY/8HlepxAk0zsbkKOIVver/43goEBnbKWwe8qgBmctnJQglysTRspQzmLXjrA20a/mfxTyrFBxiEb5AeeNFI+nIwlWfVUKdQQxptqxsY2+AVumz1YLADtjbqqy20W93oPajPuBiFPuP6bkWSJPQ= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com; spf=pass smtp.mailfrom=intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=BNDIqVTM; arc=none smtp.client-ip=192.198.163.18 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="BNDIqVTM" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1713982510; x=1745518510; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=J3/S5BDaJa8W6a3KT1KDi2bLZ8czh8Tc2c5pQvZ+hqQ=; b=BNDIqVTMzwD9X2rCh5L85ScV8YWvZiUb8Nqmaog3vNPPQuGW3PPrlexZ Z8sG+yADwc7j3VM+SwN+AznkR5agELXI9HWU9nsmMEOdfLDKNXA+SWLRH gjqSlffPKw57cgoiJ50l+K/ew1HJqk+klQzNIC4Hg+mqIMfy0CPyzOX1W YDNOxzgR2Bah3nEWjF5fS5KToCt88/FnANxTbZ2gzU2XVwN+A88193Vxs xTGNNF9CVHalOSgfQn3JXyjzGqGW7h/0wdypgQv02gk5tNvhIJ6tbQDnU 2MGz5HrGfKQky4zDJdBbHfzwvYZvW9mwQdiACPEwBLorZi9K5o6Q39YK7 g==; X-CSE-ConnectionGUID: rYt9Py0cQNqnyY0Q7RA59A== X-CSE-MsgGUID: DwEmI1I5Qz+0TMLTt8j+rA== X-IronPort-AV: E=McAfee;i="6600,9927,11054"; a="9481831" X-IronPort-AV: E=Sophos;i="6.07,226,1708416000"; d="scan'208";a="9481831" Received: from fmviesa005.fm.intel.com ([10.60.135.145]) by fmvoesa112.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 24 Apr 2024 11:14:58 -0700 X-CSE-ConnectionGUID: d+wTH2E0R+KvUsjkrxPzkQ== X-CSE-MsgGUID: 6r5h0f+ET6+PHYO0YHMU4A== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.07,226,1708416000"; d="scan'208";a="29262622" Received: from agluck-desk3.sc.intel.com ([172.25.222.105]) by fmviesa005-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 24 Apr 2024 11:14:58 -0700 From: Tony Luck To: Borislav Petkov , Herbert Xu , "David S. Miller" , Thomas Gleixner , Ingo Molnar , Dave Hansen , x86@kernel.org Cc: "H. Peter Anvin" , linux-crypto@vger.kernel.org, linux-kernel@vger.kernel.org, patches@lists.linux.dev, Tony Luck Subject: [PATCH v4 16/71] crypto: x86/poly1305 - Switch to new Intel CPU model defines Date: Wed, 24 Apr 2024 11:14:58 -0700 Message-ID: <20240424181458.41462-1-tony.luck@intel.com> X-Mailer: git-send-email 2.44.0 In-Reply-To: <20240424181245.41141-1-tony.luck@intel.com> References: <20240424181245.41141-1-tony.luck@intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" New CPU #defines encode vendor and family as well as model. Signed-off-by: Tony Luck Acked-by: Hans de Goede --- arch/x86/crypto/poly1305_glue.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/x86/crypto/poly1305_glue.c b/arch/x86/crypto/poly1305_glu= e.c index 1dfb8af48a3c..08ff4b489f7e 100644 --- a/arch/x86/crypto/poly1305_glue.c +++ b/arch/x86/crypto/poly1305_glue.c @@ -12,7 +12,7 @@ #include #include #include -#include +#include #include =20 asmlinkage void poly1305_init_x86_64(void *ctx, @@ -269,7 +269,7 @@ static int __init poly1305_simd_mod_init(void) boot_cpu_has(X86_FEATURE_AVX2) && boot_cpu_has(X86_FEATURE_AVX512F) && cpu_has_xfeatures(XFEATURE_MASK_SSE | XFEATURE_MASK_YMM | XFEATURE_MA= SK_AVX512, NULL) && /* Skylake downclocks unacceptably much when using zmm, but later gen= erations are fast. */ - boot_cpu_data.x86_model !=3D INTEL_FAM6_SKYLAKE_X) + boot_cpu_data.x86_vfm !=3D INTEL_SKYLAKE_X) static_branch_enable(&poly1305_use_avx512); return IS_REACHABLE(CONFIG_CRYPTO_HASH) ? crypto_register_shash(&alg) : 0; } --=20 2.44.0 From nobody Sat Jul 11 15:40:01 2026 Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.18]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A92D3178CF1; Wed, 24 Apr 2024 18:15:11 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=192.198.163.18 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1713982513; cv=none; b=kbUi8Ltz8BhWdB+lpoVkxbJ0UDdbTnyLCPggx2KRJuTW5MhwokLCWbbkN1XgzedesL8D5DMjqR2AlgqWCclhwp6R8Xr6t9yB+AozmduJdMHApsbNshKAA6Jbu0YkaYACIVS71nAJCLf0fhIqn6jtt1IGPeMa4v7UBotbNvbuwuE= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1713982513; c=relaxed/simple; bh=CwybUVe8crx1l4CZK03c9vCx8DvC8Bgt8uPcKdw9g+E=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=EVzH1jitA5Sh2gx09/HvH3daPjAfI7gBk/Ilpss1IwsFGWJoG6NEd2mDWmv8XS+O2AOZC0dX3Kt+xp1lji1pJbHrtAMpeEYIr5o6xztmwAzMoh4GugFzZWrP1cIgcv2xhKolnZitRUNY+vLJYQKSh7cMzMloqQ2jRoPTAClaKf8= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com; spf=pass smtp.mailfrom=intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=bAAcl3uF; arc=none smtp.client-ip=192.198.163.18 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="bAAcl3uF" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1713982511; x=1745518511; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=CwybUVe8crx1l4CZK03c9vCx8DvC8Bgt8uPcKdw9g+E=; b=bAAcl3uFqRB9u8Gf3IwmVVdlEML24vDkIZ2J+EnIUeNIIq7e3dq7Ssnp 9vXumMjUDrBdGa/HQIBK8QGs+DZ6R4lcnF+Zvtn61Jkr0ACKiyYChRNHJ WmGCHjXe0RHGaGqxfx61OuKJ5aOsUO6wImFJqOe/JOHcMw87vYu3eCzuN fFkMWL1X8euGoplAqtDb+ccVBoe/rkasHlcW6mlbpoBkpqtjdSMtPNKpK GiKyypZfilfBXyFK2/p/FvSEcZ3MQ1Dfo2iScVOVxGBinIdod3Qxw1qSL POPrseuLRSm+DB9nMfDsdweAP0ikM4WMhtQ67a8JCod4/K6wRzpFJG27n w==; X-CSE-ConnectionGUID: uHGqBQJ0SkOyduGKD8eHjA== X-CSE-MsgGUID: RZ+vYtXeQyKgftJTZUb8xA== X-IronPort-AV: E=McAfee;i="6600,9927,11054"; a="9481843" X-IronPort-AV: E=Sophos;i="6.07,226,1708416000"; d="scan'208";a="9481843" Received: from fmviesa005.fm.intel.com ([10.60.135.145]) by fmvoesa112.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 24 Apr 2024 11:14:59 -0700 X-CSE-ConnectionGUID: fIvJjhdlSqKYHN3AWZyHZg== X-CSE-MsgGUID: jJio6ahnToe8mAdZagIthw== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.07,226,1708416000"; d="scan'208";a="29262631" Received: from agluck-desk3.sc.intel.com ([172.25.222.105]) by fmviesa005-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 24 Apr 2024 11:14:59 -0700 From: Tony Luck To: Borislav Petkov , Herbert Xu , "David S. Miller" , Thomas Gleixner , Ingo Molnar , Dave Hansen , x86@kernel.org Cc: "H. Peter Anvin" , linux-crypto@vger.kernel.org, linux-kernel@vger.kernel.org, patches@lists.linux.dev, Tony Luck Subject: [PATCH v4 17/71] crypto: x86/twofish - Switch to new Intel CPU model defines Date: Wed, 24 Apr 2024 11:14:58 -0700 Message-ID: <20240424181458.41481-1-tony.luck@intel.com> X-Mailer: git-send-email 2.44.0 In-Reply-To: <20240424181245.41141-1-tony.luck@intel.com> References: <20240424181245.41141-1-tony.luck@intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" New CPU #defines encode vendor and family as well as model. Signed-off-by: Tony Luck Acked-by: Hans de Goede --- arch/x86/crypto/twofish_glue_3way.c | 10 ++++++---- 1 file changed, 6 insertions(+), 4 deletions(-) diff --git a/arch/x86/crypto/twofish_glue_3way.c b/arch/x86/crypto/twofish_= glue_3way.c index 90454cf18e0d..82311249048f 100644 --- a/arch/x86/crypto/twofish_glue_3way.c +++ b/arch/x86/crypto/twofish_glue_3way.c @@ -12,6 +12,8 @@ #include #include =20 +#include + #include "twofish.h" #include "ecb_cbc_helpers.h" =20 @@ -107,10 +109,10 @@ static bool is_blacklisted_cpu(void) if (boot_cpu_data.x86_vendor !=3D X86_VENDOR_INTEL) return false; =20 - if (boot_cpu_data.x86 =3D=3D 0x06 && - (boot_cpu_data.x86_model =3D=3D 0x1c || - boot_cpu_data.x86_model =3D=3D 0x26 || - boot_cpu_data.x86_model =3D=3D 0x36)) { + switch (boot_cpu_data.x86_vfm) { + case INTEL_ATOM_BONNELL: + case INTEL_ATOM_BONNELL_MID: + case INTEL_ATOM_SALTWELL: /* * On Atom, twofish-3way is slower than original assembler * implementation. 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Peter Anvin" , linux-perf-users@vger.kernel.org, linux-kernel@vger.kernel.org, patches@lists.linux.dev, Tony Luck Subject: [PATCH v4 18/71] perf/x86/intel/cstate: Switch to new Intel CPU model defines Date: Wed, 24 Apr 2024 11:14:59 -0700 Message-ID: <20240424181459.41500-1-tony.luck@intel.com> X-Mailer: git-send-email 2.44.0 In-Reply-To: <20240424181245.41141-1-tony.luck@intel.com> References: <20240424181245.41141-1-tony.luck@intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" New CPU #defines encode vendor and family as well as model. Signed-off-by: Tony Luck Acked-by: Hans de Goede --- arch/x86/events/intel/cstate.c | 144 ++++++++++++++++----------------- 1 file changed, 72 insertions(+), 72 deletions(-) diff --git a/arch/x86/events/intel/cstate.c b/arch/x86/events/intel/cstate.c index 326c8cd5aa2d..54eb142810fb 100644 --- a/arch/x86/events/intel/cstate.c +++ b/arch/x86/events/intel/cstate.c @@ -696,78 +696,78 @@ static const struct cstate_model srf_cstates __initco= nst =3D { =20 =20 static const struct x86_cpu_id intel_cstates_match[] __initconst =3D { - X86_MATCH_INTEL_FAM6_MODEL(NEHALEM, &nhm_cstates), - X86_MATCH_INTEL_FAM6_MODEL(NEHALEM_EP, &nhm_cstates), - X86_MATCH_INTEL_FAM6_MODEL(NEHALEM_EX, &nhm_cstates), - - X86_MATCH_INTEL_FAM6_MODEL(WESTMERE, &nhm_cstates), - X86_MATCH_INTEL_FAM6_MODEL(WESTMERE_EP, &nhm_cstates), - X86_MATCH_INTEL_FAM6_MODEL(WESTMERE_EX, &nhm_cstates), - - X86_MATCH_INTEL_FAM6_MODEL(SANDYBRIDGE, &snb_cstates), - X86_MATCH_INTEL_FAM6_MODEL(SANDYBRIDGE_X, &snb_cstates), - - X86_MATCH_INTEL_FAM6_MODEL(IVYBRIDGE, &snb_cstates), - X86_MATCH_INTEL_FAM6_MODEL(IVYBRIDGE_X, &snb_cstates), - - X86_MATCH_INTEL_FAM6_MODEL(HASWELL, &snb_cstates), - X86_MATCH_INTEL_FAM6_MODEL(HASWELL_X, &snb_cstates), - X86_MATCH_INTEL_FAM6_MODEL(HASWELL_G, &snb_cstates), - - X86_MATCH_INTEL_FAM6_MODEL(HASWELL_L, &hswult_cstates), - - X86_MATCH_INTEL_FAM6_MODEL(ATOM_SILVERMONT, &slm_cstates), - X86_MATCH_INTEL_FAM6_MODEL(ATOM_SILVERMONT_D, &slm_cstates), - X86_MATCH_INTEL_FAM6_MODEL(ATOM_AIRMONT, &slm_cstates), - - X86_MATCH_INTEL_FAM6_MODEL(BROADWELL, &snb_cstates), - X86_MATCH_INTEL_FAM6_MODEL(BROADWELL_D, &snb_cstates), - X86_MATCH_INTEL_FAM6_MODEL(BROADWELL_G, &snb_cstates), - X86_MATCH_INTEL_FAM6_MODEL(BROADWELL_X, &snb_cstates), - - X86_MATCH_INTEL_FAM6_MODEL(SKYLAKE_L, &snb_cstates), - X86_MATCH_INTEL_FAM6_MODEL(SKYLAKE, &snb_cstates), - X86_MATCH_INTEL_FAM6_MODEL(SKYLAKE_X, &snb_cstates), - - X86_MATCH_INTEL_FAM6_MODEL(KABYLAKE_L, &hswult_cstates), - X86_MATCH_INTEL_FAM6_MODEL(KABYLAKE, &hswult_cstates), - X86_MATCH_INTEL_FAM6_MODEL(COMETLAKE_L, &hswult_cstates), - X86_MATCH_INTEL_FAM6_MODEL(COMETLAKE, &hswult_cstates), - - X86_MATCH_INTEL_FAM6_MODEL(CANNONLAKE_L, &cnl_cstates), - - X86_MATCH_INTEL_FAM6_MODEL(XEON_PHI_KNL, &knl_cstates), - X86_MATCH_INTEL_FAM6_MODEL(XEON_PHI_KNM, &knl_cstates), - - X86_MATCH_INTEL_FAM6_MODEL(ATOM_GOLDMONT, &glm_cstates), - X86_MATCH_INTEL_FAM6_MODEL(ATOM_GOLDMONT_D, &glm_cstates), - X86_MATCH_INTEL_FAM6_MODEL(ATOM_GOLDMONT_PLUS, &glm_cstates), - X86_MATCH_INTEL_FAM6_MODEL(ATOM_TREMONT_D, &glm_cstates), - X86_MATCH_INTEL_FAM6_MODEL(ATOM_TREMONT, &glm_cstates), - X86_MATCH_INTEL_FAM6_MODEL(ATOM_TREMONT_L, &glm_cstates), - X86_MATCH_INTEL_FAM6_MODEL(ATOM_GRACEMONT, &adl_cstates), - X86_MATCH_INTEL_FAM6_MODEL(ATOM_CRESTMONT_X, &srf_cstates), - X86_MATCH_INTEL_FAM6_MODEL(ATOM_CRESTMONT, &grr_cstates), - - X86_MATCH_INTEL_FAM6_MODEL(ICELAKE_L, &icl_cstates), - X86_MATCH_INTEL_FAM6_MODEL(ICELAKE, &icl_cstates), - X86_MATCH_INTEL_FAM6_MODEL(ICELAKE_X, &icx_cstates), - X86_MATCH_INTEL_FAM6_MODEL(ICELAKE_D, &icx_cstates), - X86_MATCH_INTEL_FAM6_MODEL(SAPPHIRERAPIDS_X, &icx_cstates), - X86_MATCH_INTEL_FAM6_MODEL(EMERALDRAPIDS_X, &icx_cstates), - X86_MATCH_INTEL_FAM6_MODEL(GRANITERAPIDS_X, &icx_cstates), - X86_MATCH_INTEL_FAM6_MODEL(GRANITERAPIDS_D, &icx_cstates), - - X86_MATCH_INTEL_FAM6_MODEL(TIGERLAKE_L, &icl_cstates), - X86_MATCH_INTEL_FAM6_MODEL(TIGERLAKE, &icl_cstates), - X86_MATCH_INTEL_FAM6_MODEL(ROCKETLAKE, &icl_cstates), - X86_MATCH_INTEL_FAM6_MODEL(ALDERLAKE, &adl_cstates), - X86_MATCH_INTEL_FAM6_MODEL(ALDERLAKE_L, &adl_cstates), - X86_MATCH_INTEL_FAM6_MODEL(RAPTORLAKE, &adl_cstates), - X86_MATCH_INTEL_FAM6_MODEL(RAPTORLAKE_P, &adl_cstates), - X86_MATCH_INTEL_FAM6_MODEL(RAPTORLAKE_S, &adl_cstates), - X86_MATCH_INTEL_FAM6_MODEL(METEORLAKE, &adl_cstates), - X86_MATCH_INTEL_FAM6_MODEL(METEORLAKE_L, &adl_cstates), + X86_MATCH_VFM(INTEL_NEHALEM, &nhm_cstates), + X86_MATCH_VFM(INTEL_NEHALEM_EP, &nhm_cstates), + X86_MATCH_VFM(INTEL_NEHALEM_EX, &nhm_cstates), + + X86_MATCH_VFM(INTEL_WESTMERE, &nhm_cstates), + X86_MATCH_VFM(INTEL_WESTMERE_EP, &nhm_cstates), + X86_MATCH_VFM(INTEL_WESTMERE_EX, &nhm_cstates), + + X86_MATCH_VFM(INTEL_SANDYBRIDGE, &snb_cstates), + X86_MATCH_VFM(INTEL_SANDYBRIDGE_X, &snb_cstates), + + X86_MATCH_VFM(INTEL_IVYBRIDGE, &snb_cstates), + X86_MATCH_VFM(INTEL_IVYBRIDGE_X, &snb_cstates), + + X86_MATCH_VFM(INTEL_HASWELL, &snb_cstates), + X86_MATCH_VFM(INTEL_HASWELL_X, &snb_cstates), + X86_MATCH_VFM(INTEL_HASWELL_G, &snb_cstates), + + X86_MATCH_VFM(INTEL_HASWELL_L, &hswult_cstates), + + X86_MATCH_VFM(INTEL_ATOM_SILVERMONT, &slm_cstates), + X86_MATCH_VFM(INTEL_ATOM_SILVERMONT_D, &slm_cstates), + X86_MATCH_VFM(INTEL_ATOM_AIRMONT, &slm_cstates), + + X86_MATCH_VFM(INTEL_BROADWELL, &snb_cstates), + X86_MATCH_VFM(INTEL_BROADWELL_D, &snb_cstates), + X86_MATCH_VFM(INTEL_BROADWELL_G, &snb_cstates), + X86_MATCH_VFM(INTEL_BROADWELL_X, &snb_cstates), + + X86_MATCH_VFM(INTEL_SKYLAKE_L, &snb_cstates), + X86_MATCH_VFM(INTEL_SKYLAKE, &snb_cstates), + X86_MATCH_VFM(INTEL_SKYLAKE_X, &snb_cstates), + + X86_MATCH_VFM(INTEL_KABYLAKE_L, &hswult_cstates), + X86_MATCH_VFM(INTEL_KABYLAKE, &hswult_cstates), + X86_MATCH_VFM(INTEL_COMETLAKE_L, &hswult_cstates), + X86_MATCH_VFM(INTEL_COMETLAKE, &hswult_cstates), + + X86_MATCH_VFM(INTEL_CANNONLAKE_L, &cnl_cstates), + + X86_MATCH_VFM(INTEL_XEON_PHI_KNL, &knl_cstates), + X86_MATCH_VFM(INTEL_XEON_PHI_KNM, &knl_cstates), + + X86_MATCH_VFM(INTEL_ATOM_GOLDMONT, &glm_cstates), + X86_MATCH_VFM(INTEL_ATOM_GOLDMONT_D, &glm_cstates), + X86_MATCH_VFM(INTEL_ATOM_GOLDMONT_PLUS, &glm_cstates), + X86_MATCH_VFM(INTEL_ATOM_TREMONT_D, &glm_cstates), + X86_MATCH_VFM(INTEL_ATOM_TREMONT, &glm_cstates), + X86_MATCH_VFM(INTEL_ATOM_TREMONT_L, &glm_cstates), + X86_MATCH_VFM(INTEL_ATOM_GRACEMONT, &adl_cstates), + X86_MATCH_VFM(INTEL_ATOM_CRESTMONT_X, &srf_cstates), + X86_MATCH_VFM(INTEL_ATOM_CRESTMONT, &grr_cstates), + + X86_MATCH_VFM(INTEL_ICELAKE_L, &icl_cstates), + X86_MATCH_VFM(INTEL_ICELAKE, &icl_cstates), + X86_MATCH_VFM(INTEL_ICELAKE_X, &icx_cstates), + X86_MATCH_VFM(INTEL_ICELAKE_D, &icx_cstates), + X86_MATCH_VFM(INTEL_SAPPHIRERAPIDS_X, &icx_cstates), + X86_MATCH_VFM(INTEL_EMERALDRAPIDS_X, &icx_cstates), + X86_MATCH_VFM(INTEL_GRANITERAPIDS_X, &icx_cstates), + X86_MATCH_VFM(INTEL_GRANITERAPIDS_D, &icx_cstates), + + X86_MATCH_VFM(INTEL_TIGERLAKE_L, &icl_cstates), + X86_MATCH_VFM(INTEL_TIGERLAKE, &icl_cstates), + X86_MATCH_VFM(INTEL_ROCKETLAKE, &icl_cstates), + X86_MATCH_VFM(INTEL_ALDERLAKE, &adl_cstates), + X86_MATCH_VFM(INTEL_ALDERLAKE_L, &adl_cstates), + X86_MATCH_VFM(INTEL_RAPTORLAKE, &adl_cstates), + X86_MATCH_VFM(INTEL_RAPTORLAKE_P, &adl_cstates), + X86_MATCH_VFM(INTEL_RAPTORLAKE_S, &adl_cstates), + X86_MATCH_VFM(INTEL_METEORLAKE, &adl_cstates), + X86_MATCH_VFM(INTEL_METEORLAKE_L, &adl_cstates), { }, }; MODULE_DEVICE_TABLE(x86cpu, intel_cstates_match); --=20 2.44.0 From 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([172.25.222.105]) by fmviesa005-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 24 Apr 2024 11:15:00 -0700 From: Tony Luck To: Borislav Petkov , Thomas Gleixner , Dave Hansen , x86@kernel.org Cc: Peter Zijlstra , Ingo Molnar , Arnaldo Carvalho de Melo , Namhyung Kim , Mark Rutland , Alexander Shishkin , Jiri Olsa , Ian Rogers , Adrian Hunter , "H. Peter Anvin" , linux-perf-users@vger.kernel.org, linux-kernel@vger.kernel.org, patches@lists.linux.dev, Tony Luck Subject: [PATCH v4 19/71] perf/x86/lbr: Switch to new Intel CPU model defines Date: Wed, 24 Apr 2024 11:15:00 -0700 Message-ID: <20240424181500.41519-1-tony.luck@intel.com> X-Mailer: git-send-email 2.44.0 In-Reply-To: <20240424181245.41141-1-tony.luck@intel.com> References: <20240424181245.41141-1-tony.luck@intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" New CPU #defines encode vendor and family as well as model. Signed-off-by: Tony Luck Acked-by: Hans de Goede --- arch/x86/events/intel/lbr.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/arch/x86/events/intel/lbr.c b/arch/x86/events/intel/lbr.c index 78cd5084104e..86277196ffad 100644 --- a/arch/x86/events/intel/lbr.c +++ b/arch/x86/events/intel/lbr.c @@ -2,6 +2,7 @@ #include #include =20 +#include #include #include =20 @@ -1457,7 +1458,7 @@ void __init intel_pmu_lbr_init_atom(void) * to have an operational LBR which can freeze * on PMU interrupt */ - if (boot_cpu_data.x86_model =3D=3D 28 + if (boot_cpu_data.x86_vfm =3D=3D INTEL_ATOM_BONNELL && boot_cpu_data.x86_stepping < 10) { pr_cont("LBR disabled due to erratum"); return; --=20 2.44.0 From nobody Sat Jul 11 15:40:01 2026 Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.18]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 8DEE417B4E5; Wed, 24 Apr 2024 18:15:13 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=192.198.163.18 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1713982515; cv=none; b=XMR4rl/2K9x5Y7AFUbs/NcMzg4PvzccIG1bp44+AFeB9R6rKm551dJ4r4THfQlKQfNFvbOLdBBkHr3gN6Kb12ljaXPOYpyBs22bFhQnoLEancjW3mYtI0H+h4Ho/r9OqeFXOE6Gx57rhst6IgZ6DKt4IhcNxrgNme6q66yb7IRo= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1713982515; c=relaxed/simple; bh=xV3Oh1McKHpj/3XYu97f2x4TjCIeJO+j0gsK/dnPiOQ=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=XfRBzUQ/bSpAv4lfiPIhShVJLepehOUZjqSof1KpxRBq2194lSW7opMC36Lz79JjCnYAwgBfoKlaA2GhfV5N8p+HYQQOOagnfEJ6mJ557/ZUAbdAAwIhOpFuaNtEHH+KIEIwFNWbV4KoU5IS+QIfGns6xvQ0egf5xLmF5QN4Z4s= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com; spf=pass smtp.mailfrom=intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=XxRrveoH; arc=none smtp.client-ip=192.198.163.18 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="XxRrveoH" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1713982513; x=1745518513; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=xV3Oh1McKHpj/3XYu97f2x4TjCIeJO+j0gsK/dnPiOQ=; b=XxRrveoHcMyP9i05jFIY6svpOvO2/gQ4UPK/+YCOFjNGIXJo6OqQHSLY 1MGwoOM3/VcO3WX4NrICdlX/T/h2XYksjnFVSQzXgPbVA7gX2uadPmQeU eQRzGg0CYe7WcP9vjrGzAiOsEv1F8/PMHmQm7+qTWzYVQ09NMYIwH6Auj fkz0l7ZbwOSvtSVUkeX8YnYC20EzCJb1A7FFC8b22nByfGL9diSEoqMDm su04SATE4LJY2hfN7o3/SJ8mEjyBeWufC2mzgF1rHhJIc1z5WMbKMplSX 68MTQNeyMi5kXwK/adePGLeWv3c9zhSVdaV3OirM2iRIBsL/EonoYz/uO w==; X-CSE-ConnectionGUID: qFLZMwO4R1CNsO+qJ1DOSg== X-CSE-MsgGUID: exIjYjvkTgaEJLfpEjfr6Q== X-IronPort-AV: E=McAfee;i="6600,9927,11054"; a="9481876" X-IronPort-AV: E=Sophos;i="6.07,226,1708416000"; d="scan'208";a="9481876" Received: from fmviesa005.fm.intel.com ([10.60.135.145]) by fmvoesa112.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 24 Apr 2024 11:15:01 -0700 X-CSE-ConnectionGUID: S4RPMVBYTBGkd5lj1nvPXg== X-CSE-MsgGUID: 879y5PT3TXSQjKvb/qvLQA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.07,226,1708416000"; d="scan'208";a="29262647" Received: from agluck-desk3.sc.intel.com ([172.25.222.105]) by fmviesa005-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 24 Apr 2024 11:15:01 -0700 From: Tony Luck To: Borislav Petkov , Thomas Gleixner , Dave Hansen , x86@kernel.org Cc: Peter Zijlstra , Ingo Molnar , Arnaldo Carvalho de Melo , Namhyung Kim , Mark Rutland , Alexander Shishkin , Jiri Olsa , Ian Rogers , Adrian Hunter , "H. Peter Anvin" , linux-perf-users@vger.kernel.org, linux-kernel@vger.kernel.org, patches@lists.linux.dev, Tony Luck Subject: [PATCH v4 20/71] perf/x86/intel/pt: Switch to new Intel CPU model defines Date: Wed, 24 Apr 2024 11:15:00 -0700 Message-ID: <20240424181500.41538-1-tony.luck@intel.com> X-Mailer: git-send-email 2.44.0 In-Reply-To: <20240424181245.41141-1-tony.luck@intel.com> References: <20240424181245.41141-1-tony.luck@intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" New CPU #defines encode vendor and family as well as model. Signed-off-by: Tony Luck Acked-by: Hans de Goede --- arch/x86/events/intel/pt.c | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/arch/x86/events/intel/pt.c b/arch/x86/events/intel/pt.c index 8e2a12235e62..14db6d9d318b 100644 --- a/arch/x86/events/intel/pt.c +++ b/arch/x86/events/intel/pt.c @@ -22,7 +22,7 @@ #include #include #include -#include +#include =20 #include "../perf_event.h" #include "pt.h" @@ -211,11 +211,11 @@ static int __init pt_pmu_hw_init(void) } =20 /* model-specific quirks */ - switch (boot_cpu_data.x86_model) { - case INTEL_FAM6_BROADWELL: - case INTEL_FAM6_BROADWELL_D: - case INTEL_FAM6_BROADWELL_G: - case INTEL_FAM6_BROADWELL_X: + switch (boot_cpu_data.x86_vfm) { + case INTEL_BROADWELL: + case INTEL_BROADWELL_D: + case INTEL_BROADWELL_G: + case INTEL_BROADWELL_X: /* not setting BRANCH_EN will #GP, erratum BDM106 */ pt_pmu.branch_en_always_on =3D true; break; --=20 2.44.0 From nobody Sat Jul 11 15:40:01 2026 Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.18]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 8C96B17B50F; Wed, 24 Apr 2024 18:15:14 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=192.198.163.18 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1713982517; cv=none; b=gSdHEIZsjfks9Aymb2iAzjcqXjdyDpCLa3+FPaciVDM+wvdY++zDobC4D/j0MBSmG3yzYslsMH1kS1AjG5o/mCtptUAGZ6aXnzmH+kDSYlXUH0gwlyhHlDoJmuo5yT7TMsYygkLEz1P5oQqUW7kuQy1+jPRhPEigo3xOE7wfg68= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1713982517; c=relaxed/simple; bh=Zrqcnxorevl79WD5a/tmkln4E0tHA8stgjX1kIXjdB8=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=Vn0LeJJOtnh679hKNHOp8l30Jqvy9Es9GL3eLlAo5OymWzRlj+FcBAf33qZ181Sz9wZmWQID7u8W0xgRj/aHabbmoW5ulaQ53ELne3kZuK0PA4aC00DWvcmd8a11Pxr0HxBeGzE+YHDJEBAYCbc2lX+mhos9Iji9BTBAJ8ByfGU= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com; spf=pass smtp.mailfrom=intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=NoyK8df7; arc=none smtp.client-ip=192.198.163.18 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="NoyK8df7" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1713982514; x=1745518514; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=Zrqcnxorevl79WD5a/tmkln4E0tHA8stgjX1kIXjdB8=; b=NoyK8df7E5C6JCHHjgNIHHjSOStYRy7j528bH9hYqID16CWBMSSjdV6a t8d5R+orxklM66nwqh7nbI4+97jwiwgXmPj/28IegbCqZNHBvK92eBc+I 9atSWMcLaFySjN6PMUrXSPFv9ccdk5wyxW+Q7Oz9fgqcPDjGQ3sbX0f9n dxtSA+3shM0TolxqnJ8VoGcbtQ9LFyvaD2PxvVfTPFEk1T3YLR/6mDG12 wLSOCyWOhAk90oJ8vwZK4Kj9AA1HwQfXll8kDe8RcssCzRuObE2CvtNP1 nhKPKgA7t5zjwZysmjy3pQCXukKyknm1bEJbB4noriQdqrT3qgtGtUilo w==; X-CSE-ConnectionGUID: YojkRM08TxmtuWDSCzBpDA== X-CSE-MsgGUID: G5ZUDj5FT5mQF8g+ZRZO2w== X-IronPort-AV: E=McAfee;i="6600,9927,11054"; a="9481886" X-IronPort-AV: E=Sophos;i="6.07,226,1708416000"; d="scan'208";a="9481886" Received: from fmviesa005.fm.intel.com ([10.60.135.145]) by fmvoesa112.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 24 Apr 2024 11:15:02 -0700 X-CSE-ConnectionGUID: UhT24RloQQ2FKtN6GSrxcQ== X-CSE-MsgGUID: Zm4sH1dvTR+Kxlzbs3dkDw== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.07,226,1708416000"; d="scan'208";a="29262655" Received: from agluck-desk3.sc.intel.com ([172.25.222.105]) by fmviesa005-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 24 Apr 2024 11:15:02 -0700 From: Tony Luck To: Borislav Petkov , Thomas Gleixner , Dave Hansen , x86@kernel.org Cc: Peter Zijlstra , Ingo Molnar , Arnaldo Carvalho de Melo , Namhyung Kim , Mark Rutland , Alexander Shishkin , Jiri Olsa , Ian Rogers , Adrian Hunter , "H. Peter Anvin" , linux-perf-users@vger.kernel.org, linux-kernel@vger.kernel.org, patches@lists.linux.dev, Tony Luck Subject: [PATCH v4 21/71] perf/x86/intel/uncore: Switch to new Intel CPU model defines Date: Wed, 24 Apr 2024 11:15:01 -0700 Message-ID: <20240424181501.41557-1-tony.luck@intel.com> X-Mailer: git-send-email 2.44.0 In-Reply-To: <20240424181245.41141-1-tony.luck@intel.com> References: <20240424181245.41141-1-tony.luck@intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" New CPU #defines encode vendor and family as well as model. Signed-off-by: Tony Luck Acked-by: Hans de Goede --- arch/x86/events/intel/uncore.c | 100 ++++++++++++++++----------------- 1 file changed, 50 insertions(+), 50 deletions(-) diff --git a/arch/x86/events/intel/uncore.c b/arch/x86/events/intel/uncore.c index 258e2cdf28fa..419c517b8594 100644 --- a/arch/x86/events/intel/uncore.c +++ b/arch/x86/events/intel/uncore.c @@ -1829,56 +1829,56 @@ static const struct intel_uncore_init_fun generic_u= ncore_init __initconst =3D { }; =20 static const struct x86_cpu_id intel_uncore_match[] __initconst =3D { - X86_MATCH_INTEL_FAM6_MODEL(NEHALEM_EP, &nhm_uncore_init), - X86_MATCH_INTEL_FAM6_MODEL(NEHALEM, &nhm_uncore_init), - X86_MATCH_INTEL_FAM6_MODEL(WESTMERE, &nhm_uncore_init), - X86_MATCH_INTEL_FAM6_MODEL(WESTMERE_EP, &nhm_uncore_init), - X86_MATCH_INTEL_FAM6_MODEL(SANDYBRIDGE, &snb_uncore_init), - X86_MATCH_INTEL_FAM6_MODEL(IVYBRIDGE, &ivb_uncore_init), - X86_MATCH_INTEL_FAM6_MODEL(HASWELL, &hsw_uncore_init), - X86_MATCH_INTEL_FAM6_MODEL(HASWELL_L, &hsw_uncore_init), - X86_MATCH_INTEL_FAM6_MODEL(HASWELL_G, &hsw_uncore_init), - X86_MATCH_INTEL_FAM6_MODEL(BROADWELL, &bdw_uncore_init), - X86_MATCH_INTEL_FAM6_MODEL(BROADWELL_G, &bdw_uncore_init), - X86_MATCH_INTEL_FAM6_MODEL(SANDYBRIDGE_X, &snbep_uncore_init), - X86_MATCH_INTEL_FAM6_MODEL(NEHALEM_EX, &nhmex_uncore_init), - X86_MATCH_INTEL_FAM6_MODEL(WESTMERE_EX, &nhmex_uncore_init), - X86_MATCH_INTEL_FAM6_MODEL(IVYBRIDGE_X, &ivbep_uncore_init), - X86_MATCH_INTEL_FAM6_MODEL(HASWELL_X, &hswep_uncore_init), - X86_MATCH_INTEL_FAM6_MODEL(BROADWELL_X, &bdx_uncore_init), - X86_MATCH_INTEL_FAM6_MODEL(BROADWELL_D, &bdx_uncore_init), - X86_MATCH_INTEL_FAM6_MODEL(XEON_PHI_KNL, &knl_uncore_init), - X86_MATCH_INTEL_FAM6_MODEL(XEON_PHI_KNM, &knl_uncore_init), - X86_MATCH_INTEL_FAM6_MODEL(SKYLAKE, &skl_uncore_init), - X86_MATCH_INTEL_FAM6_MODEL(SKYLAKE_L, &skl_uncore_init), - X86_MATCH_INTEL_FAM6_MODEL(SKYLAKE_X, &skx_uncore_init), - X86_MATCH_INTEL_FAM6_MODEL(KABYLAKE_L, &skl_uncore_init), - X86_MATCH_INTEL_FAM6_MODEL(KABYLAKE, &skl_uncore_init), - X86_MATCH_INTEL_FAM6_MODEL(COMETLAKE_L, &skl_uncore_init), - X86_MATCH_INTEL_FAM6_MODEL(COMETLAKE, &skl_uncore_init), - X86_MATCH_INTEL_FAM6_MODEL(ICELAKE_L, &icl_uncore_init), - X86_MATCH_INTEL_FAM6_MODEL(ICELAKE_NNPI, &icl_uncore_init), - X86_MATCH_INTEL_FAM6_MODEL(ICELAKE, &icl_uncore_init), - X86_MATCH_INTEL_FAM6_MODEL(ICELAKE_D, &icx_uncore_init), - X86_MATCH_INTEL_FAM6_MODEL(ICELAKE_X, &icx_uncore_init), - X86_MATCH_INTEL_FAM6_MODEL(TIGERLAKE_L, &tgl_l_uncore_init), - X86_MATCH_INTEL_FAM6_MODEL(TIGERLAKE, &tgl_uncore_init), - X86_MATCH_INTEL_FAM6_MODEL(ROCKETLAKE, &rkl_uncore_init), - X86_MATCH_INTEL_FAM6_MODEL(ALDERLAKE, &adl_uncore_init), - X86_MATCH_INTEL_FAM6_MODEL(ALDERLAKE_L, &adl_uncore_init), - X86_MATCH_INTEL_FAM6_MODEL(RAPTORLAKE, &adl_uncore_init), - X86_MATCH_INTEL_FAM6_MODEL(RAPTORLAKE_P, &adl_uncore_init), - X86_MATCH_INTEL_FAM6_MODEL(RAPTORLAKE_S, &adl_uncore_init), - X86_MATCH_INTEL_FAM6_MODEL(METEORLAKE, &mtl_uncore_init), - X86_MATCH_INTEL_FAM6_MODEL(METEORLAKE_L, &mtl_uncore_init), - X86_MATCH_INTEL_FAM6_MODEL(SAPPHIRERAPIDS_X, &spr_uncore_init), - X86_MATCH_INTEL_FAM6_MODEL(EMERALDRAPIDS_X, &spr_uncore_init), - X86_MATCH_INTEL_FAM6_MODEL(GRANITERAPIDS_X, &gnr_uncore_init), - X86_MATCH_INTEL_FAM6_MODEL(GRANITERAPIDS_D, &gnr_uncore_init), - X86_MATCH_INTEL_FAM6_MODEL(ATOM_TREMONT_D, &snr_uncore_init), - X86_MATCH_INTEL_FAM6_MODEL(ATOM_GRACEMONT, &adl_uncore_init), - X86_MATCH_INTEL_FAM6_MODEL(ATOM_CRESTMONT_X, &gnr_uncore_init), - X86_MATCH_INTEL_FAM6_MODEL(ATOM_CRESTMONT, &gnr_uncore_init), + X86_MATCH_VFM(INTEL_NEHALEM_EP, &nhm_uncore_init), + X86_MATCH_VFM(INTEL_NEHALEM, &nhm_uncore_init), + X86_MATCH_VFM(INTEL_WESTMERE, &nhm_uncore_init), + X86_MATCH_VFM(INTEL_WESTMERE_EP, &nhm_uncore_init), + X86_MATCH_VFM(INTEL_SANDYBRIDGE, &snb_uncore_init), + X86_MATCH_VFM(INTEL_IVYBRIDGE, &ivb_uncore_init), + X86_MATCH_VFM(INTEL_HASWELL, &hsw_uncore_init), + X86_MATCH_VFM(INTEL_HASWELL_L, &hsw_uncore_init), + X86_MATCH_VFM(INTEL_HASWELL_G, &hsw_uncore_init), + X86_MATCH_VFM(INTEL_BROADWELL, &bdw_uncore_init), + X86_MATCH_VFM(INTEL_BROADWELL_G, &bdw_uncore_init), + X86_MATCH_VFM(INTEL_SANDYBRIDGE_X, &snbep_uncore_init), + X86_MATCH_VFM(INTEL_NEHALEM_EX, &nhmex_uncore_init), + X86_MATCH_VFM(INTEL_WESTMERE_EX, &nhmex_uncore_init), + X86_MATCH_VFM(INTEL_IVYBRIDGE_X, &ivbep_uncore_init), + X86_MATCH_VFM(INTEL_HASWELL_X, &hswep_uncore_init), + X86_MATCH_VFM(INTEL_BROADWELL_X, &bdx_uncore_init), + X86_MATCH_VFM(INTEL_BROADWELL_D, &bdx_uncore_init), + X86_MATCH_VFM(INTEL_XEON_PHI_KNL, &knl_uncore_init), + X86_MATCH_VFM(INTEL_XEON_PHI_KNM, &knl_uncore_init), + X86_MATCH_VFM(INTEL_SKYLAKE, &skl_uncore_init), + X86_MATCH_VFM(INTEL_SKYLAKE_L, &skl_uncore_init), + X86_MATCH_VFM(INTEL_SKYLAKE_X, &skx_uncore_init), + X86_MATCH_VFM(INTEL_KABYLAKE_L, &skl_uncore_init), + X86_MATCH_VFM(INTEL_KABYLAKE, &skl_uncore_init), + X86_MATCH_VFM(INTEL_COMETLAKE_L, &skl_uncore_init), + X86_MATCH_VFM(INTEL_COMETLAKE, &skl_uncore_init), + X86_MATCH_VFM(INTEL_ICELAKE_L, &icl_uncore_init), + X86_MATCH_VFM(INTEL_ICELAKE_NNPI, &icl_uncore_init), + X86_MATCH_VFM(INTEL_ICELAKE, &icl_uncore_init), + X86_MATCH_VFM(INTEL_ICELAKE_D, &icx_uncore_init), + X86_MATCH_VFM(INTEL_ICELAKE_X, &icx_uncore_init), + X86_MATCH_VFM(INTEL_TIGERLAKE_L, &tgl_l_uncore_init), + X86_MATCH_VFM(INTEL_TIGERLAKE, &tgl_uncore_init), + X86_MATCH_VFM(INTEL_ROCKETLAKE, &rkl_uncore_init), + X86_MATCH_VFM(INTEL_ALDERLAKE, &adl_uncore_init), + X86_MATCH_VFM(INTEL_ALDERLAKE_L, &adl_uncore_init), + X86_MATCH_VFM(INTEL_RAPTORLAKE, &adl_uncore_init), + X86_MATCH_VFM(INTEL_RAPTORLAKE_P, &adl_uncore_init), + X86_MATCH_VFM(INTEL_RAPTORLAKE_S, &adl_uncore_init), + X86_MATCH_VFM(INTEL_METEORLAKE, &mtl_uncore_init), + X86_MATCH_VFM(INTEL_METEORLAKE_L, &mtl_uncore_init), + X86_MATCH_VFM(INTEL_SAPPHIRERAPIDS_X, &spr_uncore_init), + X86_MATCH_VFM(INTEL_EMERALDRAPIDS_X, &spr_uncore_init), + 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Peter Anvin" , linux-perf-users@vger.kernel.org, linux-kernel@vger.kernel.org, patches@lists.linux.dev, Tony Luck Subject: [PATCH v4 22/71] perf/x86/intel/uncore: Switch to new Intel CPU model defines Date: Wed, 24 Apr 2024 11:15:02 -0700 Message-ID: <20240424181502.41576-1-tony.luck@intel.com> X-Mailer: git-send-email 2.44.0 In-Reply-To: <20240424181245.41141-1-tony.luck@intel.com> References: <20240424181245.41141-1-tony.luck@intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" New CPU #defines encode vendor and family as well as model. Signed-off-by: Tony Luck Acked-by: Hans de Goede --- arch/x86/events/intel/uncore_nhmex.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/arch/x86/events/intel/uncore_nhmex.c b/arch/x86/events/intel/u= ncore_nhmex.c index 92da8aaa5966..466833478e81 100644 --- a/arch/x86/events/intel/uncore_nhmex.c +++ b/arch/x86/events/intel/uncore_nhmex.c @@ -1,5 +1,6 @@ // SPDX-License-Identifier: GPL-2.0 /* Nehalem-EX/Westmere-EX uncore support */ +#include #include "uncore.h" =20 /* NHM-EX event control */ @@ -1217,7 +1218,7 @@ static struct intel_uncore_type *nhmex_msr_uncores[] = =3D { =20 void nhmex_uncore_cpu_init(void) { - if (boot_cpu_data.x86_model =3D=3D 46) + if (boot_cpu_data.x86_vfm =3D=3D INTEL_NEHALEM_EX) uncore_nhmex =3D true; else nhmex_uncore_mbox.event_descs =3D wsmex_uncore_mbox_events; --=20 2.44.0 From nobody Sat Jul 11 15:40:01 2026 Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.18]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 6781216E867; Wed, 24 Apr 2024 18:15:15 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=192.198.163.18 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1713982517; cv=none; b=E1e+wQ12rbHrvccRP0tL/Z6SWPtGVIVvkirsvtQ+mOgq1kcev0HRmgd97T7pAOPwSip0BPADZcDATHLoZDDJYqI6pbOXChvrT260AqLGZRV8Tdhf/7tg6gZ1amiUj9aRWB9UbxPNo8Gq9LPGyXbf/jeh7Bp8gQkQ6/17qo4sYBM= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1713982517; c=relaxed/simple; bh=SHMkDQNhLJVSbQAhNMfggf+iNz/SzZPr73nQsNDr5PA=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=Vprs2tUBQzgGKXM/kTNCgYFk9FQYI0CjXpzMd0g8NeEk2xPpl7+86d5Xt6Igu6lOWAnwNPZjpDXRiH7Efa/fOz5XjoxohLKlIqCuUaiLy0kqptQMJntApWNc0ubWX5iS5r97IiKG8DQZ2nWVWqFmzbBSZ3GDsJsgFuqSbsdfxm4= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com; spf=pass smtp.mailfrom=intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=YrUrxxn3; arc=none smtp.client-ip=192.198.163.18 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="YrUrxxn3" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1713982515; x=1745518515; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=SHMkDQNhLJVSbQAhNMfggf+iNz/SzZPr73nQsNDr5PA=; b=YrUrxxn3bcYLL8CbEvIKW3HCgUaQLWiXCFdmiWqtu4dHNtNHKz/7LDKF ZgbZDq546g6CpCOYWkn7XageiRym5bIGa0pww/eOiIwtHHtuz8Aneu+CQ 7OqL/Sgf4BNABHlro/GLu0llsxsAamdLeQHSXRqyVlMRgJ9U6wu7HX3oN bVps4DVRI0GCpu6aNBuDBvE9xrkHnAmofvza4vs4txrEI1PZ+4iGUL8xc woY00Ve6ZTEwVHMZXESftFeRtW8upwARtB5FJdX1cLH5Xy6/MRYgQJoQH MCs3eDZVEfRTSzg3CLpgvxV0kkJVmS2Cs7GtWDNqFevuYZHc9sVAmxwdc g==; X-CSE-ConnectionGUID: pFoDfiQpRxaMEX5YGFju7g== X-CSE-MsgGUID: 7ChaOaaASLGPttqQQKMhkQ== X-IronPort-AV: E=McAfee;i="6600,9927,11054"; a="9481907" X-IronPort-AV: E=Sophos;i="6.07,226,1708416000"; d="scan'208";a="9481907" Received: from fmviesa005.fm.intel.com ([10.60.135.145]) by fmvoesa112.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 24 Apr 2024 11:15:03 -0700 X-CSE-ConnectionGUID: Pz7yq/wzTuOGL2Mza7wa0g== X-CSE-MsgGUID: jApYVrXOTnujTNkAikv0Lw== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.07,226,1708416000"; d="scan'208";a="29262668" Received: from agluck-desk3.sc.intel.com ([172.25.222.105]) by fmviesa005-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 24 Apr 2024 11:15:03 -0700 From: Tony Luck To: Borislav Petkov , Thomas Gleixner , Dave Hansen , x86@kernel.org Cc: Peter Zijlstra , Ingo Molnar , Arnaldo Carvalho de Melo , Namhyung Kim , Mark Rutland , Alexander Shishkin , Jiri Olsa , Ian Rogers , Adrian Hunter , "H. Peter Anvin" , linux-perf-users@vger.kernel.org, linux-kernel@vger.kernel.org, patches@lists.linux.dev, Tony Luck Subject: [PATCH v4 23/71] perf/x86/intel/uncore: Switch to new Intel CPU model defines Date: Wed, 24 Apr 2024 11:15:03 -0700 Message-ID: <20240424181503.41595-1-tony.luck@intel.com> X-Mailer: git-send-email 2.44.0 In-Reply-To: <20240424181245.41141-1-tony.luck@intel.com> References: <20240424181245.41141-1-tony.luck@intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" New CPU #defines encode vendor and family as well as model. Signed-off-by: Tony Luck Acked-by: Hans de Goede --- arch/x86/events/intel/uncore_snbep.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/arch/x86/events/intel/uncore_snbep.c b/arch/x86/events/intel/u= ncore_snbep.c index 2eaf0f339849..74b8b21e8990 100644 --- a/arch/x86/events/intel/uncore_snbep.c +++ b/arch/x86/events/intel/uncore_snbep.c @@ -1,5 +1,6 @@ // SPDX-License-Identifier: GPL-2.0 /* SandyBridge-EP/IvyTown uncore support */ +#include #include "uncore.h" #include "uncore_discovery.h" =20 @@ -3285,7 +3286,7 @@ void bdx_uncore_cpu_init(void) uncore_msr_uncores =3D bdx_msr_uncores; =20 /* Detect systems with no SBOXes */ - if ((boot_cpu_data.x86_model =3D=3D 86) || hswep_has_limit_sbox(BDX_PCU_D= ID)) + if (boot_cpu_data.x86_vfm =3D=3D INTEL_BROADWELL_D || hswep_has_limit_sbo= x(BDX_PCU_DID)) uncore_msr_uncores[BDX_MSR_UNCORE_SBOX] =3D NULL; =20 hswep_uncore_pcu.constraints =3D bdx_uncore_pcu_constraints; @@ -5394,7 +5395,7 @@ static int icx_iio_get_topology(struct intel_uncore_t= ype *type) static void icx_iio_set_mapping(struct intel_uncore_type *type) { /* Detect ICX-D system. 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Peter Anvin" , linux-perf-users@vger.kernel.org, linux-kernel@vger.kernel.org, patches@lists.linux.dev, Tony Luck Subject: [PATCH v4 24/71] perf/x86/msr: Switch to new Intel CPU model defines Date: Wed, 24 Apr 2024 11:15:03 -0700 Message-ID: <20240424181503.41614-1-tony.luck@intel.com> X-Mailer: git-send-email 2.44.0 In-Reply-To: <20240424181245.41141-1-tony.luck@intel.com> References: <20240424181245.41141-1-tony.luck@intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" New CPU #defines encode vendor and family as well as model. Signed-off-by: Tony Luck Acked-by: Hans de Goede --- arch/x86/events/msr.c | 132 +++++++++++++++++++++--------------------- 1 file changed, 66 insertions(+), 66 deletions(-) diff --git a/arch/x86/events/msr.c b/arch/x86/events/msr.c index 9e237b30f017..45b1866ff051 100644 --- a/arch/x86/events/msr.c +++ b/arch/x86/events/msr.c @@ -2,7 +2,7 @@ #include #include #include -#include +#include #include "probe.h" =20 enum perf_msr_id { @@ -43,75 +43,75 @@ static bool test_intel(int idx, void *data) boot_cpu_data.x86 !=3D 6) return false; =20 - switch (boot_cpu_data.x86_model) { - case INTEL_FAM6_NEHALEM: - case INTEL_FAM6_NEHALEM_G: - case INTEL_FAM6_NEHALEM_EP: - case INTEL_FAM6_NEHALEM_EX: - - case INTEL_FAM6_WESTMERE: - case INTEL_FAM6_WESTMERE_EP: - case INTEL_FAM6_WESTMERE_EX: - - case INTEL_FAM6_SANDYBRIDGE: - case INTEL_FAM6_SANDYBRIDGE_X: - - case INTEL_FAM6_IVYBRIDGE: - case INTEL_FAM6_IVYBRIDGE_X: - - case INTEL_FAM6_HASWELL: - case INTEL_FAM6_HASWELL_X: - case INTEL_FAM6_HASWELL_L: - case INTEL_FAM6_HASWELL_G: - - case INTEL_FAM6_BROADWELL: - case INTEL_FAM6_BROADWELL_D: - case INTEL_FAM6_BROADWELL_G: - case INTEL_FAM6_BROADWELL_X: - case INTEL_FAM6_SAPPHIRERAPIDS_X: - case INTEL_FAM6_EMERALDRAPIDS_X: - case INTEL_FAM6_GRANITERAPIDS_X: - case INTEL_FAM6_GRANITERAPIDS_D: - - case INTEL_FAM6_ATOM_SILVERMONT: - case INTEL_FAM6_ATOM_SILVERMONT_D: - case INTEL_FAM6_ATOM_AIRMONT: - - case INTEL_FAM6_ATOM_GOLDMONT: - case INTEL_FAM6_ATOM_GOLDMONT_D: - case INTEL_FAM6_ATOM_GOLDMONT_PLUS: - case INTEL_FAM6_ATOM_TREMONT_D: - case INTEL_FAM6_ATOM_TREMONT: - case INTEL_FAM6_ATOM_TREMONT_L: - - case INTEL_FAM6_XEON_PHI_KNL: - case INTEL_FAM6_XEON_PHI_KNM: + switch (boot_cpu_data.x86_vfm) { + case INTEL_NEHALEM: + case INTEL_NEHALEM_G: + case INTEL_NEHALEM_EP: + case INTEL_NEHALEM_EX: + + case INTEL_WESTMERE: + case INTEL_WESTMERE_EP: + case INTEL_WESTMERE_EX: + + case INTEL_SANDYBRIDGE: + case INTEL_SANDYBRIDGE_X: + + case INTEL_IVYBRIDGE: + case INTEL_IVYBRIDGE_X: + + case INTEL_HASWELL: + case INTEL_HASWELL_X: + case INTEL_HASWELL_L: + case INTEL_HASWELL_G: + + case INTEL_BROADWELL: + case INTEL_BROADWELL_D: + case INTEL_BROADWELL_G: + case INTEL_BROADWELL_X: + case INTEL_SAPPHIRERAPIDS_X: + case INTEL_EMERALDRAPIDS_X: + case INTEL_GRANITERAPIDS_X: + case INTEL_GRANITERAPIDS_D: + + case INTEL_ATOM_SILVERMONT: + case INTEL_ATOM_SILVERMONT_D: + case INTEL_ATOM_AIRMONT: + + case INTEL_ATOM_GOLDMONT: + case INTEL_ATOM_GOLDMONT_D: + case INTEL_ATOM_GOLDMONT_PLUS: + case INTEL_ATOM_TREMONT_D: + case INTEL_ATOM_TREMONT: + case INTEL_ATOM_TREMONT_L: + + case INTEL_XEON_PHI_KNL: + case INTEL_XEON_PHI_KNM: if (idx =3D=3D PERF_MSR_SMI) return true; break; =20 - case INTEL_FAM6_SKYLAKE_L: - case INTEL_FAM6_SKYLAKE: - case INTEL_FAM6_SKYLAKE_X: - case INTEL_FAM6_KABYLAKE_L: - case INTEL_FAM6_KABYLAKE: - case INTEL_FAM6_COMETLAKE_L: - case INTEL_FAM6_COMETLAKE: - case INTEL_FAM6_ICELAKE_L: - case INTEL_FAM6_ICELAKE: - case INTEL_FAM6_ICELAKE_X: - case INTEL_FAM6_ICELAKE_D: - case INTEL_FAM6_TIGERLAKE_L: - case INTEL_FAM6_TIGERLAKE: - case INTEL_FAM6_ROCKETLAKE: - case INTEL_FAM6_ALDERLAKE: - case INTEL_FAM6_ALDERLAKE_L: - case INTEL_FAM6_ATOM_GRACEMONT: - case INTEL_FAM6_RAPTORLAKE: - case INTEL_FAM6_RAPTORLAKE_P: - case INTEL_FAM6_RAPTORLAKE_S: - case INTEL_FAM6_METEORLAKE: - case INTEL_FAM6_METEORLAKE_L: + case INTEL_SKYLAKE_L: + case INTEL_SKYLAKE: + case INTEL_SKYLAKE_X: + case INTEL_KABYLAKE_L: + case INTEL_KABYLAKE: + case INTEL_COMETLAKE_L: + case INTEL_COMETLAKE: + case INTEL_ICELAKE_L: + case INTEL_ICELAKE: + case INTEL_ICELAKE_X: + case INTEL_ICELAKE_D: + case INTEL_TIGERLAKE_L: + case INTEL_TIGERLAKE: + case INTEL_ROCKETLAKE: + case INTEL_ALDERLAKE: + case INTEL_ALDERLAKE_L: + case INTEL_ATOM_GRACEMONT: + case INTEL_RAPTORLAKE: + case INTEL_RAPTORLAKE_P: + case INTEL_RAPTORLAKE_S: + case INTEL_METEORLAKE: + case INTEL_METEORLAKE_L: if (idx =3D=3D PERF_MSR_SMI || idx =3D=3D PERF_MSR_PPERF) return true; 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Peter Anvin" , "Peter Zijlstra (Intel)" , Tony Luck , linux-kernel@vger.kernel.org, patches@lists.linux.dev Subject: [PATCH v4 25/71] x86/apic: Switch to new Intel CPU model defines Date: Wed, 24 Apr 2024 11:15:04 -0700 Message-ID: <20240424181504.41634-1-tony.luck@intel.com> X-Mailer: git-send-email 2.44.0 In-Reply-To: <20240424181245.41141-1-tony.luck@intel.com> References: <20240424181245.41141-1-tony.luck@intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" New CPU #defines encode vendor and family as well as model. Signed-off-by: Tony Luck Acked-by: Hans de Goede --- arch/x86/kernel/apic/apic.c | 38 ++++++++++++++++++------------------- 1 file changed, 19 insertions(+), 19 deletions(-) diff --git a/arch/x86/kernel/apic/apic.c b/arch/x86/kernel/apic/apic.c index c342c4aa9c68..f76aaf5216f3 100644 --- a/arch/x86/kernel/apic/apic.c +++ b/arch/x86/kernel/apic/apic.c @@ -497,32 +497,32 @@ static struct clock_event_device lapic_clockevent =3D= { static DEFINE_PER_CPU(struct clock_event_device, lapic_events); =20 static const struct x86_cpu_id deadline_match[] __initconst =3D { - X86_MATCH_INTEL_FAM6_MODEL_STEPPINGS(HASWELL_X, X86_STEPPINGS(0x2, 0x2), = 0x3a), /* EP */ - X86_MATCH_INTEL_FAM6_MODEL_STEPPINGS(HASWELL_X, X86_STEPPINGS(0x4, 0x4), = 0x0f), /* EX */ + X86_MATCH_VFM_STEPPINGS(INTEL_HASWELL_X, X86_STEPPINGS(0x2, 0x2), 0x3a), = /* EP */ + X86_MATCH_VFM_STEPPINGS(INTEL_HASWELL_X, X86_STEPPINGS(0x4, 0x4), 0x0f), = /* EX */ =20 - X86_MATCH_INTEL_FAM6_MODEL( BROADWELL_X, 0x0b000020), + X86_MATCH_VFM(INTEL_BROADWELL_X, 0x0b000020), =20 - X86_MATCH_INTEL_FAM6_MODEL_STEPPINGS(BROADWELL_D, X86_STEPPINGS(0x2, 0x2)= , 0x00000011), - X86_MATCH_INTEL_FAM6_MODEL_STEPPINGS(BROADWELL_D, X86_STEPPINGS(0x3, 0x3)= , 0x0700000e), - X86_MATCH_INTEL_FAM6_MODEL_STEPPINGS(BROADWELL_D, X86_STEPPINGS(0x4, 0x4)= , 0x0f00000c), - X86_MATCH_INTEL_FAM6_MODEL_STEPPINGS(BROADWELL_D, X86_STEPPINGS(0x5, 0x5)= , 0x0e000003), + X86_MATCH_VFM_STEPPINGS(INTEL_BROADWELL_D, X86_STEPPINGS(0x2, 0x2), 0x000= 00011), + X86_MATCH_VFM_STEPPINGS(INTEL_BROADWELL_D, X86_STEPPINGS(0x3, 0x3), 0x070= 0000e), + X86_MATCH_VFM_STEPPINGS(INTEL_BROADWELL_D, X86_STEPPINGS(0x4, 0x4), 0x0f0= 0000c), + X86_MATCH_VFM_STEPPINGS(INTEL_BROADWELL_D, X86_STEPPINGS(0x5, 0x5), 0x0e0= 00003), =20 - X86_MATCH_INTEL_FAM6_MODEL_STEPPINGS(SKYLAKE_X, X86_STEPPINGS(0x3, 0x3), = 0x01000136), - X86_MATCH_INTEL_FAM6_MODEL_STEPPINGS(SKYLAKE_X, X86_STEPPINGS(0x4, 0x4), = 0x02000014), - X86_MATCH_INTEL_FAM6_MODEL_STEPPINGS(SKYLAKE_X, X86_STEPPINGS(0x5, 0xf), = 0), + X86_MATCH_VFM_STEPPINGS(INTEL_SKYLAKE_X, X86_STEPPINGS(0x3, 0x3), 0x01000= 136), + X86_MATCH_VFM_STEPPINGS(INTEL_SKYLAKE_X, X86_STEPPINGS(0x4, 0x4), 0x02000= 014), + X86_MATCH_VFM_STEPPINGS(INTEL_SKYLAKE_X, X86_STEPPINGS(0x5, 0xf), 0), =20 - X86_MATCH_INTEL_FAM6_MODEL( HASWELL, 0x22), - X86_MATCH_INTEL_FAM6_MODEL( HASWELL_L, 0x20), - X86_MATCH_INTEL_FAM6_MODEL( HASWELL_G, 0x17), + X86_MATCH_VFM(INTEL_HASWELL, 0x22), + X86_MATCH_VFM(INTEL_HASWELL_L, 0x20), + X86_MATCH_VFM(INTEL_HASWELL_G, 0x17), =20 - X86_MATCH_INTEL_FAM6_MODEL( BROADWELL, 0x25), - X86_MATCH_INTEL_FAM6_MODEL( BROADWELL_G, 0x17), + X86_MATCH_VFM(INTEL_BROADWELL, 0x25), + X86_MATCH_VFM(INTEL_BROADWELL_G, 0x17), =20 - X86_MATCH_INTEL_FAM6_MODEL( SKYLAKE_L, 0xb2), - X86_MATCH_INTEL_FAM6_MODEL( SKYLAKE, 0xb2), + X86_MATCH_VFM(INTEL_SKYLAKE_L, 0xb2), + X86_MATCH_VFM(INTEL_SKYLAKE, 0xb2), =20 - X86_MATCH_INTEL_FAM6_MODEL( KABYLAKE_L, 0x52), - X86_MATCH_INTEL_FAM6_MODEL( KABYLAKE, 0x52), + X86_MATCH_VFM(INTEL_KABYLAKE_L, 0x52), + X86_MATCH_VFM(INTEL_KABYLAKE, 0x52), =20 {}, }; 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X-CSE-ConnectionGUID: rBmmDbMGTG6+Cv74tJK0Mw== X-CSE-MsgGUID: +q6BalzHTQmXA446NkaQVQ== X-IronPort-AV: E=McAfee;i="6600,9927,11054"; a="9481943" X-IronPort-AV: E=Sophos;i="6.07,226,1708416000"; d="scan'208";a="9481943" Received: from fmviesa005.fm.intel.com ([10.60.135.145]) by fmvoesa112.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 24 Apr 2024 11:15:06 -0700 X-CSE-ConnectionGUID: Mn4Cqx1hS26PH8lQg704lQ== X-CSE-MsgGUID: d+cdyBE0SjOYHlJxgAxWNA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.07,226,1708416000"; d="scan'208";a="29262695" Received: from agluck-desk3.sc.intel.com ([172.25.222.105]) by fmviesa005-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 24 Apr 2024 11:15:06 -0700 From: Tony Luck To: Borislav Petkov , Thomas Gleixner , Ingo Molnar , Dave Hansen , x86@kernel.org Cc: "H. Peter Anvin" , Tony Luck , linux-kernel@vger.kernel.org, patches@lists.linux.dev Subject: [PATCH v4 26/71] x86/aperfmperf: Switch to new Intel CPU model defines Date: Wed, 24 Apr 2024 11:15:05 -0700 Message-ID: <20240424181505.41654-1-tony.luck@intel.com> X-Mailer: git-send-email 2.44.0 In-Reply-To: <20240424181245.41141-1-tony.luck@intel.com> References: <20240424181245.41141-1-tony.luck@intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" New CPU #defines encode vendor and family as well as model. Signed-off-by: Tony Luck Acked-by: Hans de Goede --- arch/x86/kernel/cpu/aperfmperf.c | 17 ++++++++--------- 1 file changed, 8 insertions(+), 9 deletions(-) diff --git a/arch/x86/kernel/cpu/aperfmperf.c b/arch/x86/kernel/cpu/aperfmp= erf.c index fdbb5f07448f..f9a8c7b7943f 100644 --- a/arch/x86/kernel/cpu/aperfmperf.c +++ b/arch/x86/kernel/cpu/aperfmperf.c @@ -124,25 +124,24 @@ static bool __init slv_set_max_freq_ratio(u64 *base_f= req, u64 *turbo_freq) return true; } =20 -#define X86_MATCH(model) \ - X86_MATCH_VENDOR_FAM_MODEL_FEATURE(INTEL, 6, \ - INTEL_FAM6_##model, X86_FEATURE_APERFMPERF, NULL) +#define X86_MATCH(vfm) \ + X86_MATCH_VFM_FEATURE(vfm, X86_FEATURE_APERFMPERF, NULL) =20 static const struct x86_cpu_id has_knl_turbo_ratio_limits[] __initconst = =3D { - X86_MATCH(XEON_PHI_KNL), - X86_MATCH(XEON_PHI_KNM), + X86_MATCH(INTEL_XEON_PHI_KNL), + X86_MATCH(INTEL_XEON_PHI_KNM), {} }; =20 static const struct x86_cpu_id has_skx_turbo_ratio_limits[] __initconst = =3D { - X86_MATCH(SKYLAKE_X), + X86_MATCH(INTEL_SKYLAKE_X), {} }; =20 static const struct x86_cpu_id has_glm_turbo_ratio_limits[] __initconst = =3D { - X86_MATCH(ATOM_GOLDMONT), - X86_MATCH(ATOM_GOLDMONT_D), - X86_MATCH(ATOM_GOLDMONT_PLUS), + X86_MATCH(INTEL_ATOM_GOLDMONT), + X86_MATCH(INTEL_ATOM_GOLDMONT_D), + X86_MATCH(INTEL_ATOM_GOLDMONT_PLUS), {} }; =20 --=20 2.44.0 From nobody Sat Jul 11 15:40:01 2026 Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.18]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 68F9A180A6C for ; Wed, 24 Apr 2024 18:15:19 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=192.198.163.18 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1713982521; cv=none; b=EIOm1yXagl4J6tliDbXZUmQlVcsBMX8KlBZhIkEGW0b010Y/7SDqcakYmCgi+4+wBN+xAIOa/A0C55+itwn6jen/nTR+4F+kBXlZtfjG4aghgKKCmwk89f1cGRYdC35YlslB5lzGisiHde1WgYU/gkNk3JhpAVto4eWts6CZyfk= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1713982521; c=relaxed/simple; bh=MQ97iLFFbgxQYCiSBsEDrW3R5WSpsqJ/JU/KTZPQ0ow=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=KquNf80mU471iKxNR474JVX/EhTvYl2rBXooCrqsrgaOYF1P6SLPjvyKsdQWnSh3Kt7lb6krgoMRgC/ro9siieQ+tyANSPxg1x2mZnfcLb6Q3035uowLsZKzWYHllUx/ZX0iU2+tLJkXCExeXxTb/6QtqRN2n0tD2YRNUW2iB1Q= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com; spf=pass smtp.mailfrom=intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=LlQ0WAGc; arc=none smtp.client-ip=192.198.163.18 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="LlQ0WAGc" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1713982519; x=1745518519; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=MQ97iLFFbgxQYCiSBsEDrW3R5WSpsqJ/JU/KTZPQ0ow=; b=LlQ0WAGceM6Q025F8+v87+IN1IAVZyWavmTfXwS0ssUp/2vfvaj+VEAB Oz+v+wUoXUl56ww5TamItHXf4mLEcFFNp28LtTb9GkOvU5PTed0gyu3GI CaxZu2AoJsDc6aaCV9Vj01frAGbHQcv2mZifejg8yhKeMiw8Q73eQEP7O vp81rsiZE+8i/LeHVr3OayqDTny1xpH01+lQ3+Y23Xt5Zac1nt8GQkUPR J8Clvs+ZaOiXfioyGBxLnxEK9PSlw/PsfdrmGBSilBYBNLX/rSLmxPJeF QpjTx3fTfar3fU5b01n6UR/7oTR60cy7tVZ/j+YBY84V2e7VoARQn9ke3 w==; X-CSE-ConnectionGUID: imiSScCiQM6UnnXLZGeBVQ== X-CSE-MsgGUID: YfT6z1fWT1KkF5oYLOyg8g== X-IronPort-AV: E=McAfee;i="6600,9927,11054"; a="9481950" X-IronPort-AV: E=Sophos;i="6.07,226,1708416000"; d="scan'208";a="9481950" Received: from fmviesa005.fm.intel.com ([10.60.135.145]) by fmvoesa112.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 24 Apr 2024 11:15:06 -0700 X-CSE-ConnectionGUID: NQGb3yeuSbW5JeWJ/NDD0A== X-CSE-MsgGUID: SMvjHHtTQJySvBszTAF66A== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.07,226,1708416000"; d="scan'208";a="29262700" Received: from agluck-desk3.sc.intel.com ([172.25.222.105]) by fmviesa005-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 24 Apr 2024 11:15:07 -0700 From: Tony Luck To: Borislav Petkov , Thomas Gleixner , Peter Zijlstra , Josh Poimboeuf , Ingo Molnar , Dave Hansen , x86@kernel.org Cc: Pawan Gupta , "H. Peter Anvin" , linux-kernel@vger.kernel.org, patches@lists.linux.dev, Tony Luck Subject: [PATCH v4 27/71] x86/bugs: Switch to new Intel CPU model defines Date: Wed, 24 Apr 2024 11:15:06 -0700 Message-ID: <20240424181506.41673-1-tony.luck@intel.com> X-Mailer: git-send-email 2.44.0 In-Reply-To: <20240424181245.41141-1-tony.luck@intel.com> References: <20240424181245.41141-1-tony.luck@intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" New CPU #defines encode vendor and family as well as model. Signed-off-by: Tony Luck Acked-by: Hans de Goede Acked-by: Josh Poimboeuf --- arch/x86/kernel/cpu/bugs.c | 30 +++++++++++++++--------------- 1 file changed, 15 insertions(+), 15 deletions(-) diff --git a/arch/x86/kernel/cpu/bugs.c b/arch/x86/kernel/cpu/bugs.c index ca295b0c1eee..32d86dd976c0 100644 --- a/arch/x86/kernel/cpu/bugs.c +++ b/arch/x86/kernel/cpu/bugs.c @@ -26,7 +26,7 @@ #include #include #include -#include +#include #include #include #include @@ -2390,20 +2390,20 @@ static void override_cache_bits(struct cpuinfo_x86 = *c) if (c->x86 !=3D 6) return; =20 - switch (c->x86_model) { - case INTEL_FAM6_NEHALEM: - case INTEL_FAM6_WESTMERE: - case INTEL_FAM6_SANDYBRIDGE: - case INTEL_FAM6_IVYBRIDGE: - case INTEL_FAM6_HASWELL: - case INTEL_FAM6_HASWELL_L: - case INTEL_FAM6_HASWELL_G: - case INTEL_FAM6_BROADWELL: - case INTEL_FAM6_BROADWELL_G: - case INTEL_FAM6_SKYLAKE_L: - case INTEL_FAM6_SKYLAKE: - case INTEL_FAM6_KABYLAKE_L: - case INTEL_FAM6_KABYLAKE: + switch (c->x86_vfm) { + case INTEL_NEHALEM: + case INTEL_WESTMERE: + case INTEL_SANDYBRIDGE: + case INTEL_IVYBRIDGE: + case INTEL_HASWELL: + case INTEL_HASWELL_L: + case INTEL_HASWELL_G: + case INTEL_BROADWELL: + case INTEL_BROADWELL_G: + case INTEL_SKYLAKE_L: + case INTEL_SKYLAKE: + case INTEL_KABYLAKE_L: + case INTEL_KABYLAKE: if (c->x86_cache_bits < 44) c->x86_cache_bits =3D 44; break; --=20 2.44.0 From nobody Sat Jul 11 15:40:01 2026 Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.18]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 76CAA180A72 for ; Wed, 24 Apr 2024 18:15:19 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=192.198.163.18 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1713982521; cv=none; b=D2rK4xNXcRUiDBCl5mVNkx9jczC2N1k5EB2nwkTNEoejMroPhbNlJXBFjZxC/5iWeuw25ep0TdiT1BWbbauwO1VBHfjq3+5dUZuWrRKWly6pwFi7Jd92bN4MKB5OnPK5X46w01XFW6iiNfju2jPfNpawqD1LjOiL13OmoB7Ufek= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1713982521; c=relaxed/simple; bh=C848K1VcGM5RUfjuR4WSnPG/StJg7lvXcY8k7DJPfJE=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=jE8lFiEjJqJ+FTLulnKzzXsN/agXmLlKIlOWipqMToY7w2bpwhPIK2MNPKvIzNddLgv81s224Vc0jPYdw9dwP7trO/dEKxLlzhtZp8qFNpzNOXR9dxSkW5nyO/XHlJaHQSTmAVjDgrlZ5BpOSWxxYwQ5naFLtMnNx59Z9Y5TGoE= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com; spf=pass smtp.mailfrom=intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=VOnEgCmI; arc=none smtp.client-ip=192.198.163.18 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="VOnEgCmI" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1713982519; x=1745518519; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=C848K1VcGM5RUfjuR4WSnPG/StJg7lvXcY8k7DJPfJE=; b=VOnEgCmIp8f5O5qM/11yVxtHUBox+fsPvQTzEqsycideWMH73v4yhC4d td1S3VdzM7KRxapBWgiOHUm0qn7XcO4jS/T27QfDLY/WOL9VjRbL2WryD ATNHWVgnh9elIE5Lg6owObJPiInDmlnYn7JTOVjSMMMEkPKMaD6QnSovH GRe5BMlDRe5OxbnWv9+oNhAS9a1yBEnaXtTLb02a1/3D69R2k/PeuOw/U ORdabR/xafvT/Mwmz6WmPr1ypsrjZjUuGowaHSjoCMXZmZFVtpnHcn7BT ZaeF38+3DodYt6l2lds4a4tVPpa0VISeRLW3z/iMLhNvut8L6PjpgvVuP w==; X-CSE-ConnectionGUID: zdSJYF1uQLGrymKxtmdUyQ== X-CSE-MsgGUID: CFt9FterQMC9X51VJX44Rw== X-IronPort-AV: E=McAfee;i="6600,9927,11054"; a="9481959" X-IronPort-AV: E=Sophos;i="6.07,226,1708416000"; d="scan'208";a="9481959" Received: from fmviesa005.fm.intel.com ([10.60.135.145]) by fmvoesa112.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 24 Apr 2024 11:15:08 -0700 X-CSE-ConnectionGUID: IZST3Fk6SPyfb5F5Inwqlg== X-CSE-MsgGUID: Qx5gOBl+Qbe//9evOyt44w== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.07,226,1708416000"; d="scan'208";a="29262706" Received: from agluck-desk3.sc.intel.com ([172.25.222.105]) by fmviesa005-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 24 Apr 2024 11:15:08 -0700 From: Tony Luck To: Borislav Petkov , Thomas Gleixner , Ingo Molnar , Dave Hansen , x86@kernel.org Cc: "H. Peter Anvin" , "Peter Zijlstra (Intel)" , Tony Luck , Pawan Gupta , Rick Edgecombe , Vegard Nossum , linux-kernel@vger.kernel.org, patches@lists.linux.dev Subject: [PATCH v4 28/71] x86/bugs: Switch to new Intel CPU model defines Date: Wed, 24 Apr 2024 11:15:07 -0700 Message-ID: <20240424181507.41693-1-tony.luck@intel.com> X-Mailer: git-send-email 2.44.0 In-Reply-To: <20240424181245.41141-1-tony.luck@intel.com> References: <20240424181245.41141-1-tony.luck@intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" New CPU #defines encode vendor and family as well as model. Signed-off-by: Tony Luck Acked-by: Hans de Goede Acked-by: Josh Poimboeuf --- arch/x86/kernel/cpu/common.c | 154 +++++++++++++++++------------------ 1 file changed, 76 insertions(+), 78 deletions(-) diff --git a/arch/x86/kernel/cpu/common.c b/arch/x86/kernel/cpu/common.c index 2e70827c126f..cdaa795a9371 100644 --- a/arch/x86/kernel/cpu/common.c +++ b/arch/x86/kernel/cpu/common.c @@ -114,17 +114,17 @@ static const struct x86_cpu_id ppin_cpuids[] =3D { X86_MATCH_FEATURE(X86_FEATURE_INTEL_PPIN, &ppin_info[X86_VENDOR_INTEL]), =20 /* Legacy models without CPUID enumeration */ - X86_MATCH_INTEL_FAM6_MODEL(IVYBRIDGE_X, &ppin_info[X86_VENDOR_INTEL]), - X86_MATCH_INTEL_FAM6_MODEL(HASWELL_X, &ppin_info[X86_VENDOR_INTEL]), - X86_MATCH_INTEL_FAM6_MODEL(BROADWELL_D, &ppin_info[X86_VENDOR_INTEL]), - X86_MATCH_INTEL_FAM6_MODEL(BROADWELL_X, &ppin_info[X86_VENDOR_INTEL]), - X86_MATCH_INTEL_FAM6_MODEL(SKYLAKE_X, &ppin_info[X86_VENDOR_INTEL]), - X86_MATCH_INTEL_FAM6_MODEL(ICELAKE_X, &ppin_info[X86_VENDOR_INTEL]), - X86_MATCH_INTEL_FAM6_MODEL(ICELAKE_D, &ppin_info[X86_VENDOR_INTEL]), - X86_MATCH_INTEL_FAM6_MODEL(SAPPHIRERAPIDS_X, &ppin_info[X86_VENDOR_INTEL]= ), - X86_MATCH_INTEL_FAM6_MODEL(EMERALDRAPIDS_X, &ppin_info[X86_VENDOR_INTEL]), - X86_MATCH_INTEL_FAM6_MODEL(XEON_PHI_KNL, &ppin_info[X86_VENDOR_INTEL]), - X86_MATCH_INTEL_FAM6_MODEL(XEON_PHI_KNM, &ppin_info[X86_VENDOR_INTEL]), + X86_MATCH_VFM(INTEL_IVYBRIDGE_X, &ppin_info[X86_VENDOR_INTEL]), + X86_MATCH_VFM(INTEL_HASWELL_X, &ppin_info[X86_VENDOR_INTEL]), + X86_MATCH_VFM(INTEL_BROADWELL_D, &ppin_info[X86_VENDOR_INTEL]), + X86_MATCH_VFM(INTEL_BROADWELL_X, &ppin_info[X86_VENDOR_INTEL]), + X86_MATCH_VFM(INTEL_SKYLAKE_X, &ppin_info[X86_VENDOR_INTEL]), + X86_MATCH_VFM(INTEL_ICELAKE_X, &ppin_info[X86_VENDOR_INTEL]), + X86_MATCH_VFM(INTEL_ICELAKE_D, &ppin_info[X86_VENDOR_INTEL]), + X86_MATCH_VFM(INTEL_SAPPHIRERAPIDS_X, &ppin_info[X86_VENDOR_INTEL]), + X86_MATCH_VFM(INTEL_EMERALDRAPIDS_X, &ppin_info[X86_VENDOR_INTEL]), + X86_MATCH_VFM(INTEL_XEON_PHI_KNL, &ppin_info[X86_VENDOR_INTEL]), + X86_MATCH_VFM(INTEL_XEON_PHI_KNM, &ppin_info[X86_VENDOR_INTEL]), =20 {} }; @@ -1122,8 +1122,8 @@ static void identify_cpu_without_cpuid(struct cpuinfo= _x86 *c) #define VULNWL(vendor, family, model, whitelist) \ X86_MATCH_VENDOR_FAM_MODEL(vendor, family, model, whitelist) =20 -#define VULNWL_INTEL(model, whitelist) \ - VULNWL(INTEL, 6, INTEL_FAM6_##model, whitelist) +#define VULNWL_INTEL(vfm, whitelist) \ + X86_MATCH_VFM(vfm, whitelist) =20 #define VULNWL_AMD(family, whitelist) \ VULNWL(AMD, family, X86_MODEL_ANY, whitelist) @@ -1140,32 +1140,32 @@ static const __initconst struct x86_cpu_id cpu_vuln= _whitelist[] =3D { VULNWL(VORTEX, 6, X86_MODEL_ANY, NO_SPECULATION), =20 /* Intel Family 6 */ - VULNWL_INTEL(TIGERLAKE, NO_MMIO), - VULNWL_INTEL(TIGERLAKE_L, NO_MMIO), - VULNWL_INTEL(ALDERLAKE, NO_MMIO), - VULNWL_INTEL(ALDERLAKE_L, NO_MMIO), + VULNWL_INTEL(INTEL_TIGERLAKE, NO_MMIO), + VULNWL_INTEL(INTEL_TIGERLAKE_L, NO_MMIO), + VULNWL_INTEL(INTEL_ALDERLAKE, NO_MMIO), + VULNWL_INTEL(INTEL_ALDERLAKE_L, NO_MMIO), =20 - VULNWL_INTEL(ATOM_SALTWELL, NO_SPECULATION | NO_ITLB_MULTIHIT), - VULNWL_INTEL(ATOM_SALTWELL_TABLET, NO_SPECULATION | NO_ITLB_MULTIHIT), - VULNWL_INTEL(ATOM_SALTWELL_MID, NO_SPECULATION | NO_ITLB_MULTIHIT), - VULNWL_INTEL(ATOM_BONNELL, NO_SPECULATION | NO_ITLB_MULTIHIT), - VULNWL_INTEL(ATOM_BONNELL_MID, NO_SPECULATION | NO_ITLB_MULTIHIT), + VULNWL_INTEL(INTEL_ATOM_SALTWELL, NO_SPECULATION | NO_ITLB_MULTIHIT), + VULNWL_INTEL(INTEL_ATOM_SALTWELL_TABLET, NO_SPECULATION | NO_ITLB_MULTIHI= T), + VULNWL_INTEL(INTEL_ATOM_SALTWELL_MID, NO_SPECULATION | NO_ITLB_MULTIHIT), + VULNWL_INTEL(INTEL_ATOM_BONNELL, NO_SPECULATION | NO_ITLB_MULTIHIT), + VULNWL_INTEL(INTEL_ATOM_BONNELL_MID, NO_SPECULATION | NO_ITLB_MULTIHIT), =20 - VULNWL_INTEL(ATOM_SILVERMONT, NO_SSB | NO_L1TF | MSBDS_ONLY | NO_SWAPGS = | NO_ITLB_MULTIHIT), - VULNWL_INTEL(ATOM_SILVERMONT_D, NO_SSB | NO_L1TF | MSBDS_ONLY | NO_SWAPG= S | NO_ITLB_MULTIHIT), - VULNWL_INTEL(ATOM_SILVERMONT_MID, NO_SSB | NO_L1TF | MSBDS_ONLY | NO_SWAP= GS | NO_ITLB_MULTIHIT), - VULNWL_INTEL(ATOM_AIRMONT, NO_SSB | NO_L1TF | MSBDS_ONLY | NO_SWAPGS | N= O_ITLB_MULTIHIT), - VULNWL_INTEL(XEON_PHI_KNL, NO_SSB | NO_L1TF | MSBDS_ONLY | NO_SWAPGS | N= O_ITLB_MULTIHIT), - VULNWL_INTEL(XEON_PHI_KNM, NO_SSB | NO_L1TF | MSBDS_ONLY | NO_SWAPGS | N= O_ITLB_MULTIHIT), + VULNWL_INTEL(INTEL_ATOM_SILVERMONT, NO_SSB | NO_L1TF | MSBDS_ONLY | NO_SW= APGS | NO_ITLB_MULTIHIT), + VULNWL_INTEL(INTEL_ATOM_SILVERMONT_D, NO_SSB | NO_L1TF | MSBDS_ONLY | NO_= SWAPGS | NO_ITLB_MULTIHIT), + VULNWL_INTEL(INTEL_ATOM_SILVERMONT_MID, NO_SSB | NO_L1TF | MSBDS_ONLY | N= O_SWAPGS | NO_ITLB_MULTIHIT), + VULNWL_INTEL(INTEL_ATOM_AIRMONT, NO_SSB | NO_L1TF | MSBDS_ONLY | NO_SWAPG= S | NO_ITLB_MULTIHIT), + VULNWL_INTEL(INTEL_XEON_PHI_KNL, NO_SSB | NO_L1TF | MSBDS_ONLY | NO_SWAPG= S | NO_ITLB_MULTIHIT), + VULNWL_INTEL(INTEL_XEON_PHI_KNM, NO_SSB | NO_L1TF | MSBDS_ONLY | NO_SWAPG= S | NO_ITLB_MULTIHIT), =20 - VULNWL_INTEL(CORE_YONAH, NO_SSB), + VULNWL_INTEL(INTEL_CORE_YONAH, NO_SSB), =20 - VULNWL_INTEL(ATOM_AIRMONT_MID, NO_L1TF | MSBDS_ONLY | NO_SWAPGS | NO_ITL= B_MULTIHIT), - VULNWL_INTEL(ATOM_AIRMONT_NP, NO_L1TF | NO_SWAPGS | NO_ITLB_MULTIHIT), + VULNWL_INTEL(INTEL_ATOM_AIRMONT_MID, NO_L1TF | MSBDS_ONLY | NO_SWAPGS | N= O_ITLB_MULTIHIT), + VULNWL_INTEL(INTEL_ATOM_AIRMONT_NP, NO_L1TF | NO_SWAPGS | NO_ITLB_MULTIHI= T), =20 - VULNWL_INTEL(ATOM_GOLDMONT, NO_MDS | NO_L1TF | NO_SWAPGS | NO_ITLB_MULTI= HIT | NO_MMIO), - VULNWL_INTEL(ATOM_GOLDMONT_D, NO_MDS | NO_L1TF | NO_SWAPGS | NO_ITLB_MUL= TIHIT | NO_MMIO), - VULNWL_INTEL(ATOM_GOLDMONT_PLUS, NO_MDS | NO_L1TF | NO_SWAPGS | NO_ITLB_M= ULTIHIT | NO_MMIO | NO_EIBRS_PBRSB), + VULNWL_INTEL(INTEL_ATOM_GOLDMONT, NO_MDS | NO_L1TF | NO_SWAPGS | NO_ITLB_= MULTIHIT | NO_MMIO), + VULNWL_INTEL(INTEL_ATOM_GOLDMONT_D, NO_MDS | NO_L1TF | NO_SWAPGS | NO_ITL= B_MULTIHIT | NO_MMIO), + VULNWL_INTEL(INTEL_ATOM_GOLDMONT_PLUS, NO_MDS | NO_L1TF | NO_SWAPGS | NO_= ITLB_MULTIHIT | NO_MMIO | NO_EIBRS_PBRSB), =20 /* * Technically, swapgs isn't serializing on AMD (despite it previously @@ -1175,9 +1175,9 @@ static const __initconst struct x86_cpu_id cpu_vuln_w= hitelist[] =3D { * good enough for our purposes. */ =20 - VULNWL_INTEL(ATOM_TREMONT, NO_EIBRS_PBRSB), - VULNWL_INTEL(ATOM_TREMONT_L, NO_EIBRS_PBRSB), - VULNWL_INTEL(ATOM_TREMONT_D, NO_ITLB_MULTIHIT | NO_EIBRS_PBRSB), + VULNWL_INTEL(INTEL_ATOM_TREMONT, NO_EIBRS_PBRSB), + VULNWL_INTEL(INTEL_ATOM_TREMONT_L, NO_EIBRS_PBRSB), + VULNWL_INTEL(INTEL_ATOM_TREMONT_D, NO_ITLB_MULTIHIT | NO_EIBRS_PBRSB), =20 /* AMD Family 0xf - 0x12 */ VULNWL_AMD(0x0f, NO_MELTDOWN | NO_SSB | NO_L1TF | NO_MDS | NO_SWAPGS | NO= _ITLB_MULTIHIT | NO_MMIO | NO_BHI), @@ -1198,10 +1198,8 @@ static const __initconst struct x86_cpu_id cpu_vuln_= whitelist[] =3D { #define VULNBL(vendor, family, model, blacklist) \ X86_MATCH_VENDOR_FAM_MODEL(vendor, family, model, blacklist) =20 -#define VULNBL_INTEL_STEPPINGS(model, steppings, issues) \ - X86_MATCH_VENDOR_FAM_MODEL_STEPPINGS_FEATURE(INTEL, 6, \ - INTEL_FAM6_##model, steppings, \ - X86_FEATURE_ANY, issues) +#define VULNBL_INTEL_STEPPINGS(vfm, steppings, issues) \ + X86_MATCH_VFM_STEPPINGS(vfm, steppings, issues) =20 #define VULNBL_AMD(family, blacklist) \ VULNBL(AMD, family, X86_MODEL_ANY, blacklist) @@ -1226,43 +1224,43 @@ static const __initconst struct x86_cpu_id cpu_vuln= _whitelist[] =3D { #define RFDS BIT(7) =20 static const struct x86_cpu_id cpu_vuln_blacklist[] __initconst =3D { - VULNBL_INTEL_STEPPINGS(IVYBRIDGE, X86_STEPPING_ANY, SRBDS), - VULNBL_INTEL_STEPPINGS(HASWELL, X86_STEPPING_ANY, SRBDS), - VULNBL_INTEL_STEPPINGS(HASWELL_L, X86_STEPPING_ANY, SRBDS), - VULNBL_INTEL_STEPPINGS(HASWELL_G, X86_STEPPING_ANY, SRBDS), - VULNBL_INTEL_STEPPINGS(HASWELL_X, X86_STEPPING_ANY, MMIO), - VULNBL_INTEL_STEPPINGS(BROADWELL_D, X86_STEPPING_ANY, MMIO), - VULNBL_INTEL_STEPPINGS(BROADWELL_G, X86_STEPPING_ANY, SRBDS), - VULNBL_INTEL_STEPPINGS(BROADWELL_X, X86_STEPPING_ANY, MMIO), - VULNBL_INTEL_STEPPINGS(BROADWELL, X86_STEPPING_ANY, SRBDS), - VULNBL_INTEL_STEPPINGS(SKYLAKE_X, X86_STEPPING_ANY, MMIO | RETBLEED | GD= S), - VULNBL_INTEL_STEPPINGS(SKYLAKE_L, X86_STEPPING_ANY, MMIO | RETBLEED | GD= S | SRBDS), - VULNBL_INTEL_STEPPINGS(SKYLAKE, X86_STEPPING_ANY, MMIO | RETBLEED | GDS= | SRBDS), - VULNBL_INTEL_STEPPINGS(KABYLAKE_L, X86_STEPPING_ANY, MMIO | RETBLEED | G= DS | SRBDS), - VULNBL_INTEL_STEPPINGS(KABYLAKE, X86_STEPPING_ANY, MMIO | RETBLEED | GDS= | SRBDS), - VULNBL_INTEL_STEPPINGS(CANNONLAKE_L, X86_STEPPING_ANY, RETBLEED), - VULNBL_INTEL_STEPPINGS(ICELAKE_L, X86_STEPPING_ANY, MMIO | MMIO_SBDS | R= ETBLEED | GDS), - VULNBL_INTEL_STEPPINGS(ICELAKE_D, X86_STEPPING_ANY, MMIO | GDS), - VULNBL_INTEL_STEPPINGS(ICELAKE_X, X86_STEPPING_ANY, MMIO | GDS), - VULNBL_INTEL_STEPPINGS(COMETLAKE, X86_STEPPING_ANY, MMIO | MMIO_SBDS | R= ETBLEED | GDS), - VULNBL_INTEL_STEPPINGS(COMETLAKE_L, X86_STEPPINGS(0x0, 0x0), MMIO | RETBL= EED), - VULNBL_INTEL_STEPPINGS(COMETLAKE_L, X86_STEPPING_ANY, MMIO | MMIO_SBDS |= RETBLEED | GDS), - VULNBL_INTEL_STEPPINGS(TIGERLAKE_L, X86_STEPPING_ANY, GDS), - VULNBL_INTEL_STEPPINGS(TIGERLAKE, X86_STEPPING_ANY, GDS), - VULNBL_INTEL_STEPPINGS(LAKEFIELD, X86_STEPPING_ANY, MMIO | MMIO_SBDS | R= ETBLEED), - VULNBL_INTEL_STEPPINGS(ROCKETLAKE, X86_STEPPING_ANY, MMIO | RETBLEED | G= DS), - VULNBL_INTEL_STEPPINGS(ALDERLAKE, X86_STEPPING_ANY, RFDS), - VULNBL_INTEL_STEPPINGS(ALDERLAKE_L, X86_STEPPING_ANY, RFDS), - VULNBL_INTEL_STEPPINGS(RAPTORLAKE, X86_STEPPING_ANY, RFDS), - VULNBL_INTEL_STEPPINGS(RAPTORLAKE_P, X86_STEPPING_ANY, RFDS), - VULNBL_INTEL_STEPPINGS(RAPTORLAKE_S, X86_STEPPING_ANY, RFDS), - VULNBL_INTEL_STEPPINGS(ATOM_GRACEMONT, X86_STEPPING_ANY, RFDS), - VULNBL_INTEL_STEPPINGS(ATOM_TREMONT, X86_STEPPING_ANY, MMIO | MMIO_SBDS = | RFDS), - VULNBL_INTEL_STEPPINGS(ATOM_TREMONT_D, X86_STEPPING_ANY, MMIO | RFDS), - VULNBL_INTEL_STEPPINGS(ATOM_TREMONT_L, X86_STEPPING_ANY, MMIO | MMIO_SBD= S | RFDS), - VULNBL_INTEL_STEPPINGS(ATOM_GOLDMONT, X86_STEPPING_ANY, RFDS), - VULNBL_INTEL_STEPPINGS(ATOM_GOLDMONT_D, X86_STEPPING_ANY, RFDS), - VULNBL_INTEL_STEPPINGS(ATOM_GOLDMONT_PLUS, X86_STEPPING_ANY, RFDS), + VULNBL_INTEL_STEPPINGS(INTEL_IVYBRIDGE, X86_STEPPING_ANY, SRBDS), + VULNBL_INTEL_STEPPINGS(INTEL_HASWELL, X86_STEPPING_ANY, SRBDS), + VULNBL_INTEL_STEPPINGS(INTEL_HASWELL_L, X86_STEPPING_ANY, SRBDS), + VULNBL_INTEL_STEPPINGS(INTEL_HASWELL_G, X86_STEPPING_ANY, SRBDS), + VULNBL_INTEL_STEPPINGS(INTEL_HASWELL_X, X86_STEPPING_ANY, MMIO), + VULNBL_INTEL_STEPPINGS(INTEL_BROADWELL_D, X86_STEPPING_ANY, MMIO), + VULNBL_INTEL_STEPPINGS(INTEL_BROADWELL_G, X86_STEPPING_ANY, SRBDS), + VULNBL_INTEL_STEPPINGS(INTEL_BROADWELL_X, X86_STEPPING_ANY, MMIO), + VULNBL_INTEL_STEPPINGS(INTEL_BROADWELL, X86_STEPPING_ANY, SRBDS), + VULNBL_INTEL_STEPPINGS(INTEL_SKYLAKE_X, X86_STEPPING_ANY, MMIO | RETBLE= ED | GDS), + VULNBL_INTEL_STEPPINGS(INTEL_SKYLAKE_L, X86_STEPPING_ANY, MMIO | RETBLE= ED | GDS | SRBDS), + VULNBL_INTEL_STEPPINGS(INTEL_SKYLAKE, X86_STEPPING_ANY, MMIO | RETBLEED= | GDS | SRBDS), + VULNBL_INTEL_STEPPINGS(INTEL_KABYLAKE_L, X86_STEPPING_ANY, MMIO | RETBLE= ED | GDS | SRBDS), + VULNBL_INTEL_STEPPINGS(INTEL_KABYLAKE, X86_STEPPING_ANY, MMIO | RETBLEE= D | GDS | SRBDS), + VULNBL_INTEL_STEPPINGS(INTEL_CANNONLAKE_L, X86_STEPPING_ANY, RETBLEED), + VULNBL_INTEL_STEPPINGS(INTEL_ICELAKE_L, X86_STEPPING_ANY, MMIO | MMIO_S= BDS | RETBLEED | GDS), + VULNBL_INTEL_STEPPINGS(INTEL_ICELAKE_D, X86_STEPPING_ANY, MMIO | GDS), + VULNBL_INTEL_STEPPINGS(INTEL_ICELAKE_X, X86_STEPPING_ANY, MMIO | GDS), + VULNBL_INTEL_STEPPINGS(INTEL_COMETLAKE, X86_STEPPING_ANY, MMIO | MMIO_S= BDS | RETBLEED | GDS), + VULNBL_INTEL_STEPPINGS(INTEL_COMETLAKE_L, X86_STEPPINGS(0x0, 0x0), MMIO |= RETBLEED), + VULNBL_INTEL_STEPPINGS(INTEL_COMETLAKE_L, X86_STEPPING_ANY, MMIO | MMIO_= SBDS | RETBLEED | GDS), + VULNBL_INTEL_STEPPINGS(INTEL_TIGERLAKE_L, X86_STEPPING_ANY, GDS), + VULNBL_INTEL_STEPPINGS(INTEL_TIGERLAKE, X86_STEPPING_ANY, GDS), + VULNBL_INTEL_STEPPINGS(INTEL_LAKEFIELD, X86_STEPPING_ANY, MMIO | MMIO_S= BDS | RETBLEED), + VULNBL_INTEL_STEPPINGS(INTEL_ROCKETLAKE, X86_STEPPING_ANY, MMIO | RETBLE= ED | GDS), + VULNBL_INTEL_STEPPINGS(INTEL_ALDERLAKE, X86_STEPPING_ANY, RFDS), + VULNBL_INTEL_STEPPINGS(INTEL_ALDERLAKE_L, X86_STEPPING_ANY, RFDS), + VULNBL_INTEL_STEPPINGS(INTEL_RAPTORLAKE, X86_STEPPING_ANY, RFDS), + VULNBL_INTEL_STEPPINGS(INTEL_RAPTORLAKE_P, X86_STEPPING_ANY, RFDS), + VULNBL_INTEL_STEPPINGS(INTEL_RAPTORLAKE_S, X86_STEPPING_ANY, RFDS), + VULNBL_INTEL_STEPPINGS(INTEL_ATOM_GRACEMONT, X86_STEPPING_ANY, RFDS), + VULNBL_INTEL_STEPPINGS(INTEL_ATOM_TREMONT, X86_STEPPING_ANY, MMIO | MMIO= _SBDS | RFDS), + VULNBL_INTEL_STEPPINGS(INTEL_ATOM_TREMONT_D, X86_STEPPING_ANY, MMIO | RF= DS), + VULNBL_INTEL_STEPPINGS(INTEL_ATOM_TREMONT_L, X86_STEPPING_ANY, MMIO | MM= IO_SBDS | RFDS), + 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X-CSE-ConnectionGUID: kGcKGbeRS3WEgqFr7qlN2w== X-CSE-MsgGUID: uIBjtiY+SiivX3hEFuKguA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.07,226,1708416000"; d="scan'208";a="29262718" Received: from agluck-desk3.sc.intel.com ([172.25.222.105]) by fmviesa005-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 24 Apr 2024 11:15:09 -0700 From: Tony Luck To: Borislav Petkov , Thomas Gleixner , Ingo Molnar , Dave Hansen , x86@kernel.org Cc: "H. Peter Anvin" , Luis Chamberlain , Paolo Bonzini , Ashok Raj , Bingsong Si , Tony Luck , linux-kernel@vger.kernel.org, patches@lists.linux.dev Subject: [PATCH v4 29/71] x86/cpu/intel: Switch to new Intel CPU model defines Date: Wed, 24 Apr 2024 11:15:08 -0700 Message-ID: <20240424181508.41713-1-tony.luck@intel.com> X-Mailer: git-send-email 2.44.0 In-Reply-To: <20240424181245.41141-1-tony.luck@intel.com> References: <20240424181245.41141-1-tony.luck@intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" New CPU #defines encode vendor and family as well as model. Signed-off-by: Tony Luck Acked-by: Hans de Goede --- arch/x86/kernel/cpu/intel.c | 115 +++++++++++++++++++----------------- 1 file changed, 60 insertions(+), 55 deletions(-) diff --git a/arch/x86/kernel/cpu/intel.c b/arch/x86/kernel/cpu/intel.c index 3c3e7e5695ba..b85afd5d6128 100644 --- a/arch/x86/kernel/cpu/intel.c +++ b/arch/x86/kernel/cpu/intel.c @@ -72,19 +72,19 @@ static bool cpu_model_supports_sld __ro_after_init; */ static void check_memory_type_self_snoop_errata(struct cpuinfo_x86 *c) { - switch (c->x86_model) { - case INTEL_FAM6_CORE_YONAH: - case INTEL_FAM6_CORE2_MEROM: - case INTEL_FAM6_CORE2_MEROM_L: - case INTEL_FAM6_CORE2_PENRYN: - case INTEL_FAM6_CORE2_DUNNINGTON: - case INTEL_FAM6_NEHALEM: - case INTEL_FAM6_NEHALEM_G: - case INTEL_FAM6_NEHALEM_EP: - case INTEL_FAM6_NEHALEM_EX: - case INTEL_FAM6_WESTMERE: - case INTEL_FAM6_WESTMERE_EP: - case INTEL_FAM6_SANDYBRIDGE: + switch (c->x86_vfm) { + case INTEL_CORE_YONAH: + case INTEL_CORE2_MEROM: + case INTEL_CORE2_MEROM_L: + case INTEL_CORE2_PENRYN: + case INTEL_CORE2_DUNNINGTON: + case INTEL_NEHALEM: + case INTEL_NEHALEM_G: + case INTEL_NEHALEM_EP: + case INTEL_NEHALEM_EX: + case INTEL_WESTMERE: + case INTEL_WESTMERE_EP: + case INTEL_SANDYBRIDGE: setup_clear_cpu_cap(X86_FEATURE_SELFSNOOP); } } @@ -106,9 +106,9 @@ static void probe_xeon_phi_r3mwait(struct cpuinfo_x86 *= c) */ if (c->x86 !=3D 6) return; - switch (c->x86_model) { - case INTEL_FAM6_XEON_PHI_KNL: - case INTEL_FAM6_XEON_PHI_KNM: + switch (c->x86_vfm) { + case INTEL_XEON_PHI_KNL: + case INTEL_XEON_PHI_KNM: break; default: return; @@ -134,34 +134,41 @@ static void probe_xeon_phi_r3mwait(struct cpuinfo_x86= *c) * - Release note from 20180108 microcode release */ struct sku_microcode { - u8 model; + u32 vfm; u8 stepping; u32 microcode; }; static const struct sku_microcode spectre_bad_microcodes[] =3D { - { INTEL_FAM6_KABYLAKE, 0x0B, 0x80 }, - { INTEL_FAM6_KABYLAKE, 0x0A, 0x80 }, - { INTEL_FAM6_KABYLAKE, 0x09, 0x80 }, - { INTEL_FAM6_KABYLAKE_L, 0x0A, 0x80 }, - { INTEL_FAM6_KABYLAKE_L, 0x09, 0x80 }, - { INTEL_FAM6_SKYLAKE_X, 0x03, 0x0100013e }, - { INTEL_FAM6_SKYLAKE_X, 0x04, 0x0200003c }, - { INTEL_FAM6_BROADWELL, 0x04, 0x28 }, - { INTEL_FAM6_BROADWELL_G, 0x01, 0x1b }, - { INTEL_FAM6_BROADWELL_D, 0x02, 0x14 }, - { INTEL_FAM6_BROADWELL_D, 0x03, 0x07000011 }, - { INTEL_FAM6_BROADWELL_X, 0x01, 0x0b000025 }, - { INTEL_FAM6_HASWELL_L, 0x01, 0x21 }, - { INTEL_FAM6_HASWELL_G, 0x01, 0x18 }, - { INTEL_FAM6_HASWELL, 0x03, 0x23 }, - { INTEL_FAM6_HASWELL_X, 0x02, 0x3b }, - { INTEL_FAM6_HASWELL_X, 0x04, 0x10 }, - { INTEL_FAM6_IVYBRIDGE_X, 0x04, 0x42a }, + { INTEL_KABYLAKE, 0x0B, 0x80 }, + { INTEL_KABYLAKE, 0x0A, 0x80 }, + { INTEL_KABYLAKE, 0x09, 0x80 }, + { INTEL_KABYLAKE_L, 0x0A, 0x80 }, + { INTEL_KABYLAKE_L, 0x09, 0x80 }, + { INTEL_SKYLAKE_X, 0x03, 0x0100013e }, + { INTEL_SKYLAKE_X, 0x04, 0x0200003c }, + { INTEL_BROADWELL, 0x04, 0x28 }, + { INTEL_BROADWELL_G, 0x01, 0x1b }, + { INTEL_BROADWELL_D, 0x02, 0x14 }, + { INTEL_BROADWELL_D, 0x03, 0x07000011 }, + { INTEL_BROADWELL_X, 0x01, 0x0b000025 }, + { INTEL_HASWELL_L, 0x01, 0x21 }, + { INTEL_HASWELL_G, 0x01, 0x18 }, + { INTEL_HASWELL, 0x03, 0x23 }, + { INTEL_HASWELL_X, 0x02, 0x3b }, + { INTEL_HASWELL_X, 0x04, 0x10 }, + { INTEL_IVYBRIDGE_X, 0x04, 0x42a }, /* Observed in the wild */ - { INTEL_FAM6_SANDYBRIDGE_X, 0x06, 0x61b }, - { INTEL_FAM6_SANDYBRIDGE_X, 0x07, 0x712 }, + { INTEL_SANDYBRIDGE_X, 0x06, 0x61b }, + { INTEL_SANDYBRIDGE_X, 0x07, 0x712 }, }; =20 +static bool vfm_match(struct cpuinfo_x86 *c, u32 vfm) +{ + return c->x86_vendor =3D=3D VFM_VENDOR(vfm) && + c->x86 =3D=3D VFM_FAMILY(vfm) && + c->x86_model =3D=3D VFM_MODEL(vfm); +} + static bool bad_spectre_microcode(struct cpuinfo_x86 *c) { int i; @@ -173,11 +180,8 @@ static bool bad_spectre_microcode(struct cpuinfo_x86 *= c) if (cpu_has(c, X86_FEATURE_HYPERVISOR)) return false; =20 - if (c->x86 !=3D 6) - return false; - for (i =3D 0; i < ARRAY_SIZE(spectre_bad_microcodes); i++) { - if (c->x86_model =3D=3D spectre_bad_microcodes[i].model && + if (vfm_match(c, spectre_bad_microcodes[i].vfm) && c->x86_stepping =3D=3D spectre_bad_microcodes[i].stepping) return (c->microcode <=3D spectre_bad_microcodes[i].microcode); } @@ -313,7 +317,7 @@ static void early_init_intel(struct cpuinfo_x86 *c) * need the microcode to have already been loaded... so if it is * not, recommend a BIOS update and disable large pages. */ - if (c->x86 =3D=3D 6 && c->x86_model =3D=3D 0x1c && c->x86_stepping <=3D 2= && + if (c->x86_vfm =3D=3D INTEL_ATOM_BONNELL && c->x86_stepping <=3D 2 && c->microcode < 0x20e) { pr_warn("Atom PSE erratum detected, BIOS microcode update recommended\n"= ); clear_cpu_cap(c, X86_FEATURE_PSE); @@ -346,11 +350,11 @@ static void early_init_intel(struct cpuinfo_x86 *c) =20 /* Penwell and Cloverview have the TSC which doesn't sleep on S3 */ if (c->x86 =3D=3D 6) { - switch (c->x86_model) { - case INTEL_FAM6_ATOM_SALTWELL_MID: - case INTEL_FAM6_ATOM_SALTWELL_TABLET: - case INTEL_FAM6_ATOM_SILVERMONT_MID: - case INTEL_FAM6_ATOM_AIRMONT_NP: + switch (c->x86_vfm) { + case INTEL_ATOM_SALTWELL_MID: + case INTEL_ATOM_SALTWELL_TABLET: + case INTEL_ATOM_SILVERMONT_MID: + case INTEL_ATOM_AIRMONT_NP: set_cpu_cap(c, X86_FEATURE_NONSTOP_TSC_S3); break; default: @@ -394,7 +398,7 @@ static void early_init_intel(struct cpuinfo_x86 *c) * should be false so that __flush_tlb_all() causes CR3 instead of CR4.PGE * to be modified. */ - if (c->x86 =3D=3D 5 && c->x86_model =3D=3D 9) { + if (c->x86_vfm =3D=3D INTEL_QUARK_X1000) { pr_info("Disabling PGE capability bit\n"); setup_clear_cpu_cap(X86_FEATURE_PGE); } @@ -626,12 +630,13 @@ static void init_intel(struct cpuinfo_x86 *c) set_cpu_cap(c, X86_FEATURE_PEBS); } =20 - if (c->x86 =3D=3D 6 && boot_cpu_has(X86_FEATURE_CLFLUSH) && - (c->x86_model =3D=3D 29 || c->x86_model =3D=3D 46 || c->x86_model =3D= =3D 47)) + if (boot_cpu_has(X86_FEATURE_CLFLUSH) && + (c->x86_vfm =3D=3D INTEL_CORE2_DUNNINGTON || + c->x86_vfm =3D=3D INTEL_NEHALEM_EX || + c->x86_vfm =3D=3D INTEL_WESTMERE_EX)) set_cpu_bug(c, X86_BUG_CLFLUSH_MONITOR); =20 - if (c->x86 =3D=3D 6 && boot_cpu_has(X86_FEATURE_MWAIT) && - ((c->x86_model =3D=3D INTEL_FAM6_ATOM_GOLDMONT))) + if (boot_cpu_has(X86_FEATURE_MWAIT) && c->x86_vfm =3D=3D INTEL_ATOM_GOLDM= ONT) set_cpu_bug(c, X86_BUG_MONITOR); =20 #ifdef CONFIG_X86_64 @@ -1247,9 +1252,9 @@ void handle_bus_lock(struct pt_regs *regs) * feature even though they do not enumerate IA32_CORE_CAPABILITIES. */ static const struct x86_cpu_id split_lock_cpu_ids[] __initconst =3D { - X86_MATCH_INTEL_FAM6_MODEL(ICELAKE_X, 0), - X86_MATCH_INTEL_FAM6_MODEL(ICELAKE_L, 0), - X86_MATCH_INTEL_FAM6_MODEL(ICELAKE_D, 0), + X86_MATCH_VFM(INTEL_ICELAKE_X, 0), + X86_MATCH_VFM(INTEL_ICELAKE_L, 0), + X86_MATCH_VFM(INTEL_ICELAKE_D, 0), {} }; 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Peter Anvin" , "Rafael J. Wysocki" , Gavin Shan , James Morse , "Russell King (Oracle)" , Tony Luck , Peter Zijlstra , linux-kernel@vger.kernel.org, patches@lists.linux.dev Subject: [PATCH v4 30/71] x86/cpu/intel_epb: Switch to new Intel CPU model defines Date: Wed, 24 Apr 2024 11:15:09 -0700 Message-ID: <20240424181510.41733-1-tony.luck@intel.com> X-Mailer: git-send-email 2.44.0 In-Reply-To: <20240424181245.41141-1-tony.luck@intel.com> References: <20240424181245.41141-1-tony.luck@intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" New CPU #defines encode vendor and family as well as model. Signed-off-by: Tony Luck Acked-by: Hans de Goede --- arch/x86/kernel/cpu/intel_epb.c | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/arch/x86/kernel/cpu/intel_epb.c b/arch/x86/kernel/cpu/intel_ep= b.c index f18d35fe27a9..30b1d63b97f3 100644 --- a/arch/x86/kernel/cpu/intel_epb.c +++ b/arch/x86/kernel/cpu/intel_epb.c @@ -204,12 +204,12 @@ static int intel_epb_offline(unsigned int cpu) } =20 static const struct x86_cpu_id intel_epb_normal[] =3D { - X86_MATCH_INTEL_FAM6_MODEL(ALDERLAKE_L, - ENERGY_PERF_BIAS_NORMAL_POWERSAVE), - X86_MATCH_INTEL_FAM6_MODEL(ATOM_GRACEMONT, - ENERGY_PERF_BIAS_NORMAL_POWERSAVE), - X86_MATCH_INTEL_FAM6_MODEL(RAPTORLAKE_P, - ENERGY_PERF_BIAS_NORMAL_POWERSAVE), + X86_MATCH_VFM(INTEL_ALDERLAKE_L, + ENERGY_PERF_BIAS_NORMAL_POWERSAVE), + X86_MATCH_VFM(INTEL_ATOM_GRACEMONT, + ENERGY_PERF_BIAS_NORMAL_POWERSAVE), + X86_MATCH_VFM(INTEL_RAPTORLAKE_P, + ENERGY_PERF_BIAS_NORMAL_POWERSAVE), {} }; =20 --=20 2.44.0 From nobody Sat Jul 11 15:40:01 2026 Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.18]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 8878D181329 for ; Wed, 24 Apr 2024 18:15:21 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=192.198.163.18 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1713982523; cv=none; b=AvvYlM/Lp7rWSqH+tSmoqqEGh6lT/lckr+ZmoyplE6eb618gcvTcs6ie2nPFkGIMKSY1guKDjY1lLhRGr+wuYanhBKdb/UMWOAZBEgHDRtNkY2DQbEPT/1psNw5ckHATeJLbYxCWD9pRvB0oh4LpU0OJjtJUUQOutBr4y1ZreVQ= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1713982523; c=relaxed/simple; bh=PH4S/Ii609Lmbnp6CowHBve2HoFhBNoMQHmg9A/lKU0=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=HhIiJZ7DRWowSSyaKulcj45da7MoEzmpZ/vsFfpnlO5v2Bfq7MMJUTtm61mzgokNvyHWDqpsZHrjRXyTlu7EOs9qax5eufVMduhXP61b8RHbE4ImJWYz0HcTIPAlraIBv8UfzotzI6GzD/7bH1VQeSGVPNkTVL3IBCwcEOKsNRk= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com; spf=pass smtp.mailfrom=intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=WwksgWQN; arc=none smtp.client-ip=192.198.163.18 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="WwksgWQN" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1713982521; x=1745518521; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=PH4S/Ii609Lmbnp6CowHBve2HoFhBNoMQHmg9A/lKU0=; b=WwksgWQNnC992Y2n93Rnk3BhfeJfjJKYP7H8BPU0vXkOJNq1EOX5FRKC gh1hbzrvEirZ1reuBqcoW5QhZYNHdYAA1gcU1ZqL10pvn5Bz8BnXdwqAP cxcZscf1bkaqf4FODyD29hKgQcDjbITio6xjIKearVOfKgIV2d9icVpkE hfWT+unb87V41YPqXi3Pwzw67sNIUun3QPcRIwzl3GomPbY4PATvJH6lN 78gseTt1n9w5BEzE2gT4Ob9dKDsNu7wfSkknGJwZz/gfA4Klp3PDhHqSV G11ZnkfwGle8UX5o8b7MzR1jOoAWI1lN/hlXUBN2hZdcCwmkoZP4Tec6M A==; X-CSE-ConnectionGUID: Q7hwYCQaQ5qF9XKVYMGXfw== X-CSE-MsgGUID: GTPDdibGRLiZDbGXJZIfKw== X-IronPort-AV: E=McAfee;i="6600,9927,11054"; a="9481987" X-IronPort-AV: E=Sophos;i="6.07,226,1708416000"; d="scan'208";a="9481987" Received: from fmviesa005.fm.intel.com ([10.60.135.145]) by fmvoesa112.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 24 Apr 2024 11:15:11 -0700 X-CSE-ConnectionGUID: S0SzPpkVTTiK11GDlb5eIA== X-CSE-MsgGUID: y+qNwmC9SpO/79qqtW+3QQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.07,226,1708416000"; d="scan'208";a="29262738" Received: from agluck-desk3.sc.intel.com ([172.25.222.105]) by fmviesa005-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 24 Apr 2024 11:15:11 -0700 From: Tony Luck To: Borislav Petkov , Thomas Gleixner , Ingo Molnar , Dave Hansen , x86@kernel.org Cc: "H. Peter Anvin" , Tony Luck , linux-kernel@vger.kernel.org, patches@lists.linux.dev Subject: [PATCH v4 31/71] x86/cpu: Switch to new Intel CPU model defines Date: Wed, 24 Apr 2024 11:15:11 -0700 Message-ID: <20240424181511.41753-1-tony.luck@intel.com> X-Mailer: git-send-email 2.44.0 In-Reply-To: <20240424181245.41141-1-tony.luck@intel.com> References: <20240424181245.41141-1-tony.luck@intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" New CPU #defines encode vendor and family as well as model. Signed-off-by: Tony Luck Acked-by: Hans de Goede --- arch/x86/kernel/cpu/match.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/x86/kernel/cpu/match.c b/arch/x86/kernel/cpu/match.c index 2243083f0bc2..8651643bddae 100644 --- a/arch/x86/kernel/cpu/match.c +++ b/arch/x86/kernel/cpu/match.c @@ -25,7 +25,7 @@ * asm/cpu_device_id.h contains a set of useful macros which are shortcuts * for various common selections. The above can be shortened to: * - * X86_MATCH_INTEL_FAM6_MODEL(BROADWELL, NULL); + * X86_MATCH_VFM(INTEL_BROADWELL, NULL); * * Arrays used to match for this should also be declared using * MODULE_DEVICE_TABLE(x86cpu, ...) --=20 2.44.0 From nobody Sat Jul 11 15:40:01 2026 Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.18]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D4CC218133A; Wed, 24 Apr 2024 18:15:21 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=192.198.163.18 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1713982523; cv=none; b=BRP3Ys80+ls+V+WHxDQO1lX7eHZ9+rB7Vde6ow27+/o5kd5Ovv+2QYtErUPW9+Sj5xteQh6aI2QIlWDt9B7KMD0sk3qTiiLZ9AAE/2j8qDFFkDTHfPptZ7anO6+7Iu13AY2mf3xeTyDcVxEMMBZkdr2aoUN4fnf1FATfIvWt4Hk= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1713982523; c=relaxed/simple; bh=J5hiIdzXZvx6tAF17llwzadEEbvMd4HK2TJQKlWWZVo=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=FaXSCY8QBPkWwI8LopEpsyT8tBZ0tgJVdgglJFRR0h4MBogadx4fTU28dp1ZdOFoNOtLvuFxQgvTc9JEt6cqBZsLpurMeqSvOAZGo9pzC2AaNQsQ3raPt8Vfh2reJNXZEyYy8+QKhNs5ltZ8JdjbDI6fL0R9TLaQVVlBPKSONPw= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com; spf=pass smtp.mailfrom=intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=UCkIxdrn; arc=none smtp.client-ip=192.198.163.18 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="UCkIxdrn" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1713982522; x=1745518522; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=J5hiIdzXZvx6tAF17llwzadEEbvMd4HK2TJQKlWWZVo=; b=UCkIxdrnsmSKj+DzxJkQEwIKAcyqo6wsFZCiAqIxec68E7E9KJCxRCHE DDZyMOUqGJfblyU1N7aeGBfpa8fCYnXwtTsKRbvCUTZ5sPXBDD1+B+2F2 QpCwekAVzihJP6UByVRjlunpbRQoK/mxIMz41vZkD/fHamqFTeCN2R3SO G061f5cE6K7ZKUKxKvJg2BMQgN1GSAhsMq1aKbsZ38Y6Uj8htpRmMfGQL TUN9KJWNf1P2VZeC01R+CNv9y+HYhAqEOWWaIGzNCIPl6l8BmFI5x6lmB pOgJHCsWBJzVNSswVO1+FxyfWlCSyvhv1zrpcohdYX/OB3t5tOMrwBNER Q==; X-CSE-ConnectionGUID: 42oprxY3Ro2AggsFbfmsKw== X-CSE-MsgGUID: 8r4wpvh7SVeAG1HQzMzQpw== X-IronPort-AV: E=McAfee;i="6600,9927,11054"; a="9481994" X-IronPort-AV: E=Sophos;i="6.07,226,1708416000"; d="scan'208";a="9481994" Received: from fmviesa005.fm.intel.com ([10.60.135.145]) by fmvoesa112.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 24 Apr 2024 11:15:12 -0700 X-CSE-ConnectionGUID: u9kpHmymT3qBVaY3N+AmTg== X-CSE-MsgGUID: sLnf+kpDTLyA3e6CtDkmrg== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.07,226,1708416000"; d="scan'208";a="29262744" Received: from agluck-desk3.sc.intel.com ([172.25.222.105]) by fmviesa005-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 24 Apr 2024 11:15:12 -0700 From: Tony Luck To: Borislav Petkov , Tony Luck , Thomas Gleixner , Ingo Molnar , Dave Hansen , x86@kernel.org Cc: "H. Peter Anvin" , linux-edac@vger.kernel.org, linux-kernel@vger.kernel.org, patches@lists.linux.dev Subject: [PATCH v4 32/71] x86/mce: Switch to new Intel CPU model defines Date: Wed, 24 Apr 2024 11:15:11 -0700 Message-ID: <20240424181511.41772-1-tony.luck@intel.com> X-Mailer: git-send-email 2.44.0 In-Reply-To: <20240424181245.41141-1-tony.luck@intel.com> References: <20240424181245.41141-1-tony.luck@intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" New CPU #defines encode vendor and family as well as model. Signed-off-by: Tony Luck Acked-by: Hans de Goede --- arch/x86/kernel/cpu/mce/core.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/arch/x86/kernel/cpu/mce/core.c b/arch/x86/kernel/cpu/mce/core.c index 771a9f183260..ad0623b659ed 100644 --- a/arch/x86/kernel/cpu/mce/core.c +++ b/arch/x86/kernel/cpu/mce/core.c @@ -47,7 +47,7 @@ #include =20 #include -#include +#include #include #include #include @@ -1948,14 +1948,14 @@ static int __mcheck_cpu_apply_quirks(struct cpuinfo= _x86 *c) if (c->x86 =3D=3D 6 && c->x86_model <=3D 13 && cfg->bootlog < 0) cfg->bootlog =3D 0; =20 - if (c->x86 =3D=3D 6 && c->x86_model =3D=3D 45) + if (c->x86_vfm =3D=3D INTEL_SANDYBRIDGE_X) mce_flags.snb_ifu_quirk =3D 1; =20 /* * Skylake, Cascacde Lake and Cooper Lake require a quirk on * rep movs. */ - if (c->x86 =3D=3D 6 && c->x86_model =3D=3D INTEL_FAM6_SKYLAKE_X) + if (c->x86_vfm =3D=3D INTEL_SKYLAKE_X) mce_flags.skx_repmov_quirk =3D 1; } =20 --=20 2.44.0 From nobody Sat Jul 11 15:40:01 2026 Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.18]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 64CFE17F39E; Wed, 24 Apr 2024 18:15:23 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=192.198.163.18 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1713982526; cv=none; b=lwr1vIZP+J84kO2IQm5bkmMcfwXmXummkCHOA674mnuKxxy2o8sEpbdPzisqrxQuvfpN5ukjH681FyXIxCuy9kOesPvqLTm/SkGEfz8/daIMHXSNOnQ7CjFkhTTluoHbUlWK+DwN5ff8J7Oi/Ixvbd2y1Ncas7ILjLnBVMmtQOA= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1713982526; c=relaxed/simple; bh=RNT+k0vH5nyuxqu3Y+Ud1FK95n7UPRfWtbXzxwVqrV4=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=BMyCs4LVS0bC7xIJyB8m6W5hxN5wRLFDzQwNCcRZAQHFyy+WkoI8ii4c5nY5ESNeLA9xGTOdBSp5X3SqsrPsI0nnrPprZzNTLnjLAPDnCb1d2xMaz7w7RmfdvwYce0qLUi0HoUUBZWFi/3giQ4c6I1vI9dEGZ7f3f+c4PM7KeRY= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com; spf=pass smtp.mailfrom=intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=l7omLfu+; arc=none smtp.client-ip=192.198.163.18 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="l7omLfu+" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1713982523; x=1745518523; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=RNT+k0vH5nyuxqu3Y+Ud1FK95n7UPRfWtbXzxwVqrV4=; b=l7omLfu+CTStaV+Zlo0n5EfzFvQ5zfrxWgTGb45tP2qWkrMzOce/1yyF bANiIyGwgGg6TrKGwl4simkeEjo8qZTJiPFWLVy75j1Pk+ZdzCGWfwKIP jAUdy+MoQOYJJvMuemE3iyWf37XCY8CQ2s1FQtZPGQsZL5Gg5XUl6oDke Q7i4Z+DA+uOjtM1jigUuXbu99O+mIqoDdm4sIvTDCB21SLTObqZXs5U1F 98DZhSOzn0P7T4hNTvA7ArrNdnQ5zn3bx+ZMqXu5QVh47JxMqAe9WM09o ufZY9OuzeMUyMQEnpPckuR6wIExh4PLsTlsc2v4Q4Vmn18hVbskZnl0Ae g==; X-CSE-ConnectionGUID: IfrdMIN1RhmFy1jMxpYpYg== X-CSE-MsgGUID: rcpsuFpYQBOQBQw99uBcWQ== X-IronPort-AV: E=McAfee;i="6600,9927,11054"; a="9482004" X-IronPort-AV: E=Sophos;i="6.07,226,1708416000"; d="scan'208";a="9482004" Received: from fmviesa005.fm.intel.com ([10.60.135.145]) by fmvoesa112.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 24 Apr 2024 11:15:12 -0700 X-CSE-ConnectionGUID: 3N7OQ/o8SAO9NhA7ZCmJIw== X-CSE-MsgGUID: bDu9a9cXQw6s048MOIf4tQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.07,226,1708416000"; d="scan'208";a="29262748" Received: from agluck-desk3.sc.intel.com ([172.25.222.105]) by fmviesa005-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 24 Apr 2024 11:15:12 -0700 From: Tony Luck To: Borislav Petkov , Tony Luck , Thomas Gleixner , Ingo Molnar , Dave Hansen , x86@kernel.org Cc: "H. Peter Anvin" , linux-edac@vger.kernel.org, linux-kernel@vger.kernel.org, patches@lists.linux.dev Subject: [PATCH v4 33/71] x86/mce: Switch to new Intel CPU model defines Date: Wed, 24 Apr 2024 11:15:12 -0700 Message-ID: <20240424181512.41791-1-tony.luck@intel.com> X-Mailer: git-send-email 2.44.0 In-Reply-To: <20240424181245.41141-1-tony.luck@intel.com> References: <20240424181245.41141-1-tony.luck@intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" New CPU #defines encode vendor and family as well as model. Signed-off-by: Tony Luck Acked-by: Hans de Goede --- arch/x86/kernel/cpu/mce/intel.c | 21 ++++++++++----------- 1 file changed, 10 insertions(+), 11 deletions(-) diff --git a/arch/x86/kernel/cpu/mce/intel.c b/arch/x86/kernel/cpu/mce/inte= l.c index 399b62e223d2..f6103e6bf69a 100644 --- a/arch/x86/kernel/cpu/mce/intel.c +++ b/arch/x86/kernel/cpu/mce/intel.c @@ -13,7 +13,7 @@ #include #include #include -#include +#include #include #include #include @@ -455,10 +455,10 @@ static void intel_imc_init(struct cpuinfo_x86 *c) { u64 error_control; =20 - switch (c->x86_model) { - case INTEL_FAM6_SANDYBRIDGE_X: - case INTEL_FAM6_IVYBRIDGE_X: - case INTEL_FAM6_HASWELL_X: + switch (c->x86_vfm) { + case INTEL_SANDYBRIDGE_X: + case INTEL_IVYBRIDGE_X: + case INTEL_HASWELL_X: if (rdmsrl_safe(MSR_ERROR_CONTROL, &error_control)) return; error_control |=3D 2; @@ -484,12 +484,11 @@ bool intel_filter_mce(struct mce *m) struct cpuinfo_x86 *c =3D &boot_cpu_data; =20 /* MCE errata HSD131, HSM142, HSW131, BDM48, HSM142 and SKX37 */ - if ((c->x86 =3D=3D 6) && - ((c->x86_model =3D=3D INTEL_FAM6_HASWELL) || - (c->x86_model =3D=3D INTEL_FAM6_HASWELL_L) || - (c->x86_model =3D=3D INTEL_FAM6_BROADWELL) || - (c->x86_model =3D=3D INTEL_FAM6_HASWELL_G) || - (c->x86_model =3D=3D INTEL_FAM6_SKYLAKE_X)) && + if ((c->x86_vfm =3D=3D INTEL_HASWELL || + c->x86_vfm =3D=3D INTEL_HASWELL_L || + c->x86_vfm =3D=3D INTEL_BROADWELL || + c->x86_vfm =3D=3D INTEL_HASWELL_G || + c->x86_vfm =3D=3D INTEL_SKYLAKE_X) && (m->bank =3D=3D 0) && ((m->status & 0xa0000000ffffffff) =3D=3D 0x80000000000f0005)) return true; --=20 2.44.0 From nobody Sat Jul 11 15:40:01 2026 Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.18]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 6CB54181CE5; Wed, 24 Apr 2024 18:15:23 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=192.198.163.18 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1713982527; cv=none; b=sfc36+2m2TAWomfR2owIyJy2ivxxf3cvRn9OChXYJi/oGMIDH+SQ6RRu6DC7HZdS3TUbzHGikcTvbTqIIWjwj2TzR4TsImDlim+NCscoYDjta2+h7pePrQd9xdxZ7nspslBoIMtB0nbM/gArTtxL/UO72LX1LdLtTMwig6mAgR4= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1713982527; c=relaxed/simple; bh=iFfVDMwRelTPhBugxwSRQJDD52d9QsnZEZNpB2fnYgc=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=ThHv8uvXaR6kg9IhqxI5GS4w8Evm1UqdJTyoS2medeqH5ezahNsH0yEZvHN4FrvAeBxt7a4OuzjiSdshxFgTo8uEEn1fKrAV/XyfQNKUVFgsOyIbbJ4I5byUomgeo6NpRhh+6Hdsh6uO6WYe2M3NL7KVG1rBb8Djt2X26qQ/LEw= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com; spf=pass smtp.mailfrom=intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=d7Q3+AvA; arc=none smtp.client-ip=192.198.163.18 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="d7Q3+AvA" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1713982523; x=1745518523; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=iFfVDMwRelTPhBugxwSRQJDD52d9QsnZEZNpB2fnYgc=; b=d7Q3+AvATS+jKQFlPqrtfVT95NxnMkoneuGa+uX+qD4LUkT66GYFKHbN M5XzpsYCcs2aUP5HE5SdbTg75e3TOB12FGWHc87o4sL4oxXRHuBF1zXov NUNm+FwY1fuawrZL1cpdPgjYiU4P5loFJ57YykX01hWd/ItYhZcnC8Blx ZJxY2rLV9AHu0aRHmNPjLugV+euwhhqC0w2n8aIDsB6kTVxn7/fQTQHEd 3Dbjcp9f7H5shosL5V9xFVvFfRjQgsqx3Cz2o23kFqfzQRhbnzT0DoY3p kicwp+/g9E5UM2au8N3QLWaypfGKr9WQ5oBXm9VVdgAXSY0z7ej24A1hE A==; X-CSE-ConnectionGUID: ZmFasxx6SH2Uep9SNahmtg== X-CSE-MsgGUID: nia1bv8VQuKMZSm4c67G8g== X-IronPort-AV: E=McAfee;i="6600,9927,11054"; a="9482013" X-IronPort-AV: E=Sophos;i="6.07,226,1708416000"; d="scan'208";a="9482013" Received: from fmviesa005.fm.intel.com ([10.60.135.145]) by fmvoesa112.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 24 Apr 2024 11:15:13 -0700 X-CSE-ConnectionGUID: 3Me6owXQQ8yo33zZQJIkew== X-CSE-MsgGUID: hGlTsOXjSqaC+Kej4mCGHQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.07,226,1708416000"; d="scan'208";a="29262754" Received: from agluck-desk3.sc.intel.com ([172.25.222.105]) by fmviesa005-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 24 Apr 2024 11:15:13 -0700 From: Tony Luck To: Borislav Petkov , Tony Luck , Thomas Gleixner , Ingo Molnar , Dave Hansen , x86@kernel.org Cc: "H. Peter Anvin" , linux-edac@vger.kernel.org, linux-kernel@vger.kernel.org, patches@lists.linux.dev Subject: [PATCH v4 34/71] x86/mce: Switch to new Intel CPU model defines Date: Wed, 24 Apr 2024 11:15:13 -0700 Message-ID: <20240424181513.41810-1-tony.luck@intel.com> X-Mailer: git-send-email 2.44.0 In-Reply-To: <20240424181245.41141-1-tony.luck@intel.com> References: <20240424181245.41141-1-tony.luck@intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" New CPU #defines encode vendor and family as well as model. Signed-off-by: Tony Luck Acked-by: Hans de Goede --- arch/x86/kernel/cpu/mce/severity.c | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/arch/x86/kernel/cpu/mce/severity.c b/arch/x86/kernel/cpu/mce/s= everity.c index fc8988cfe1c3..7293a1c49050 100644 --- a/arch/x86/kernel/cpu/mce/severity.c +++ b/arch/x86/kernel/cpu/mce/severity.c @@ -12,7 +12,7 @@ #include =20 #include -#include +#include #include #include #include @@ -45,14 +45,14 @@ static struct severity { unsigned char context; unsigned char excp; unsigned char covered; - unsigned char cpu_model; + unsigned int cpu_vfm; unsigned char cpu_minstepping; unsigned char bank_lo, bank_hi; char *msg; } severities[] =3D { #define MCESEV(s, m, c...) { .sev =3D MCE_ ## s ## _SEVERITY, .msg =3D m, = ## c } #define BANK_RANGE(l, h) .bank_lo =3D l, .bank_hi =3D h -#define MODEL_STEPPING(m, s) .cpu_model =3D m, .cpu_minstepping =3D s +#define VFM_STEPPING(m, s) .cpu_vfm =3D m, .cpu_minstepping =3D s #define KERNEL .context =3D IN_KERNEL #define USER .context =3D IN_USER #define KERNEL_RECOV .context =3D IN_KERNEL_RECOV @@ -128,7 +128,7 @@ static struct severity { MCESEV( AO, "Uncorrected Patrol Scrub Error", SER, MASK(MCI_STATUS_UC|MCI_ADDR|0xffffeff0, MCI_ADDR|0x001000c0), - MODEL_STEPPING(INTEL_FAM6_SKYLAKE_X, 4), BANK_RANGE(13, 18) + VFM_STEPPING(INTEL_SKYLAKE_X, 4), BANK_RANGE(13, 18) ), =20 /* ignore OVER for UCNA */ @@ -398,7 +398,7 @@ static noinstr int mce_severity_intel(struct mce *m, st= ruct pt_regs *regs, char continue; if (s->excp && excp !=3D s->excp) continue; - if (s->cpu_model && boot_cpu_data.x86_model !=3D s->cpu_model) + if (s->cpu_vfm && boot_cpu_data.x86_model !=3D s->cpu_vfm) continue; if (s->cpu_minstepping && boot_cpu_data.x86_stepping < s->cpu_minsteppin= g) continue; --=20 2.44.0 From nobody Sat Jul 11 15:40:01 2026 Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.18]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B4CB2181CF8 for ; Wed, 24 Apr 2024 18:15:23 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=192.198.163.18 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1713982525; cv=none; b=qmutXNqke0mcQzZza2RPF9kWTdsMAOu4NJOJy9RgkKO2JOqmoZKOti7S11aaiY9Oex9edIvJbIBPoX8nzEY6vcCG+mZyO9Rx+Ucmk4F6gZSReyysieKurjJrx1H0Dn83nmZJS3ILN6wjyZenL6S3dSleYaU5Jr0IaJuekQsQSIM= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1713982525; c=relaxed/simple; bh=MetFmFlhAPE7vpRJ4pnmuEjVeVxyl19C3RDm5bFHSMs=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=ZC145a1rvDMVQ5N4APDCQx2RV62F/lho2q7gyGVB574wyVu2vJChY95B77WndIhvSLwN3uXAI6aAuBfpBfxBkiQ3AF1UxvXfAXgLd/04/2YzJbkvoY8VGrx/E0rIEgVh4kXUbna79Kd5+cOm3fmhN1tDVFD5bCfr1DeyJWRhnMQ= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com; spf=pass smtp.mailfrom=intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=Fl5OGbmq; arc=none smtp.client-ip=192.198.163.18 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="Fl5OGbmq" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1713982523; x=1745518523; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=MetFmFlhAPE7vpRJ4pnmuEjVeVxyl19C3RDm5bFHSMs=; b=Fl5OGbmqlIydLqeI8Viidm4TijDTbD1J4QNhWSbgCftdFjgMVzWI/kzg q42nk8OqAhV1cBrLJawantDGN0zbWuaNLV9ZLsPBwrXkm+7sS0mfBnr0a dIt2AjaLNf3iAPsFrBPTZUMciLvuIWQOH0l/8PUu/ZmFJr0SHhwiVQkIC /KTAvyVclzcW3hNeB8JSUY/iekRliGlyu9EqlY1fSOEv77wnT7T/8/UYQ 2mV/E2TsnWgO/YwMZj6PgKUN4R1pa9W6ruVfDBcsGRXrRlvG9183QjbKi QbBjHpOKRcPGCVESwSa/GyPAjnoieBfDPUl2ydXGLx78Gw82Qq/KwptL0 g==; X-CSE-ConnectionGUID: q1OIDzYERnm4luQVcvM6EA== X-CSE-MsgGUID: voberBd2RSaILcIjLVavSg== X-IronPort-AV: E=McAfee;i="6600,9927,11054"; a="9482022" X-IronPort-AV: E=Sophos;i="6.07,226,1708416000"; d="scan'208";a="9482022" Received: from fmviesa005.fm.intel.com ([10.60.135.145]) by fmvoesa112.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 24 Apr 2024 11:15:14 -0700 X-CSE-ConnectionGUID: AfJ2xFzOSQqry4fUNXU0nw== X-CSE-MsgGUID: BHJJCOJSQFefEC9GPZ5QeA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.07,226,1708416000"; d="scan'208";a="29262762" Received: from agluck-desk3.sc.intel.com ([172.25.222.105]) by fmviesa005-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 24 Apr 2024 11:15:14 -0700 From: Tony Luck To: Borislav Petkov , Thomas Gleixner , Ingo Molnar , Dave Hansen , x86@kernel.org Cc: "H. Peter Anvin" , linux-kernel@vger.kernel.org, patches@lists.linux.dev, Tony Luck Subject: [PATCH v4 35/71] x86/microcode/intel: Switch to new Intel CPU model defines Date: Wed, 24 Apr 2024 11:15:13 -0700 Message-ID: <20240424181513.41829-1-tony.luck@intel.com> X-Mailer: git-send-email 2.44.0 In-Reply-To: <20240424181245.41141-1-tony.luck@intel.com> References: <20240424181245.41141-1-tony.luck@intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" New CPU #defines encode vendor and family as well as model. Signed-off-by: Tony Luck Acked-by: Hans de Goede --- arch/x86/kernel/cpu/microcode/intel.c | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) diff --git a/arch/x86/kernel/cpu/microcode/intel.c b/arch/x86/kernel/cpu/mi= crocode/intel.c index 5f0414452b67..815fa67356a2 100644 --- a/arch/x86/kernel/cpu/microcode/intel.c +++ b/arch/x86/kernel/cpu/microcode/intel.c @@ -21,7 +21,7 @@ #include #include =20 -#include +#include #include #include #include @@ -577,8 +577,7 @@ static bool is_blacklisted(unsigned int cpu) * This behavior is documented in item BDF90, #334165 (Intel Xeon * Processor E7-8800/4800 v4 Product Family). */ - if (c->x86 =3D=3D 6 && - c->x86_model =3D=3D INTEL_FAM6_BROADWELL_X && + if (c->x86_vfm =3D=3D INTEL_BROADWELL_X && c->x86_stepping =3D=3D 0x01 && llc_size_per_core > 2621440 && c->microcode < 0x0b000021) { --=20 2.44.0 From nobody Sat Jul 11 15:40:01 2026 Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.18]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C15101836E3 for ; Wed, 24 Apr 2024 18:15:25 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=192.198.163.18 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1713982527; cv=none; b=NZfqqTupC5HtNSNgiOjQ6p02X216Znkygq+EuDHIThZcQ7MFJGE7QWe55cpRGASJ0SRfkpV4cj4bvGoDSzDElwQh2JuAXCBSeO6pVySAII0KIs+DTyhlx//6UhUgl+lHbaPi6wrJMEiYpdnyjuf2dWhzMm3hOZX+l/W/XMbN2cY= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1713982527; c=relaxed/simple; bh=rbO/n0ZcIOAgbilZJb15Crb7LJz39zrSZlFzfUY+p5o=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=LGB57w16kj+zRm/vHYjlhUjW2dnflgq0pRe9qIEZClgHNwK8zItFMQ3lozVJrxbix8oce/piIjpEwt0saXXuWLWZEK9gNHhIfLXACwXR5bZ+nmvoJIdmLlPqWiluVkEY4dJqKQMWRBZXXZF38h43+6cW4byAEjqOqu3mdN9vaSg= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com; spf=pass smtp.mailfrom=intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=U8SoRNU0; arc=none smtp.client-ip=192.198.163.18 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="U8SoRNU0" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1713982525; x=1745518525; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=rbO/n0ZcIOAgbilZJb15Crb7LJz39zrSZlFzfUY+p5o=; b=U8SoRNU0S3JcAbfUG0Rymof+sr6+YA4HsYKRflfnE1y56ahsaCZNKokK iFhyeeqyjTAg6e4jGHKJm3JRxTO/KEd4KLtkIn4M2EKmUSfD9g6n+O8dd h62+ZPfG+OW50wvA3ek02heRwfGOENU7Tz8U53nc/lFgfNC6KfEG1ZABL +JCxyqgPrPLCpdTfUYnAe9dgdJ+x1CPDu3oULxx9qYa0ossQ/2yo9Fhpz 4A54A0yQwhB/6FLB20PvyO+j34FNuBqkusgqd5krLHO2OHXhFLTTAUsw8 nSL5knNUmk9kQs9N26PO25tNqrUfCnIN4lBZw1g6iGuKVSgF03rUWWbq7 Q==; X-CSE-ConnectionGUID: NN+MYepwS36Vp14L9mDYFg== X-CSE-MsgGUID: Z2jM0IV8SJeHqwiwYzAbMw== X-IronPort-AV: E=McAfee;i="6600,9927,11054"; a="9482031" X-IronPort-AV: E=Sophos;i="6.07,226,1708416000"; d="scan'208";a="9482031" Received: from fmviesa005.fm.intel.com ([10.60.135.145]) by fmvoesa112.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 24 Apr 2024 11:15:14 -0700 X-CSE-ConnectionGUID: tbjZvTI6QoKjNbkICFGz+A== X-CSE-MsgGUID: hMpfnLJBRtKz+nILQ8lYYw== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.07,226,1708416000"; d="scan'208";a="29262768" Received: from agluck-desk3.sc.intel.com ([172.25.222.105]) by fmviesa005-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 24 Apr 2024 11:15:14 -0700 From: Tony Luck To: Borislav Petkov , Thomas Gleixner , Ingo Molnar , Dave Hansen , x86@kernel.org Cc: Fenghua Yu , Reinette Chatre , "H. Peter Anvin" , linux-kernel@vger.kernel.org, patches@lists.linux.dev, Tony Luck Subject: [PATCH v4 36/71] x86/resctrl: Switch to new Intel CPU model defines Date: Wed, 24 Apr 2024 11:15:14 -0700 Message-ID: <20240424181514.41848-1-tony.luck@intel.com> X-Mailer: git-send-email 2.44.0 In-Reply-To: <20240424181245.41141-1-tony.luck@intel.com> References: <20240424181245.41141-1-tony.luck@intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" New CPU #defines encode vendor and family as well as model. Signed-off-by: Tony Luck Acked-by: Hans de Goede --- arch/x86/kernel/cpu/resctrl/core.c | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/arch/x86/kernel/cpu/resctrl/core.c b/arch/x86/kernel/cpu/resct= rl/core.c index 83e40341583e..19b4fdb94a36 100644 --- a/arch/x86/kernel/cpu/resctrl/core.c +++ b/arch/x86/kernel/cpu/resctrl/core.c @@ -22,7 +22,7 @@ #include #include =20 -#include +#include #include #include "internal.h" =20 @@ -821,18 +821,18 @@ static __init bool get_rdt_mon_resources(void) =20 static __init void __check_quirks_intel(void) { - switch (boot_cpu_data.x86_model) { - case INTEL_FAM6_HASWELL_X: + switch (boot_cpu_data.x86_vfm) { + case INTEL_HASWELL_X: if (!rdt_options[RDT_FLAG_L3_CAT].force_off) cache_alloc_hsw_probe(); break; - case INTEL_FAM6_SKYLAKE_X: + case INTEL_SKYLAKE_X: if (boot_cpu_data.x86_stepping <=3D 4) set_rdt_options("!cmt,!mbmtotal,!mbmlocal,!l3cat"); else set_rdt_options("!l3cat"); fallthrough; - case INTEL_FAM6_BROADWELL_X: + case INTEL_BROADWELL_X: intel_rdt_mbm_apply_quirk(); break; } --=20 2.44.0 From nobody Sat Jul 11 15:40:01 2026 Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.18]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C5E52184111 for ; Wed, 24 Apr 2024 18:15:26 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=192.198.163.18 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1713982528; cv=none; b=kJtNZnCrVSSl1QDAdy5LzPyVZdnSjCR+oyniXzvCsUiI58ui2dCeez57I7YdNgmEKJwYiO/L/7TL2l8ii7eNRyclGh990T0pVkChC5YEqP8tqDvkmzGMoEehgsk3meOXlyffmAS/ZPTCopy8JiNrOBQTEStfie0CWqrKqOcRICY= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1713982528; c=relaxed/simple; bh=AsjGODFPSGB1rd7KGy1xLTYIPWqwB7V2MxUYDxCtEt0=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=bO1ZnuwmfKaxEu7CKgDBh8t5TjhoWqhpVYXJg1MCbw0Gw1u3TZqdkq8S0ssSUMv9rFSxxV+b77j5CzekMHSqpP7mfZF00dL8n3W8RXdFPVoFZJf6UIaNElPRmIBAvsaGghMLpgyVKEV/T+hU6f+vU/5F0QcJ15fVRrXaVM0PL30= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com; spf=pass smtp.mailfrom=intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=AHui+clW; arc=none smtp.client-ip=192.198.163.18 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="AHui+clW" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1713982527; x=1745518527; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=AsjGODFPSGB1rd7KGy1xLTYIPWqwB7V2MxUYDxCtEt0=; b=AHui+clWdDNJ7DuhdlFmkgG4VGiaUz2ups/1yo+XR3+ZXseqq2BHWFhW pmEC5qDTHUN0E9vSdEOgp6Rp8dG88XPyk2Z20u58HpZEWTrkCbSn1LUiC Pq+Arg93hHzjDxOLRnJwhmnVM6+KrC8Ysw3pthzyK724X7WJzJK6pi2Yp 0DzxiK8WRy6QWAzUwvDSorjE57LLqOUj48WW9yWeAiEfEihB66sgNL2lP +D2Hqh9rYkjZUojHBRLuJVh9HrChDUHfc2JUdDwSjJLZVt9OvAzSuGYal UIlyEO0yQSJY7tle8KO+0vzHM6eD1jQjYr4ylqSmhXuwP49RIU+MuLYzF g==; X-CSE-ConnectionGUID: P++34PywSw+Eu7qhX1ClTg== X-CSE-MsgGUID: fwAmb8gbTg6Y2PCrz5AAMQ== X-IronPort-AV: E=McAfee;i="6600,9927,11054"; a="9482039" X-IronPort-AV: E=Sophos;i="6.07,226,1708416000"; d="scan'208";a="9482039" Received: from fmviesa005.fm.intel.com ([10.60.135.145]) by fmvoesa112.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 24 Apr 2024 11:15:15 -0700 X-CSE-ConnectionGUID: K3hFkVG1Sseq0SnQKXWUCg== X-CSE-MsgGUID: +9Cg8+tzTJO+K/x3MGB3aw== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.07,226,1708416000"; d="scan'208";a="29262772" Received: from agluck-desk3.sc.intel.com ([172.25.222.105]) by fmviesa005-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 24 Apr 2024 11:15:15 -0700 From: Tony Luck To: Borislav Petkov , Thomas Gleixner , Ingo Molnar , Dave Hansen , x86@kernel.org Cc: Fenghua Yu , Reinette Chatre , "H. Peter Anvin" , linux-kernel@vger.kernel.org, patches@lists.linux.dev, Tony Luck Subject: [PATCH v4 37/71] x86/resctrl: Switch to new Intel CPU model defines Date: Wed, 24 Apr 2024 11:15:14 -0700 Message-ID: <20240424181514.41867-1-tony.luck@intel.com> X-Mailer: git-send-email 2.44.0 In-Reply-To: <20240424181245.41141-1-tony.luck@intel.com> References: <20240424181245.41141-1-tony.luck@intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" New CPU #defines encode vendor and family as well as model. Signed-off-by: Tony Luck Acked-by: Hans de Goede --- arch/x86/kernel/cpu/resctrl/pseudo_lock.c | 22 +++++++++++----------- 1 file changed, 11 insertions(+), 11 deletions(-) diff --git a/arch/x86/kernel/cpu/resctrl/pseudo_lock.c b/arch/x86/kernel/cp= u/resctrl/pseudo_lock.c index 884b88e25141..04584a76ceb4 100644 --- a/arch/x86/kernel/cpu/resctrl/pseudo_lock.c +++ b/arch/x86/kernel/cpu/resctrl/pseudo_lock.c @@ -23,7 +23,7 @@ #include =20 #include -#include +#include #include #include =20 @@ -88,8 +88,8 @@ static u64 get_prefetch_disable_bits(void) boot_cpu_data.x86 !=3D 6) return 0; =20 - switch (boot_cpu_data.x86_model) { - case INTEL_FAM6_BROADWELL_X: + switch (boot_cpu_data.x86_vfm) { + case INTEL_BROADWELL_X: /* * SDM defines bits of MSR_MISC_FEATURE_CONTROL register * as: @@ -100,8 +100,8 @@ static u64 get_prefetch_disable_bits(void) * 63:4 Reserved */ return 0xF; - case INTEL_FAM6_ATOM_GOLDMONT: - case INTEL_FAM6_ATOM_GOLDMONT_PLUS: + case INTEL_ATOM_GOLDMONT: + case INTEL_ATOM_GOLDMONT_PLUS: /* * SDM defines bits of MSR_MISC_FEATURE_CONTROL register * as: @@ -1084,9 +1084,9 @@ static int measure_l2_residency(void *_plr) * L2_HIT 02H * L2_MISS 10H */ - switch (boot_cpu_data.x86_model) { - case INTEL_FAM6_ATOM_GOLDMONT: - case INTEL_FAM6_ATOM_GOLDMONT_PLUS: + switch (boot_cpu_data.x86_vfm) { + case INTEL_ATOM_GOLDMONT: + case INTEL_ATOM_GOLDMONT_PLUS: perf_miss_attr.config =3D X86_CONFIG(.event =3D 0xd1, .umask =3D 0x10); perf_hit_attr.config =3D X86_CONFIG(.event =3D 0xd1, @@ -1123,8 +1123,8 @@ static int measure_l3_residency(void *_plr) * MISS 41H */ =20 - switch (boot_cpu_data.x86_model) { - case INTEL_FAM6_BROADWELL_X: + switch (boot_cpu_data.x86_vfm) { + case INTEL_BROADWELL_X: /* On BDW the hit event counts references, not hits */ perf_hit_attr.config =3D X86_CONFIG(.event =3D 0x2e, .umask =3D 0x4f); @@ -1142,7 +1142,7 @@ static int measure_l3_residency(void *_plr) */ =20 counts.miss_after -=3D counts.miss_before; - if (boot_cpu_data.x86_model =3D=3D INTEL_FAM6_BROADWELL_X) { + if (boot_cpu_data.x86_vfm =3D=3D INTEL_BROADWELL_X) { /* * On BDW references and misses are counted, need to adjust. * Sometimes the "hits" counter is a bit more than the --=20 2.44.0 From nobody Sat Jul 11 15:40:01 2026 Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.18]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E9F9C190671 for ; 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Peter Anvin" , Peter Zijlstra , David Woodhouse , linux-kernel@vger.kernel.org, patches@lists.linux.dev, Tony Luck Subject: [PATCH v4 38/71] x86/cpu/: Switch to new Intel CPU model defines Date: Wed, 24 Apr 2024 11:15:16 -0700 Message-ID: <20240424181516.41887-1-tony.luck@intel.com> X-Mailer: git-send-email 2.44.0 In-Reply-To: <20240424181245.41141-1-tony.luck@intel.com> References: <20240424181245.41141-1-tony.luck@intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" New CPU #defines encode vendor and family as well as model. Signed-off-by: Tony Luck Acked-by: Hans de Goede --- arch/x86/kernel/smpboot.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/arch/x86/kernel/smpboot.c b/arch/x86/kernel/smpboot.c index a58109583c47..8dc83b16845b 100644 --- a/arch/x86/kernel/smpboot.c +++ b/arch/x86/kernel/smpboot.c @@ -438,9 +438,9 @@ static bool match_pkg(struct cpuinfo_x86 *c, struct cpu= info_x86 *o) */ =20 static const struct x86_cpu_id intel_cod_cpu[] =3D { - X86_MATCH_INTEL_FAM6_MODEL(HASWELL_X, 0), /* COD */ - X86_MATCH_INTEL_FAM6_MODEL(BROADWELL_X, 0), /* COD */ - X86_MATCH_INTEL_FAM6_MODEL(ANY, 1), /* SNC */ + X86_MATCH_VFM(INTEL_HASWELL_X, 0), /* COD */ + X86_MATCH_VFM(INTEL_BROADWELL_X, 0), /* COD */ + X86_MATCH_VFM(INTEL_ANY, 1), /* SNC */ {} }; =20 --=20 2.44.0 From nobody Sat Jul 11 15:40:01 2026 Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.18]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E93D919066D for ; Wed, 24 Apr 2024 18:15:27 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=192.198.163.18 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1713982529; cv=none; b=DyAbZasNR0jxmOb6cTC0KAd2/UgZaI9OQgAJJW+q+9ScRGFqg936PBptXlSoFXM/Vo0G+HDzxF3pgBbKxYJhcCyrTqv+86wIBuRs5f0LuvQu930uF/bkpS2biz4qoRoUgO7na5rI5J+03i7MXmLHciSpTwZEM+SN+i5kCjYG6H8= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1713982529; c=relaxed/simple; bh=ebqOtnUkt/A9psEl5cZDP3DS54C80vHz8/R3RNrcpS8=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=Lh25ef1JVLNYf8IfGGCl8m5rnLiGHWRy6clyW9nb/IZjH0RvFFlOX3T0Z9L+h4TeenaIZe1p13HGh51+8/WERd0GjF7Q20mWZ9WGtbbuTtsGIZoUyghusxhTV1gkw9rZB7zvxmOkcI7NotBoHXYDDJ8BRXFC3tRRl6bbLMxX9Os= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com; spf=pass smtp.mailfrom=intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=WVSzOgU8; arc=none smtp.client-ip=192.198.163.18 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="WVSzOgU8" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1713982528; x=1745518528; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=ebqOtnUkt/A9psEl5cZDP3DS54C80vHz8/R3RNrcpS8=; b=WVSzOgU8UJ7xnqkty8AZCf79VQBIJSbkpVB/1nNdIUwi/hk/TgNcV1Lp da4a7q7osIATK8XqEwdxB8MPVrxInmRhoYcvJ/w+MwNpbE0CvbWMcLvdm LwfattwQrBpOuRhaqaigj/QD/S9yhT8jCrq3rfzq/QrYTyRpgTaWn1qwQ 9B1fDoQYmtXq9L0DCnWjZyUMG4weZW8L+JEbBoTsY5tkHoW7t+oxQywlU WX4zNhWBetCCbAmW6VV+MrY7dEAzSkkzbDEMobeB3AGtHgb70SrhNCUcf VhKxWwYveJtnpq5CVTBVECEDYtvoJV5jC1p4eWZu96hW+ufW/mc66ovxS A==; X-CSE-ConnectionGUID: Gx+bneXRR62Z5c4b7s5x6A== X-CSE-MsgGUID: T2Il1whRTpWmk+EdkWAMfA== X-IronPort-AV: E=McAfee;i="6600,9927,11054"; a="9482061" X-IronPort-AV: E=Sophos;i="6.07,226,1708416000"; d="scan'208";a="9482061" Received: from fmviesa005.fm.intel.com ([10.60.135.145]) by fmvoesa112.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 24 Apr 2024 11:15:17 -0700 X-CSE-ConnectionGUID: JpdAqOPdReKZb5fPA5G9Eg== X-CSE-MsgGUID: 8NhhASDjSpKDp8oAugHh2A== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.07,226,1708416000"; d="scan'208";a="29262785" Received: from agluck-desk3.sc.intel.com ([172.25.222.105]) by fmviesa005-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 24 Apr 2024 11:15:17 -0700 From: Tony Luck To: Borislav Petkov , Thomas Gleixner , Ingo Molnar , Dave Hansen , x86@kernel.org Cc: "H. Peter Anvin" , Peter Hilber , Peter Zijlstra , "Paul E. McKenney" , Feng Tang , Tony Luck , Randy Dunlap , linux-kernel@vger.kernel.org, patches@lists.linux.dev Subject: [PATCH v4 39/71] x86/tsc: Switch to new Intel CPU model defines Date: Wed, 24 Apr 2024 11:15:17 -0700 Message-ID: <20240424181517.41907-1-tony.luck@intel.com> X-Mailer: git-send-email 2.44.0 In-Reply-To: <20240424181245.41141-1-tony.luck@intel.com> References: <20240424181245.41141-1-tony.luck@intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" New CPU #defines encode vendor and family as well as model. Signed-off-by: Tony Luck Acked-by: Hans de Goede --- arch/x86/kernel/tsc.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/arch/x86/kernel/tsc.c b/arch/x86/kernel/tsc.c index 5a69a49acc96..c4745141dd17 100644 --- a/arch/x86/kernel/tsc.c +++ b/arch/x86/kernel/tsc.c @@ -26,7 +26,7 @@ #include #include #include -#include +#include #include #include =20 @@ -682,7 +682,7 @@ unsigned long native_calibrate_tsc(void) * clock. */ if (crystal_khz =3D=3D 0 && - boot_cpu_data.x86_model =3D=3D INTEL_FAM6_ATOM_GOLDMONT_D) + boot_cpu_data.x86_vfm =3D=3D INTEL_ATOM_GOLDMONT_D) crystal_khz =3D 25000; =20 /* @@ -713,7 +713,7 @@ unsigned long native_calibrate_tsc(void) * For Atom SoCs TSC is the only reliable clocksource. * Mark TSC reliable so no watchdog on it. */ - if (boot_cpu_data.x86_model =3D=3D INTEL_FAM6_ATOM_GOLDMONT) + if (boot_cpu_data.x86_vfm =3D=3D INTEL_ATOM_GOLDMONT) setup_force_cpu_cap(X86_FEATURE_TSC_RELIABLE); =20 #ifdef CONFIG_X86_LOCAL_APIC --=20 2.44.0 From nobody Sat Jul 11 15:40:01 2026 Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.18]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E2DC2199EA9 for ; Wed, 24 Apr 2024 18:15:28 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=192.198.163.18 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1713982530; cv=none; b=dDEu2HXN7BYuab+f5H2vqeT8ZQ7ovpeYdBtOksP+uS7E/vy3pDN1YiWy7UYt+HN0aMeUHuu33ZPRyVbgCt6wNpbCMV9LNMwgA4THe6QiueQHkNjDA6KofV8FdSizkxG7eF/HLLiJwrtDm/zd/J2rxzeokaLyemHaV03eUjUk0qs= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1713982530; c=relaxed/simple; bh=dCC5e5zdUWP8nN10zczP7r4e33cRc3Nah82w39Vvy74=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=dQciXMpMoIvmiuzfsNCzG76FwsDFnJMWX9MVQOaiLNtGvIhLuSzC26bA5QXu6vEcuXFBy8fBxlCOB5wSiAVi0JAgeR67sT6a6KzHE5uSn+CwLInf08+eooX7QQhjuOJ/UinkevY3rrP+10ISWfFER/xNu6WA74Q8+kIzgyUGvUI= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com; spf=pass smtp.mailfrom=intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=Z/nX5rg9; arc=none smtp.client-ip=192.198.163.18 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="Z/nX5rg9" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1713982529; x=1745518529; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=dCC5e5zdUWP8nN10zczP7r4e33cRc3Nah82w39Vvy74=; b=Z/nX5rg93JZVjrZu/ez6E9VE7I8Ly6AAk30qaxSdbXFR73mMYjZY69zH Bm15k/CX0NKz627oU2u0a24pJF0tctsSBMCgkcLju47JQ3NIYk37wU2lB Wbpj+Ys2lbAqCbLx7CMv0KQmWu0MWuqbBkuubuqyT7Zuul31maEwPvM1H pZVKmR1yTtXiPmHHZwxVQP/gbBU/e8mgwZM8XD/GO8pGy9sqYrq6Zq4yi pSLNfG/bHGgXL3QSBSu2fCGVopKtU2Hzlu9rTpKZfr/ypcOvHkRMKqNpa 9jaKmIaC+ED9zFlpPcXtt9wMe9Bte4HhGZaz4mkw2+G1XuH66cMY/qY4a Q==; X-CSE-ConnectionGUID: EU/b5jb6T8iGI40zBOWe6A== X-CSE-MsgGUID: ynEM4odkSpKb+RD5gkAjRw== X-IronPort-AV: E=McAfee;i="6600,9927,11054"; a="9482072" X-IronPort-AV: E=Sophos;i="6.07,226,1708416000"; d="scan'208";a="9482072" Received: from fmviesa005.fm.intel.com ([10.60.135.145]) by fmvoesa112.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 24 Apr 2024 11:15:18 -0700 X-CSE-ConnectionGUID: mgTPo2hJR/2Epmgb3jkRYA== X-CSE-MsgGUID: HLu4AdKOSLGC4CcDZD7aOA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.07,226,1708416000"; d="scan'208";a="29262788" Received: from agluck-desk3.sc.intel.com ([172.25.222.105]) by fmviesa005-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 24 Apr 2024 11:15:18 -0700 From: Tony Luck To: Borislav Petkov , Thomas Gleixner , Ingo Molnar , Dave Hansen , x86@kernel.org Cc: "H. Peter Anvin" , Tony Luck , linux-kernel@vger.kernel.org, patches@lists.linux.dev Subject: [PATCH v4 40/71] x86/tsc_msr: Switch to new Intel CPU model defines Date: Wed, 24 Apr 2024 11:15:18 -0700 Message-ID: <20240424181518.41927-1-tony.luck@intel.com> X-Mailer: git-send-email 2.44.0 In-Reply-To: <20240424181245.41141-1-tony.luck@intel.com> References: <20240424181245.41141-1-tony.luck@intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" New CPU #defines encode vendor and family as well as model. Signed-off-by: Tony Luck Acked-by: Hans de Goede --- arch/x86/kernel/tsc_msr.c | 14 +++++++------- 1 file changed, 7 insertions(+), 7 deletions(-) diff --git a/arch/x86/kernel/tsc_msr.c b/arch/x86/kernel/tsc_msr.c index 6555a857a1e6..deeb02825670 100644 --- a/arch/x86/kernel/tsc_msr.c +++ b/arch/x86/kernel/tsc_msr.c @@ -147,13 +147,13 @@ static const struct freq_desc freq_desc_lgm =3D { }; =20 static const struct x86_cpu_id tsc_msr_cpu_ids[] =3D { - X86_MATCH_INTEL_FAM6_MODEL(ATOM_SALTWELL_MID, &freq_desc_pnw), - X86_MATCH_INTEL_FAM6_MODEL(ATOM_SALTWELL_TABLET,&freq_desc_clv), - X86_MATCH_INTEL_FAM6_MODEL(ATOM_SILVERMONT, &freq_desc_byt), - X86_MATCH_INTEL_FAM6_MODEL(ATOM_SILVERMONT_MID, &freq_desc_tng), - X86_MATCH_INTEL_FAM6_MODEL(ATOM_AIRMONT, &freq_desc_cht), - X86_MATCH_INTEL_FAM6_MODEL(ATOM_AIRMONT_MID, &freq_desc_ann), - X86_MATCH_INTEL_FAM6_MODEL(ATOM_AIRMONT_NP, &freq_desc_lgm), + X86_MATCH_VFM(INTEL_ATOM_SALTWELL_MID, &freq_desc_pnw), + X86_MATCH_VFM(INTEL_ATOM_SALTWELL_TABLET, &freq_desc_clv), + X86_MATCH_VFM(INTEL_ATOM_SILVERMONT, &freq_desc_byt), + X86_MATCH_VFM(INTEL_ATOM_SILVERMONT_MID, &freq_desc_tng), + X86_MATCH_VFM(INTEL_ATOM_AIRMONT, &freq_desc_cht), + X86_MATCH_VFM(INTEL_ATOM_AIRMONT_MID, &freq_desc_ann), + X86_MATCH_VFM(INTEL_ATOM_AIRMONT_NP, &freq_desc_lgm), {} }; =20 --=20 2.44.0 From nobody Sat Jul 11 15:40:01 2026 Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.18]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id F078519DF7A for ; Wed, 24 Apr 2024 18:15:29 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=192.198.163.18 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1713982531; cv=none; b=qSX9tLnPyYMxQK5KUfc8SjUMjmLJUS5nUDydNNbmJzrzFD1i0+nJGNPkUOOPc55isQ4JbzFY0u9gn//8JdEDc9AGLcwprQeD6s0fFMyBaHpMujeKatk4keEVpPySUx9zwMGFxZP7QZuMaGsWN+3h/jKbnpxil5iOhn1seiFwHAQ= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1713982531; c=relaxed/simple; bh=FfXHVVXxAXvXhf26U3fzvKJ4+8iaBCg597mpHe5hnu0=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=SU1QlC+B66f5wN0ZILvQYVrRvhs7zTwrJ80Jgt166CsxSSMVpQsQBWG4DjYuK6/0uamorPn/1UpvXLeYv5QpUhcqFlhekS7fPvRzIAQ3QBc6w1WXw1mLYgckZy9WWVhv0KOgl/3ldxiHMqFeTmInFTSYlKWQPnZP2VaJMezUbiQ= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com; spf=pass smtp.mailfrom=intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=DsCe/ZYA; arc=none smtp.client-ip=192.198.163.18 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="DsCe/ZYA" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1713982530; x=1745518530; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=FfXHVVXxAXvXhf26U3fzvKJ4+8iaBCg597mpHe5hnu0=; b=DsCe/ZYAU7iRq8SD1I9BTCYT6VYG5poUNnyh8yNEcnQ3rT2msr5nkZtS KbvjIxRQz1m6d7I2abvQbq1jT9WsWOiEVdKcmQZo3OJpLfC6DnXhq7jv3 AGEeUKulA1E3q9kvBT2x0zGh2CoAD0Hc2454cIg2lcXzVt4k7gUh7+N+k bmZExerT4CW+0buUkM7/d42P5URrXXLfo6HsFbPfv/fW5Mkg3bM3/ho8l QhidrqcC50bK7rpc5d3vH1SPgQTLSPJSzxFWxoBdKVInMI0W+EYsozFqa Z0x1jdqfPsUOPQd9kXkXwu6UAiBcO+Pcn1DD3gjjeJOmtVeo5JiLBqqT6 A==; X-CSE-ConnectionGUID: DQHxgBteQj2VnzYLmj3OVQ== X-CSE-MsgGUID: q8fCCNrGR/KxzN1kc0xW5Q== X-IronPort-AV: E=McAfee;i="6600,9927,11054"; a="9482081" X-IronPort-AV: E=Sophos;i="6.07,226,1708416000"; d="scan'208";a="9482081" Received: from fmviesa005.fm.intel.com ([10.60.135.145]) by fmvoesa112.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 24 Apr 2024 11:15:19 -0700 X-CSE-ConnectionGUID: bO0fFlafRrua07hw4U++9g== X-CSE-MsgGUID: WU2AeidrSl6GnEj/OycV3w== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.07,226,1708416000"; d="scan'208";a="29262793" Received: from agluck-desk3.sc.intel.com ([172.25.222.105]) by fmviesa005-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 24 Apr 2024 11:15:19 -0700 From: Tony Luck To: Borislav Petkov , Dave Hansen , Andy Lutomirski , Peter Zijlstra , Thomas Gleixner , Ingo Molnar , x86@kernel.org Cc: "H. Peter Anvin" , linux-kernel@vger.kernel.org, patches@lists.linux.dev, Tony Luck Subject: [PATCH v4 41/71] x86/mm: Switch to new Intel CPU model defines Date: Wed, 24 Apr 2024 11:15:18 -0700 Message-ID: <20240424181518.41946-1-tony.luck@intel.com> X-Mailer: git-send-email 2.44.0 In-Reply-To: <20240424181245.41141-1-tony.luck@intel.com> References: <20240424181245.41141-1-tony.luck@intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" New CPU #defines encode vendor and family as well as model. Signed-off-by: Tony Luck Acked-by: Hans de Goede --- arch/x86/mm/init.c | 16 ++++++---------- 1 file changed, 6 insertions(+), 10 deletions(-) diff --git a/arch/x86/mm/init.c b/arch/x86/mm/init.c index 679893ea5e68..fadc3fc3ee41 100644 --- a/arch/x86/mm/init.c +++ b/arch/x86/mm/init.c @@ -261,21 +261,17 @@ static void __init probe_page_size_mask(void) } } =20 -#define INTEL_MATCH(_model) { .vendor =3D X86_VENDOR_INTEL, \ - .family =3D 6, \ - .model =3D _model, \ - } /* * INVLPG may not properly flush Global entries * on these CPUs when PCIDs are enabled. */ static const struct x86_cpu_id invlpg_miss_ids[] =3D { - INTEL_MATCH(INTEL_FAM6_ALDERLAKE ), - INTEL_MATCH(INTEL_FAM6_ALDERLAKE_L ), - INTEL_MATCH(INTEL_FAM6_ATOM_GRACEMONT ), - INTEL_MATCH(INTEL_FAM6_RAPTORLAKE ), - INTEL_MATCH(INTEL_FAM6_RAPTORLAKE_P), - INTEL_MATCH(INTEL_FAM6_RAPTORLAKE_S), + X86_MATCH_VFM(INTEL_ALDERLAKE, 0), + X86_MATCH_VFM(INTEL_ALDERLAKE_L, 0), + X86_MATCH_VFM(INTEL_ATOM_GRACEMONT, 0), + X86_MATCH_VFM(INTEL_RAPTORLAKE, 0), + X86_MATCH_VFM(INTEL_RAPTORLAKE_P, 0), + X86_MATCH_VFM(INTEL_RAPTORLAKE_S, 0), {} }; =20 --=20 2.44.0 From nobody Sat Jul 11 15:40:01 2026 Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.19]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 7E77C181326; Wed, 24 Apr 2024 18:15:21 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=192.198.163.19 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1713982524; cv=none; b=sJCsXqgCmwaqGjU0LqmFOkaoZ8/B8a8aiHamDceqgbIJwQ2b5D0EsfCn8k1xYxMWq6/SapKc8A8h7zpK28mAFA6cUcDQz6SNnk7JpYu6a6a3/IgWMlXJ9GdX4VwSIjfFFxvadGD1XRnr1n+JdtC/j7naHNQOyCPItrT6htfpMvk= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1713982524; c=relaxed/simple; bh=obhXYEmt6d4ZPBEnG583vH7Ox14Ir+rTrmmNAEgF6jg=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=seFhzEHQ9gn8XJWiPF+QRuIz2N1OrP8gnh5RrUqdWUwS3JpFrV+ZNEoNYosrFDe6c/wZNbyQGQTDIMWNJkXYmJCSrjF9YXY9MaRqBcsYisxtvq8RMLFcc8IZbrcxqhPByD4G2Z7Usx48Xd7KJBL56Q+jG6cLEu+Q1mhDvQgmii4= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com; spf=pass smtp.mailfrom=intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=B3cj5rbl; arc=none smtp.client-ip=192.198.163.19 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="B3cj5rbl" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1713982521; x=1745518521; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=obhXYEmt6d4ZPBEnG583vH7Ox14Ir+rTrmmNAEgF6jg=; b=B3cj5rblgcOnu7sbJn3nZ6XpbLriNwm3J5GbITYADQK568h/LFJSiUT8 UimrECfPEpMig6AckfbBLfsuktxc41MaXrrG14A5hR+a+AStygTFKu4FY 3ixfK4A+GOJElGXBZ0yGAnb0chM8TdAhDWg+udOQAG1qsGwjFU1vd6c9s ZA7+4QM0TYcJYtk7zzQMoLqYxBdEg0TGu4J1fnY18l+iD7RkmSGjljDDo 9Mws2y9QAj7ajRGt8Dv/mCYy3lOqVed1nwWnUgMyzjLQ2fTCIBuyzcV/j tpnvl13t4cKwf82g375OYGIyREESPJrMq6PEZ4rhqMZT5EbQ5AGpr/E6O Q==; X-CSE-ConnectionGUID: gGjtlU4CTWi2nxX1DEfAjw== X-CSE-MsgGUID: CG7faPwISdCsUXGIJl3fdA== X-IronPort-AV: E=McAfee;i="6600,9927,11054"; a="9503539" X-IronPort-AV: E=Sophos;i="6.07,226,1708416000"; d="scan'208";a="9503539" Received: from orviesa002.jf.intel.com ([10.64.159.142]) by fmvoesa113.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 24 Apr 2024 11:15:21 -0700 X-CSE-ConnectionGUID: VcIiWi/bQZai5oz5I5U70w== X-CSE-MsgGUID: lbQj+TPeSR6BAaCag2O2PQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.07,226,1708416000"; d="scan'208";a="55750130" Received: from agluck-desk3.sc.intel.com ([172.25.222.105]) by orviesa002-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 24 Apr 2024 11:15:20 -0700 From: Tony Luck To: Borislav Petkov , Thomas Gleixner , Ingo Molnar , Dave Hansen , x86@kernel.org Cc: Bjorn Helgaas , "H. Peter Anvin" , linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org, patches@lists.linux.dev, Tony Luck Subject: [PATCH v4 42/71] x86/PCI: Switch to new Intel CPU model defines Date: Wed, 24 Apr 2024 11:15:20 -0700 Message-ID: <20240424181520.41965-1-tony.luck@intel.com> X-Mailer: git-send-email 2.44.0 In-Reply-To: <20240424181245.41141-1-tony.luck@intel.com> References: <20240424181245.41141-1-tony.luck@intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" New CPU #defines encode vendor and family as well as model. Signed-off-by: Tony Luck Acked-by: Hans de Goede --- arch/x86/pci/intel_mid_pci.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/x86/pci/intel_mid_pci.c b/arch/x86/pci/intel_mid_pci.c index 8edd62206604..933ff795e53e 100644 --- a/arch/x86/pci/intel_mid_pci.c +++ b/arch/x86/pci/intel_mid_pci.c @@ -216,7 +216,7 @@ static int pci_write(struct pci_bus *bus, unsigned int = devfn, int where, } =20 static const struct x86_cpu_id intel_mid_cpu_ids[] =3D { - X86_MATCH_INTEL_FAM6_MODEL(ATOM_SILVERMONT_MID, NULL), + X86_MATCH_VFM(INTEL_ATOM_SILVERMONT_MID, NULL), {} }; =20 @@ -243,7 +243,7 @@ static int intel_mid_pci_irq_enable(struct pci_dev *dev) model =3D id->model; =20 switch (model) { - case INTEL_FAM6_ATOM_SILVERMONT_MID: + case VFM_MODEL(INTEL_ATOM_SILVERMONT_MID): polarity_low =3D false; =20 /* Special treatment for IRQ0 */ --=20 2.44.0 From nobody Sat Jul 11 15:40:01 2026 Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.19]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B0EAC181CF4 for ; Wed, 24 Apr 2024 18:15:23 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=192.198.163.19 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1713982525; cv=none; b=EWnh2kuAtO1cTAB4WSLQGbBux6a7zAtGG9Fg/Oa6MYWQw83d9bCz3Q2tvOMkxTwIC8LbFowLLZ8MAE/0W83r/79dismpod20qb1klOosg4fMczB28x+hHrx5X5yprRjFTI+munVwks/K5L+CHPhSwnNGo84gmJAhfH0CF4c2aAI= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1713982525; c=relaxed/simple; bh=zpJumNq7u5KsT133nYF8l88fxW5RaBTIKz2lN9diWJs=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=KXRQwmV6n8RjKeTsWMqLTt3gX2MwatGsO6Vw8WqIPKQrXxZquovOiSBee/Voq7xFLH4A0xTGBE0bTYHA23/TLRyeA+ez5UAXLo6Y/9nWEpNHrjFvzvfAmcUBNkbGKsn21xAT9xyihOEf9AfDGkhOnbuz1sfdDsxbuTD+yUtmTKc= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com; spf=pass smtp.mailfrom=intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=ZPaGAXpF; arc=none smtp.client-ip=192.198.163.19 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="ZPaGAXpF" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1713982523; x=1745518523; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=zpJumNq7u5KsT133nYF8l88fxW5RaBTIKz2lN9diWJs=; b=ZPaGAXpFmrF7pCjwqM5CM6QYg5G4ValsGB9sjuvrsfG6bj18GW5VFx4r t98F8NMcEYIvU88SJN/WXS6EBM8GMBcBcFNvlTTNA7CoYxKrhM+TXhpCX 1hSIMaOHmS+NoE6KQ5ZGDsBxq88FU9YH4657xViqdo8YGoIFJf4Gvgn+I QT8QWR1b9Z1+jGBtSvETjmDcj4SeCCrnk92CNk1HfYRGO5dcDnD3GaWRq yuHQBe7QZsCm6f6FO+gnZRSggxjeckiZxV+2kY2T+x53ruqecju373V0N uXEo9TTa2YdUC79mQUB4o2Gvp7ORwBs5kOghne9Cw2Mys1FFO9gKOB96g w==; X-CSE-ConnectionGUID: d7vRFbxDSm+AfrGF0iab1g== X-CSE-MsgGUID: X46MGLF3Qc+BEm96NSWkgA== X-IronPort-AV: E=McAfee;i="6600,9927,11054"; a="9503545" X-IronPort-AV: E=Sophos;i="6.07,226,1708416000"; d="scan'208";a="9503545" Received: from orviesa002.jf.intel.com ([10.64.159.142]) by fmvoesa113.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 24 Apr 2024 11:15:21 -0700 X-CSE-ConnectionGUID: yLYbQYPRRbq++zx8rXyWIQ== X-CSE-MsgGUID: QcLdNXhVRx29TbGdnJqhFA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.07,226,1708416000"; d="scan'208";a="55750135" Received: from agluck-desk3.sc.intel.com ([172.25.222.105]) by orviesa002-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 24 Apr 2024 11:15:21 -0700 From: Tony Luck To: Borislav Petkov , Thomas Gleixner , Ingo Molnar , x86@kernel.org Cc: "Kirill A. Shutemov" , Dave Hansen , "H. Peter Anvin" , linux-coco@lists.linux.dev, linux-kernel@vger.kernel.org, patches@lists.linux.dev, Tony Luck Subject: [PATCH v4 43/71] x86/virt/tdx: Switch to new Intel CPU model defines Date: Wed, 24 Apr 2024 11:15:21 -0700 Message-ID: <20240424181521.41984-1-tony.luck@intel.com> X-Mailer: git-send-email 2.44.0 In-Reply-To: <20240424181245.41141-1-tony.luck@intel.com> References: <20240424181245.41141-1-tony.luck@intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" New CPU #defines encode vendor and family as well as model. Signed-off-by: Tony Luck Acked-by: Hans de Goede --- arch/x86/virt/vmx/tdx/tdx.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/x86/virt/vmx/tdx/tdx.c b/arch/x86/virt/vmx/tdx/tdx.c index 4d6826a76f78..ee9a9273b75a 100644 --- a/arch/x86/virt/vmx/tdx/tdx.c +++ b/arch/x86/virt/vmx/tdx/tdx.c @@ -34,7 +34,7 @@ #include #include #include -#include +#include #include #include #include "tdx.h" @@ -1427,9 +1427,9 @@ static void __init check_tdx_erratum(void) * private memory poisons that memory, and a subsequent read of * that memory triggers #MC. */ - switch (boot_cpu_data.x86_model) { - case INTEL_FAM6_SAPPHIRERAPIDS_X: - case INTEL_FAM6_EMERALDRAPIDS_X: + switch (boot_cpu_data.x86_vfm) { + case INTEL_SAPPHIRERAPIDS_X: + case INTEL_EMERALDRAPIDS_X: setup_force_cpu_bug(X86_BUG_TDX_PW_MCE); } } --=20 2.44.0 From nobody Sat Jul 11 15:40:01 2026 Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.19]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C9FFC1836C1; Wed, 24 Apr 2024 18:15:24 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=192.198.163.19 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1713982527; cv=none; b=H+fz1RGVMDtEMSli15TWYV9RjZs3tg+RgVTEtYhwxThzhaicqo4ysyWi4L7YCHiqDYwGIoDMBjDzXAgAPVw/mVE+tTpQoe0PV9e7yQNgASwwIIkPSrrkDis6d6mOb6WISplpI1XgaB1mlJrF14yAJAVPf3r7iCecL7ogntfcu3Q= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1713982527; c=relaxed/simple; bh=UCKckKaf+DcEOivednlx2AHS0yzAWKTc2jZ4Dmi/hSY=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=l7V1ngiQAIM3awDsFhr7kuyjJPC0IGMFjpU7WL2n72e0YeeZ9yNoVq25BIuA2RhuDVU4uNJT/DfXf8JrKWws8cdIzCWFlT1fRyZtYbOLzTNsusFsV0jptOzcsGpgQGgsuY5w8hBs1A4PBARoWpRpJfiP4iJ0232YhkIH7h/rKlo= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com; spf=pass smtp.mailfrom=intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=DlnrfCQz; arc=none smtp.client-ip=192.198.163.19 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="DlnrfCQz" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1713982525; x=1745518525; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=UCKckKaf+DcEOivednlx2AHS0yzAWKTc2jZ4Dmi/hSY=; b=DlnrfCQzjYQFH1/W2wdDFVk8zKcgwEyLLLADdpw5K7MWNe9V0eChVzHc FulF7P4iEIBNx4tetStVCzud0CXvp2YY+Y2PNFEX/itiC8PJ0xQuQX7S2 qVJfp2vY3INw4k5hLm2MwLuVTEgeMSaAtKtHRgbX6uwxxWsWedra/18ii FJbAqYgje4Y0lTjNdIqkwUCnSnh44ltmU2UsC1DjWCdGaodMBQ+qrB8TV 5IByCQzVuxsCikTDAH5CU6nXcrsqQOu03zqz/nX3frWo2nVilzNVwrph4 z6+Cql/zPN2wQW2eNwkWZeQxLT4D35orahCfmOXSd9jMcjJMj5OA+/aDA w==; X-CSE-ConnectionGUID: 5EYwfrMLRC6+zh0QkRH7tA== X-CSE-MsgGUID: J5ZAeboDTDyOqB64535UaA== X-IronPort-AV: E=McAfee;i="6600,9927,11054"; a="9503556" X-IronPort-AV: E=Sophos;i="6.07,226,1708416000"; d="scan'208";a="9503556" Received: from orviesa002.jf.intel.com ([10.64.159.142]) by fmvoesa113.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 24 Apr 2024 11:15:23 -0700 X-CSE-ConnectionGUID: PhqqU9O7TOu74FunfXepfg== X-CSE-MsgGUID: PAd/USUvR3aYcNgGOkVE2w== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.07,226,1708416000"; d="scan'208";a="55750143" Received: from agluck-desk3.sc.intel.com ([172.25.222.105]) by orviesa002-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 24 Apr 2024 11:15:22 -0700 From: Tony Luck To: Borislav Petkov , Thomas Gleixner , Dave Hansen , x86@kernel.org Cc: Peter Zijlstra , Ingo Molnar , Arnaldo Carvalho de Melo , Namhyung Kim , Mark Rutland , Alexander Shishkin , Jiri Olsa , Ian Rogers , Adrian Hunter , "H. Peter Anvin" , linux-perf-users@vger.kernel.org, linux-kernel@vger.kernel.org, patches@lists.linux.dev, Tony Luck Subject: [PATCH v4 44/71] perf/x86/intel: Switch to new Intel CPU model defines Date: Wed, 24 Apr 2024 11:15:22 -0700 Message-ID: <20240424181522.42003-1-tony.luck@intel.com> X-Mailer: git-send-email 2.44.0 In-Reply-To: <20240424181245.41141-1-tony.luck@intel.com> References: <20240424181245.41141-1-tony.luck@intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" New CPU #defines encode vendor and family as well as model. Signed-off-by: Tony Luck Acked-by: Hans de Goede --- arch/x86/events/intel/core.c | 148 +++++++++++++++++------------------ 1 file changed, 74 insertions(+), 74 deletions(-) diff --git a/arch/x86/events/intel/core.c b/arch/x86/events/intel/core.c index 768d1414897f..94206f8cd371 100644 --- a/arch/x86/events/intel/core.c +++ b/arch/x86/events/intel/core.c @@ -4698,8 +4698,8 @@ static void intel_pmu_check_extra_regs(struct extra_r= eg *extra_regs); static inline bool intel_pmu_broken_perf_cap(void) { /* The Perf Metric (Bit 15) is always cleared */ - if ((boot_cpu_data.x86_model =3D=3D INTEL_FAM6_METEORLAKE) || - (boot_cpu_data.x86_model =3D=3D INTEL_FAM6_METEORLAKE_L)) + if (boot_cpu_data.x86_vfm =3D=3D INTEL_METEORLAKE || + boot_cpu_data.x86_vfm =3D=3D INTEL_METEORLAKE_L) return true; =20 return false; @@ -6245,19 +6245,19 @@ __init int intel_pmu_init(void) /* * Install the hw-cache-events table: */ - switch (boot_cpu_data.x86_model) { - case INTEL_FAM6_CORE_YONAH: + switch (boot_cpu_data.x86_vfm) { + case INTEL_CORE_YONAH: pr_cont("Core events, "); name =3D "core"; break; =20 - case INTEL_FAM6_CORE2_MEROM: + case INTEL_CORE2_MEROM: x86_add_quirk(intel_clovertown_quirk); fallthrough; =20 - case INTEL_FAM6_CORE2_MEROM_L: - case INTEL_FAM6_CORE2_PENRYN: - case INTEL_FAM6_CORE2_DUNNINGTON: + case INTEL_CORE2_MEROM_L: + case INTEL_CORE2_PENRYN: + case INTEL_CORE2_DUNNINGTON: memcpy(hw_cache_event_ids, core2_hw_cache_event_ids, sizeof(hw_cache_event_ids)); =20 @@ -6269,9 +6269,9 @@ __init int intel_pmu_init(void) name =3D "core2"; break; =20 - case INTEL_FAM6_NEHALEM: - case INTEL_FAM6_NEHALEM_EP: - case INTEL_FAM6_NEHALEM_EX: + case INTEL_NEHALEM: + case INTEL_NEHALEM_EP: + case INTEL_NEHALEM_EX: memcpy(hw_cache_event_ids, nehalem_hw_cache_event_ids, sizeof(hw_cache_event_ids)); memcpy(hw_cache_extra_regs, nehalem_hw_cache_extra_regs, @@ -6303,11 +6303,11 @@ __init int intel_pmu_init(void) name =3D "nehalem"; break; =20 - case INTEL_FAM6_ATOM_BONNELL: - case INTEL_FAM6_ATOM_BONNELL_MID: - case INTEL_FAM6_ATOM_SALTWELL: - case INTEL_FAM6_ATOM_SALTWELL_MID: - case INTEL_FAM6_ATOM_SALTWELL_TABLET: + case INTEL_ATOM_BONNELL: + case INTEL_ATOM_BONNELL_MID: + case INTEL_ATOM_SALTWELL: + case INTEL_ATOM_SALTWELL_MID: + case INTEL_ATOM_SALTWELL_TABLET: memcpy(hw_cache_event_ids, atom_hw_cache_event_ids, sizeof(hw_cache_event_ids)); =20 @@ -6320,11 +6320,11 @@ __init int intel_pmu_init(void) name =3D "bonnell"; break; =20 - case INTEL_FAM6_ATOM_SILVERMONT: - case INTEL_FAM6_ATOM_SILVERMONT_D: - case INTEL_FAM6_ATOM_SILVERMONT_MID: - case INTEL_FAM6_ATOM_AIRMONT: - case INTEL_FAM6_ATOM_AIRMONT_MID: + case INTEL_ATOM_SILVERMONT: + case INTEL_ATOM_SILVERMONT_D: + case INTEL_ATOM_SILVERMONT_MID: + case INTEL_ATOM_AIRMONT: + case INTEL_ATOM_AIRMONT_MID: memcpy(hw_cache_event_ids, slm_hw_cache_event_ids, sizeof(hw_cache_event_ids)); memcpy(hw_cache_extra_regs, slm_hw_cache_extra_regs, @@ -6342,8 +6342,8 @@ __init int intel_pmu_init(void) name =3D "silvermont"; break; =20 - case INTEL_FAM6_ATOM_GOLDMONT: - case INTEL_FAM6_ATOM_GOLDMONT_D: + case INTEL_ATOM_GOLDMONT: + case INTEL_ATOM_GOLDMONT_D: memcpy(hw_cache_event_ids, glm_hw_cache_event_ids, sizeof(hw_cache_event_ids)); memcpy(hw_cache_extra_regs, glm_hw_cache_extra_regs, @@ -6369,7 +6369,7 @@ __init int intel_pmu_init(void) name =3D "goldmont"; break; =20 - case INTEL_FAM6_ATOM_GOLDMONT_PLUS: + case INTEL_ATOM_GOLDMONT_PLUS: memcpy(hw_cache_event_ids, glp_hw_cache_event_ids, sizeof(hw_cache_event_ids)); memcpy(hw_cache_extra_regs, glp_hw_cache_extra_regs, @@ -6398,9 +6398,9 @@ __init int intel_pmu_init(void) name =3D "goldmont_plus"; break; =20 - case INTEL_FAM6_ATOM_TREMONT_D: - case INTEL_FAM6_ATOM_TREMONT: - case INTEL_FAM6_ATOM_TREMONT_L: + case INTEL_ATOM_TREMONT_D: + case INTEL_ATOM_TREMONT: + case INTEL_ATOM_TREMONT_L: x86_pmu.late_ack =3D true; memcpy(hw_cache_event_ids, glp_hw_cache_event_ids, sizeof(hw_cache_event_ids)); @@ -6427,7 +6427,7 @@ __init int intel_pmu_init(void) name =3D "Tremont"; break; =20 - case INTEL_FAM6_ATOM_GRACEMONT: + case INTEL_ATOM_GRACEMONT: intel_pmu_init_grt(NULL); intel_pmu_pebs_data_source_grt(); x86_pmu.pebs_latency_data =3D adl_latency_data_small; @@ -6439,8 +6439,8 @@ __init int intel_pmu_init(void) name =3D "gracemont"; break; =20 - case INTEL_FAM6_ATOM_CRESTMONT: - case INTEL_FAM6_ATOM_CRESTMONT_X: + case INTEL_ATOM_CRESTMONT: + case INTEL_ATOM_CRESTMONT_X: intel_pmu_init_grt(NULL); x86_pmu.extra_regs =3D intel_cmt_extra_regs; intel_pmu_pebs_data_source_cmt(); @@ -6453,9 +6453,9 @@ __init int intel_pmu_init(void) name =3D "crestmont"; break; =20 - case INTEL_FAM6_WESTMERE: - case INTEL_FAM6_WESTMERE_EP: - case INTEL_FAM6_WESTMERE_EX: + case INTEL_WESTMERE: + case INTEL_WESTMERE_EP: + case INTEL_WESTMERE_EX: memcpy(hw_cache_event_ids, westmere_hw_cache_event_ids, sizeof(hw_cache_event_ids)); memcpy(hw_cache_extra_regs, nehalem_hw_cache_extra_regs, @@ -6484,8 +6484,8 @@ __init int intel_pmu_init(void) name =3D "westmere"; break; =20 - case INTEL_FAM6_SANDYBRIDGE: - case INTEL_FAM6_SANDYBRIDGE_X: + case INTEL_SANDYBRIDGE: + case INTEL_SANDYBRIDGE_X: x86_add_quirk(intel_sandybridge_quirk); x86_add_quirk(intel_ht_bug); memcpy(hw_cache_event_ids, snb_hw_cache_event_ids, @@ -6498,7 +6498,7 @@ __init int intel_pmu_init(void) x86_pmu.event_constraints =3D intel_snb_event_constraints; x86_pmu.pebs_constraints =3D intel_snb_pebs_event_constraints; x86_pmu.pebs_aliases =3D intel_pebs_aliases_snb; - if (boot_cpu_data.x86_model =3D=3D INTEL_FAM6_SANDYBRIDGE_X) + if (boot_cpu_data.x86_vfm =3D=3D INTEL_SANDYBRIDGE_X) x86_pmu.extra_regs =3D intel_snbep_extra_regs; else x86_pmu.extra_regs =3D intel_snb_extra_regs; @@ -6524,8 +6524,8 @@ __init int intel_pmu_init(void) name =3D "sandybridge"; break; =20 - case INTEL_FAM6_IVYBRIDGE: - case INTEL_FAM6_IVYBRIDGE_X: + case INTEL_IVYBRIDGE: + case INTEL_IVYBRIDGE_X: x86_add_quirk(intel_ht_bug); memcpy(hw_cache_event_ids, snb_hw_cache_event_ids, sizeof(hw_cache_event_ids)); @@ -6541,7 +6541,7 @@ __init int intel_pmu_init(void) x86_pmu.pebs_constraints =3D intel_ivb_pebs_event_constraints; x86_pmu.pebs_aliases =3D intel_pebs_aliases_ivb; x86_pmu.pebs_prec_dist =3D true; - if (boot_cpu_data.x86_model =3D=3D INTEL_FAM6_IVYBRIDGE_X) + if (boot_cpu_data.x86_vfm =3D=3D INTEL_IVYBRIDGE_X) x86_pmu.extra_regs =3D intel_snbep_extra_regs; else x86_pmu.extra_regs =3D intel_snb_extra_regs; @@ -6563,10 +6563,10 @@ __init int intel_pmu_init(void) break; =20 =20 - case INTEL_FAM6_HASWELL: - case INTEL_FAM6_HASWELL_X: - case INTEL_FAM6_HASWELL_L: - case INTEL_FAM6_HASWELL_G: + case INTEL_HASWELL: + case INTEL_HASWELL_X: + case INTEL_HASWELL_L: + case INTEL_HASWELL_G: x86_add_quirk(intel_ht_bug); x86_add_quirk(intel_pebs_isolation_quirk); x86_pmu.late_ack =3D true; @@ -6596,10 +6596,10 @@ __init int intel_pmu_init(void) name =3D "haswell"; break; =20 - case INTEL_FAM6_BROADWELL: - case INTEL_FAM6_BROADWELL_D: - case INTEL_FAM6_BROADWELL_G: - case INTEL_FAM6_BROADWELL_X: + case INTEL_BROADWELL: + case INTEL_BROADWELL_D: + case INTEL_BROADWELL_G: + case INTEL_BROADWELL_X: x86_add_quirk(intel_pebs_isolation_quirk); x86_pmu.late_ack =3D true; memcpy(hw_cache_event_ids, hsw_hw_cache_event_ids, sizeof(hw_cache_event= _ids)); @@ -6638,8 +6638,8 @@ __init int intel_pmu_init(void) name =3D "broadwell"; break; =20 - case INTEL_FAM6_XEON_PHI_KNL: - case INTEL_FAM6_XEON_PHI_KNM: + case INTEL_XEON_PHI_KNL: + case INTEL_XEON_PHI_KNM: memcpy(hw_cache_event_ids, slm_hw_cache_event_ids, sizeof(hw_cache_event_ids)); memcpy(hw_cache_extra_regs, @@ -6658,15 +6658,15 @@ __init int intel_pmu_init(void) name =3D "knights-landing"; break; =20 - case INTEL_FAM6_SKYLAKE_X: + case INTEL_SKYLAKE_X: pmem =3D true; fallthrough; - case INTEL_FAM6_SKYLAKE_L: - case INTEL_FAM6_SKYLAKE: - case INTEL_FAM6_KABYLAKE_L: - case INTEL_FAM6_KABYLAKE: - case INTEL_FAM6_COMETLAKE_L: - case INTEL_FAM6_COMETLAKE: + case INTEL_SKYLAKE_L: + case INTEL_SKYLAKE: + case INTEL_KABYLAKE_L: + case INTEL_KABYLAKE: + case INTEL_COMETLAKE_L: + case INTEL_COMETLAKE: x86_add_quirk(intel_pebs_isolation_quirk); x86_pmu.late_ack =3D true; memcpy(hw_cache_event_ids, skl_hw_cache_event_ids, sizeof(hw_cache_event= _ids)); @@ -6715,16 +6715,16 @@ __init int intel_pmu_init(void) name =3D "skylake"; break; =20 - case INTEL_FAM6_ICELAKE_X: - case INTEL_FAM6_ICELAKE_D: + case INTEL_ICELAKE_X: + case INTEL_ICELAKE_D: x86_pmu.pebs_ept =3D 1; pmem =3D true; fallthrough; - case INTEL_FAM6_ICELAKE_L: - case INTEL_FAM6_ICELAKE: - case INTEL_FAM6_TIGERLAKE_L: - case INTEL_FAM6_TIGERLAKE: - case INTEL_FAM6_ROCKETLAKE: + case INTEL_ICELAKE_L: + case INTEL_ICELAKE: + case INTEL_TIGERLAKE_L: + case INTEL_TIGERLAKE: + case INTEL_ROCKETLAKE: x86_pmu.late_ack =3D true; memcpy(hw_cache_event_ids, skl_hw_cache_event_ids, sizeof(hw_cache_event= _ids)); memcpy(hw_cache_extra_regs, skl_hw_cache_extra_regs, sizeof(hw_cache_ext= ra_regs)); @@ -6759,13 +6759,13 @@ __init int intel_pmu_init(void) name =3D "icelake"; break; =20 - case INTEL_FAM6_SAPPHIRERAPIDS_X: - case INTEL_FAM6_EMERALDRAPIDS_X: + case INTEL_SAPPHIRERAPIDS_X: + case INTEL_EMERALDRAPIDS_X: x86_pmu.flags |=3D PMU_FL_MEM_LOADS_AUX; x86_pmu.extra_regs =3D intel_glc_extra_regs; fallthrough; - case INTEL_FAM6_GRANITERAPIDS_X: - case INTEL_FAM6_GRANITERAPIDS_D: + case INTEL_GRANITERAPIDS_X: + case INTEL_GRANITERAPIDS_D: intel_pmu_init_glc(NULL); if (!x86_pmu.extra_regs) x86_pmu.extra_regs =3D intel_rwc_extra_regs; @@ -6783,11 +6783,11 @@ __init int intel_pmu_init(void) name =3D "sapphire_rapids"; break; =20 - case INTEL_FAM6_ALDERLAKE: - case INTEL_FAM6_ALDERLAKE_L: - case INTEL_FAM6_RAPTORLAKE: - case INTEL_FAM6_RAPTORLAKE_P: - case INTEL_FAM6_RAPTORLAKE_S: + case INTEL_ALDERLAKE: + case INTEL_ALDERLAKE_L: + case INTEL_RAPTORLAKE: + case INTEL_RAPTORLAKE_P: + case INTEL_RAPTORLAKE_S: /* * Alder Lake has 2 types of CPU, core and atom. * @@ -6845,8 +6845,8 @@ __init int intel_pmu_init(void) name =3D "alderlake_hybrid"; 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Peter Anvin" , Andy Shevchenko , Tony Luck , linux-kernel@vger.kernel.org, patches@lists.linux.dev Subject: [PATCH v4 45/71] x86/platform/intel-mid: Switch to new Intel CPU model defines Date: Wed, 24 Apr 2024 11:15:23 -0700 Message-ID: <20240424181523.42023-1-tony.luck@intel.com> X-Mailer: git-send-email 2.44.0 In-Reply-To: <20240424181245.41141-1-tony.luck@intel.com> References: <20240424181245.41141-1-tony.luck@intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" New CPU #defines encode vendor and family as well as model. Signed-off-by: Tony Luck Acked-by: Andy Shevchenko Acked-by: Hans de Goede --- arch/x86/platform/intel-mid/intel-mid.c | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/arch/x86/platform/intel-mid/intel-mid.c b/arch/x86/platform/in= tel-mid/intel-mid.c index 7be71c2cdc83..8b8173fb0a43 100644 --- a/arch/x86/platform/intel-mid/intel-mid.c +++ b/arch/x86/platform/intel-mid/intel-mid.c @@ -22,6 +22,7 @@ #include #include #include +#include #include #include #include @@ -55,9 +56,9 @@ static void __init intel_mid_time_init(void) =20 static void intel_mid_arch_setup(void) { - switch (boot_cpu_data.x86_model) { - case 0x3C: - case 0x4A: + switch (boot_cpu_data.x86_vfm) { + case INTEL_HASWELL: + case INTEL_ATOM_SILVERMONT_MID: x86_platform.legacy.rtc =3D 1; break; default: --=20 2.44.0 From nobody Sat Jul 11 15:40:01 2026 Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.19]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 85977184103 for ; Wed, 24 Apr 2024 18:15:26 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=192.198.163.19 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1713982528; cv=none; b=DHyvKWUR/MbnUlvlI6iptcw7oXI9/ZXMP+6Eshgq0OT1ZCPF31kcXA4ireD36ZRWr/mmSE0TUxy/VzkJFYJ/vorolRs3WwZNjDYmCzokt0FNtfknPmUFV4SfADVm8zLOEEGNOh1YzpFFlI5e8tDJ9k8hVE/0QN9ehgq2Yk0YX/o= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1713982528; c=relaxed/simple; bh=KWWRdUU5f5jfluH+XjQDN6u50z+YdtCCFs2TFHrBnZg=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=ENVwJqLvp0SIMD/nWofmM4LA1XI+2iV3j1nI37DrmJb60aFeDdVj5F5So6mBSEQE09dR0JdGuaB+imYp2UMPR1qxl2zHvOLA2tYdWyldc0cB0sFvM3komlPAnPHtYAxrO26Oo8XEBI7YHqc7wmS5fX1567A3pA9Em2/JWnU2EbY= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com; spf=pass smtp.mailfrom=intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=PJOH3V5m; arc=none smtp.client-ip=192.198.163.19 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="PJOH3V5m" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1713982526; x=1745518526; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=KWWRdUU5f5jfluH+XjQDN6u50z+YdtCCFs2TFHrBnZg=; b=PJOH3V5mGXNnefMXY0iP9ch3e499ofgsDOtlDL3WUjsvao/obfTjYawC 9cSwRg2l8ONMNYLeSsKzuanvjSlPnHbxELN7RvNWXPQJDS59pdQlfKLqw m7ENmtJaKcw5vy8BmXERn14VKix0yxuD3KdJJ8L2mrUSWKLswoBbXSCub 35wFjo5eg2olcWuwRDGzYbbPqZKuXyuycno38h4zAqywS3mCscCw4NW4Y 2UjulORWWL+s8enhVF29n5Y7p6dRSx7DjlvJ0hDAo6atVL0H5G1NrfWAv pwUUywjt5vEjEGjBUAlvgGPFKEb7BfvBGIEXSH5VVHiJdrrgeFsEPg7TY w==; X-CSE-ConnectionGUID: 9BMmsSpCTjyhL2qxtBZI9g== X-CSE-MsgGUID: rhPgeYUKQiKTb9uhifXLWQ== X-IronPort-AV: E=McAfee;i="6600,9927,11054"; a="9503581" X-IronPort-AV: E=Sophos;i="6.07,226,1708416000"; d="scan'208";a="9503581" Received: from orviesa002.jf.intel.com ([10.64.159.142]) by fmvoesa113.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 24 Apr 2024 11:15:25 -0700 X-CSE-ConnectionGUID: frX1FmZ/Q8+j9izbmvqBfw== X-CSE-MsgGUID: AfU7iprISOqMf9sUP5P87g== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.07,226,1708416000"; d="scan'208";a="55750156" Received: from agluck-desk3.sc.intel.com ([172.25.222.105]) by orviesa002-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 24 Apr 2024 11:15:25 -0700 From: Tony Luck To: Borislav Petkov , Thomas Gleixner , Ingo Molnar , Dave Hansen , x86@kernel.org Cc: "H. Peter Anvin" , =?UTF-8?q?Ilpo=20J=C3=A4rvinen?= , Johannes Stezenbach , Takashi Iwai , Tony Luck , linux-kernel@vger.kernel.org, patches@lists.linux.dev Subject: [PATCH v4 46/71] x86/platform/atom: Switch to new Intel CPU model defines Date: Wed, 24 Apr 2024 11:15:25 -0700 Message-ID: <20240424181525.42043-1-tony.luck@intel.com> X-Mailer: git-send-email 2.44.0 In-Reply-To: <20240424181245.41141-1-tony.luck@intel.com> References: <20240424181245.41141-1-tony.luck@intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" New CPU #defines encode vendor and family as well as model. Signed-off-by: Tony Luck Acked-by: Hans de Goede --- arch/x86/platform/atom/punit_atom_debug.c | 11 +++++------ 1 file changed, 5 insertions(+), 6 deletions(-) diff --git a/arch/x86/platform/atom/punit_atom_debug.c b/arch/x86/platform/= atom/punit_atom_debug.c index 6b9c6deca8ba..44c30ce6360a 100644 --- a/arch/x86/platform/atom/punit_atom_debug.c +++ b/arch/x86/platform/atom/punit_atom_debug.c @@ -165,14 +165,13 @@ static void punit_s2idle_check_register(struct punit_= device *punit_device) {} static void punit_s2idle_check_unregister(void) {} #endif =20 -#define X86_MATCH(model, data) \ - X86_MATCH_VENDOR_FAM_MODEL_FEATURE(INTEL, 6, INTEL_FAM6_##model, \ - X86_FEATURE_MWAIT, data) +#define X86_MATCH(vfm, data) \ + X86_MATCH_VFM_FEATURE(vfm, X86_FEATURE_MWAIT, data) =20 static const struct x86_cpu_id intel_punit_cpu_ids[] =3D { - X86_MATCH(ATOM_SILVERMONT, &punit_device_byt), - X86_MATCH(ATOM_SILVERMONT_MID, &punit_device_tng), - X86_MATCH(ATOM_AIRMONT, &punit_device_cht), + X86_MATCH(INTEL_ATOM_SILVERMONT, &punit_device_byt), + X86_MATCH(INTEL_ATOM_SILVERMONT_MID, &punit_device_tng), + X86_MATCH(INTEL_ATOM_AIRMONT, &punit_device_cht), {} }; MODULE_DEVICE_TABLE(x86cpu, intel_punit_cpu_ids); --=20 2.44.0 From nobody Sat Jul 11 15:40:01 2026 Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.19]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 54056194C75; Wed, 24 Apr 2024 18:15:28 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=192.198.163.19 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1713982530; cv=none; b=qW7PKnN4s4BYCXwKC9nJiXirjctPAA83U7k6vDdf54VcUVkkEoniYzTz7Efl7kw724632EIJJha39Q3VQyKGdM+3aztZA2/QGcYH2ib8O0wE/L4SK0xAoCPI+ghv7IStiMMTKNflGC8/EgF/BdNmIHkshAr3GWgEhOnak+2HN2s= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1713982530; c=relaxed/simple; bh=iSDmP+MytJ7eLJmAn34fXLBZm0qQmXA1YWZNK0YVPgs=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=Hur9fqncgjtu3gFzdQnx6hg1HDrfq/843syR6nRgReVA3bgups24UMIB3CoBIgqdWI2sCadnHaOzQIBhUFOg/hqBqN9VJU/P1vOu72YWRFcAEMoZeF46fzqCc+OjzAWsbTrL1Tf41qXVnvsW6zov8344XQ1Gug1XW0tVGNLZLcA= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com; spf=pass smtp.mailfrom=intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=nP+43LFC; arc=none smtp.client-ip=192.198.163.19 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="nP+43LFC" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1713982528; x=1745518528; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=iSDmP+MytJ7eLJmAn34fXLBZm0qQmXA1YWZNK0YVPgs=; b=nP+43LFChJSfGuwEUBKGdKjTRwoWBW18B1hiOKRXNiZ7u4BTiY5VzWKt fOotmbZCDrCIIrbXCatFOZuyuUU4bFUVnsA75quvUfzS8KShp8UGRjvS+ pHLetzdsEiEVlYvsU7DLm3rKNbp+GZMkOY1jvG7iytC2l1gYXoXhHcWzl dc1DxUOMHXbKK+/yh8YgTkGhdkqMGQv9+8KBHTW6/ZhwQkbdhzWEIqRXE dEIbVMIw9bPsT2u9wJwu4nQ1o8wLku7KOHjRxl3S/X4nG/bwFR6LWLRfu BxmLnzov2C08T+kgeEKXz5bH1ifNAeKVHU4sgsoBSVpvfx3z2ntM9cvOE Q==; X-CSE-ConnectionGUID: LUDkKGp6TeSPjH+yglt1Wg== X-CSE-MsgGUID: HyoqyaaSSfmLr2sXV1q8Zw== X-IronPort-AV: E=McAfee;i="6600,9927,11054"; a="9503596" X-IronPort-AV: E=Sophos;i="6.07,226,1708416000"; d="scan'208";a="9503596" Received: from orviesa002.jf.intel.com ([10.64.159.142]) by fmvoesa113.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 24 Apr 2024 11:15:27 -0700 X-CSE-ConnectionGUID: dyKn5rdOQSKtPHnYaNTl7Q== X-CSE-MsgGUID: 6soV4DYhRzqI7GH2rtN7Fw== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.07,226,1708416000"; d="scan'208";a="55750163" Received: from agluck-desk3.sc.intel.com ([172.25.222.105]) by orviesa002-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 24 Apr 2024 11:15:27 -0700 From: Tony Luck To: Borislav Petkov , Thomas Gleixner , Dave Hansen , x86@kernel.org Cc: Peter Zijlstra , Ingo Molnar , Arnaldo Carvalho de Melo , Namhyung Kim , Mark Rutland , Alexander Shishkin , Jiri Olsa , Ian Rogers , Adrian Hunter , "H. Peter Anvin" , Tony Luck , linux-perf-users@vger.kernel.org, linux-kernel@vger.kernel.org, patches@lists.linux.dev Subject: [PATCH v4 47/71] x86/cpu: Switch to new Intel CPU model defines Date: Wed, 24 Apr 2024 11:15:26 -0700 Message-ID: <20240424181526.42063-1-tony.luck@intel.com> X-Mailer: git-send-email 2.44.0 In-Reply-To: <20240424181245.41141-1-tony.luck@intel.com> References: <20240424181245.41141-1-tony.luck@intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" New CPU #defines encode vendor and family as well as model. Update INTEL_CPU_DESC() to work with vendor/family/model. Signed-off-by: Tony Luck Acked-by: Hans de Goede --- arch/x86/include/asm/cpu_device_id.h | 8 ++-- arch/x86/events/intel/core.c | 64 ++++++++++++++-------------- 2 files changed, 36 insertions(+), 36 deletions(-) diff --git a/arch/x86/include/asm/cpu_device_id.h b/arch/x86/include/asm/cp= u_device_id.h index 970a232009c3..cac33812c609 100644 --- a/arch/x86/include/asm/cpu_device_id.h +++ b/arch/x86/include/asm/cpu_device_id.h @@ -275,10 +275,10 @@ struct x86_cpu_desc { u32 x86_microcode_rev; }; =20 -#define INTEL_CPU_DESC(model, stepping, revision) { \ - .x86_family =3D 6, \ - .x86_vendor =3D X86_VENDOR_INTEL, \ - .x86_model =3D (model), \ +#define INTEL_CPU_DESC(vfm, stepping, revision) { \ + .x86_family =3D VFM_FAMILY(vfm), \ + .x86_vendor =3D VFM_VENDOR(vfm), \ + .x86_model =3D VFM_MODEL(vfm), \ .x86_stepping =3D (stepping), \ .x86_microcode_rev =3D (revision), \ } diff --git a/arch/x86/events/intel/core.c b/arch/x86/events/intel/core.c index 94206f8cd371..d3294ef18aef 100644 --- a/arch/x86/events/intel/core.c +++ b/arch/x86/events/intel/core.c @@ -5187,35 +5187,35 @@ static __init void intel_clovertown_quirk(void) } =20 static const struct x86_cpu_desc isolation_ucodes[] =3D { - INTEL_CPU_DESC(INTEL_FAM6_HASWELL, 3, 0x0000001f), - INTEL_CPU_DESC(INTEL_FAM6_HASWELL_L, 1, 0x0000001e), - INTEL_CPU_DESC(INTEL_FAM6_HASWELL_G, 1, 0x00000015), - INTEL_CPU_DESC(INTEL_FAM6_HASWELL_X, 2, 0x00000037), - INTEL_CPU_DESC(INTEL_FAM6_HASWELL_X, 4, 0x0000000a), - INTEL_CPU_DESC(INTEL_FAM6_BROADWELL, 4, 0x00000023), - INTEL_CPU_DESC(INTEL_FAM6_BROADWELL_G, 1, 0x00000014), - INTEL_CPU_DESC(INTEL_FAM6_BROADWELL_D, 2, 0x00000010), - INTEL_CPU_DESC(INTEL_FAM6_BROADWELL_D, 3, 0x07000009), - INTEL_CPU_DESC(INTEL_FAM6_BROADWELL_D, 4, 0x0f000009), - INTEL_CPU_DESC(INTEL_FAM6_BROADWELL_D, 5, 0x0e000002), - INTEL_CPU_DESC(INTEL_FAM6_BROADWELL_X, 1, 0x0b000014), - INTEL_CPU_DESC(INTEL_FAM6_SKYLAKE_X, 3, 0x00000021), - INTEL_CPU_DESC(INTEL_FAM6_SKYLAKE_X, 4, 0x00000000), - INTEL_CPU_DESC(INTEL_FAM6_SKYLAKE_X, 5, 0x00000000), - INTEL_CPU_DESC(INTEL_FAM6_SKYLAKE_X, 6, 0x00000000), - INTEL_CPU_DESC(INTEL_FAM6_SKYLAKE_X, 7, 0x00000000), - INTEL_CPU_DESC(INTEL_FAM6_SKYLAKE_X, 11, 0x00000000), - INTEL_CPU_DESC(INTEL_FAM6_SKYLAKE_L, 3, 0x0000007c), - INTEL_CPU_DESC(INTEL_FAM6_SKYLAKE, 3, 0x0000007c), - INTEL_CPU_DESC(INTEL_FAM6_KABYLAKE, 9, 0x0000004e), - INTEL_CPU_DESC(INTEL_FAM6_KABYLAKE_L, 9, 0x0000004e), - INTEL_CPU_DESC(INTEL_FAM6_KABYLAKE_L, 10, 0x0000004e), - INTEL_CPU_DESC(INTEL_FAM6_KABYLAKE_L, 11, 0x0000004e), - INTEL_CPU_DESC(INTEL_FAM6_KABYLAKE_L, 12, 0x0000004e), - INTEL_CPU_DESC(INTEL_FAM6_KABYLAKE, 10, 0x0000004e), - INTEL_CPU_DESC(INTEL_FAM6_KABYLAKE, 11, 0x0000004e), - INTEL_CPU_DESC(INTEL_FAM6_KABYLAKE, 12, 0x0000004e), - INTEL_CPU_DESC(INTEL_FAM6_KABYLAKE, 13, 0x0000004e), + INTEL_CPU_DESC(INTEL_HASWELL, 3, 0x0000001f), + INTEL_CPU_DESC(INTEL_HASWELL_L, 1, 0x0000001e), + INTEL_CPU_DESC(INTEL_HASWELL_G, 1, 0x00000015), + INTEL_CPU_DESC(INTEL_HASWELL_X, 2, 0x00000037), + INTEL_CPU_DESC(INTEL_HASWELL_X, 4, 0x0000000a), + INTEL_CPU_DESC(INTEL_BROADWELL, 4, 0x00000023), + INTEL_CPU_DESC(INTEL_BROADWELL_G, 1, 0x00000014), + INTEL_CPU_DESC(INTEL_BROADWELL_D, 2, 0x00000010), + INTEL_CPU_DESC(INTEL_BROADWELL_D, 3, 0x07000009), + INTEL_CPU_DESC(INTEL_BROADWELL_D, 4, 0x0f000009), + INTEL_CPU_DESC(INTEL_BROADWELL_D, 5, 0x0e000002), + INTEL_CPU_DESC(INTEL_BROADWELL_X, 1, 0x0b000014), + INTEL_CPU_DESC(INTEL_SKYLAKE_X, 3, 0x00000021), + INTEL_CPU_DESC(INTEL_SKYLAKE_X, 4, 0x00000000), + INTEL_CPU_DESC(INTEL_SKYLAKE_X, 5, 0x00000000), + INTEL_CPU_DESC(INTEL_SKYLAKE_X, 6, 0x00000000), + INTEL_CPU_DESC(INTEL_SKYLAKE_X, 7, 0x00000000), + INTEL_CPU_DESC(INTEL_SKYLAKE_X, 11, 0x00000000), + INTEL_CPU_DESC(INTEL_SKYLAKE_L, 3, 0x0000007c), + INTEL_CPU_DESC(INTEL_SKYLAKE, 3, 0x0000007c), + INTEL_CPU_DESC(INTEL_KABYLAKE, 9, 0x0000004e), + INTEL_CPU_DESC(INTEL_KABYLAKE_L, 9, 0x0000004e), + INTEL_CPU_DESC(INTEL_KABYLAKE_L, 10, 0x0000004e), + INTEL_CPU_DESC(INTEL_KABYLAKE_L, 11, 0x0000004e), + INTEL_CPU_DESC(INTEL_KABYLAKE_L, 12, 0x0000004e), + INTEL_CPU_DESC(INTEL_KABYLAKE, 10, 0x0000004e), + INTEL_CPU_DESC(INTEL_KABYLAKE, 11, 0x0000004e), + INTEL_CPU_DESC(INTEL_KABYLAKE, 12, 0x0000004e), + INTEL_CPU_DESC(INTEL_KABYLAKE, 13, 0x0000004e), {} }; =20 @@ -5232,9 +5232,9 @@ static __init void intel_pebs_isolation_quirk(void) } =20 static const struct x86_cpu_desc pebs_ucodes[] =3D { - INTEL_CPU_DESC(INTEL_FAM6_SANDYBRIDGE, 7, 0x00000028), - INTEL_CPU_DESC(INTEL_FAM6_SANDYBRIDGE_X, 6, 0x00000618), - INTEL_CPU_DESC(INTEL_FAM6_SANDYBRIDGE_X, 7, 0x0000070c), + INTEL_CPU_DESC(INTEL_SANDYBRIDGE, 7, 0x00000028), + INTEL_CPU_DESC(INTEL_SANDYBRIDGE_X, 6, 0x00000618), + INTEL_CPU_DESC(INTEL_SANDYBRIDGE_X, 7, 0x0000070c), {} }; =20 --=20 2.44.0 From nobody Sat Jul 11 15:40:01 2026 Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.19]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id DD42C199EA8 for ; Wed, 24 Apr 2024 18:15:28 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=192.198.163.19 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1713982530; cv=none; b=g9TfzmpSDzEo2ZAALn42k6PIc7INWepwsI2jAHZHzvJ/eDCuavrjHeTGlEfD2Odb+yNalridvUwCBibSUevyTeFDdRl5CA+Zm8BDSJmboocy2UxfxZOf4sHU0lSFanAvSFtIBWl4SWfXjXv2aMzgIk4WgiMR5LlR78+iIVup6/4= ARC-Message-Signature: i=1; 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d="scan'208";a="55750175" Received: from agluck-desk3.sc.intel.com ([172.25.222.105]) by orviesa002-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 24 Apr 2024 11:15:28 -0700 From: Tony Luck To: Borislav Petkov , Thomas Gleixner , Ingo Molnar , Dave Hansen , x86@kernel.org Cc: "H. Peter Anvin" , Tony Luck , linux-kernel@vger.kernel.org, patches@lists.linux.dev Subject: [PATCH v4 48/71] x86/boot: Switch to new Intel CPU model defines Date: Wed, 24 Apr 2024 11:15:28 -0700 Message-ID: <20240424181528.42083-1-tony.luck@intel.com> X-Mailer: git-send-email 2.44.0 In-Reply-To: <20240424181245.41141-1-tony.luck@intel.com> References: <20240424181245.41141-1-tony.luck@intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" New CPU #defines encode vendor and family as well as model but boot code doesn't have all the infrastucture to use them. Hard code the one CPU model number used here. Signed-off-by: Tony Luck Acked-by: Hans de Goede --- arch/x86/boot/cpucheck.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/x86/boot/cpucheck.c b/arch/x86/boot/cpucheck.c index fed8d13ce252..0aae4d4ed615 100644 --- a/arch/x86/boot/cpucheck.c +++ b/arch/x86/boot/cpucheck.c @@ -203,7 +203,7 @@ int check_knl_erratum(void) */ if (!is_intel() || cpu.family !=3D 6 || - cpu.model !=3D INTEL_FAM6_XEON_PHI_KNL) + cpu.model !=3D 0x57 /*INTEL_XEON_PHI_KNL*/) return 0; =20 /* --=20 2.44.0 From nobody Sat Jul 11 15:40:01 2026 Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.19]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 2FA421A0AEA; Wed, 24 Apr 2024 18:15:30 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=192.198.163.19 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1713982532; cv=none; b=JDeAkgkAwa+GQP22zfrGFNE1+4QHpitdVbYlw6yTz24IxOrEY6PT3SIg3qkoT2WxJY7pXBmoAKjZEzcpz8Aua8e+B/aCKC+RdvggAjJBbz4kArzURxSvoVr0gh5AJYwXiNzmp23eKMoK7sQweowmdbVT5QkyOBnNMnjVUgwU1ks= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1713982532; c=relaxed/simple; bh=/JbFqsT4QboTVC5nN5+7Tn0VrIVjmy0ALnM5ZmCJwqg=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=r/7bF/6WFMgjyPlBOHZ7vuoZzdKR3Gpb3rYPlYuuaOGVLDB00JMRBcAknmtL56BNfvbgxiEnf67Cpiv+wxAdiNXplSdKuIp+5SOgTF4C53RHjIgCF3xqE03jRy8M7KLBTYEuh1GnVr2dJoyWWQmZqyPNjioqUOkmu/V9QbKB/rI= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com; spf=pass smtp.mailfrom=intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=EDNsZDzX; arc=none smtp.client-ip=192.198.163.19 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="EDNsZDzX" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1713982530; x=1745518530; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=/JbFqsT4QboTVC5nN5+7Tn0VrIVjmy0ALnM5ZmCJwqg=; b=EDNsZDzXkw421EzYDI6azQd/yOjY80eTTFyDMspVDKf9aH9dQS4Yw7HC C/NUEP/NOgRBs7VVlw/JL6/9aFvz325yuBYkBn3ov66ccV/XPbhoQbZZQ uZH216nD2GGS82PTYympNl4dPeKAu8UYRTKXiCXJQfHApbwSY+Fe9NAjW +5QqwtSwPCo84Bv6BWS5P7pploWTFA2K/yfQGL0cJZKFHG8MQKHagtdAM lJFu0BIuE5optxot/aGyvu9u23x6A9Qh6TvWQ+8d0TERMpNLOQqEiFdlQ 3J5Ql9QguLe4JcQen5lVRyXOT+UpgIdZU33qRJrMjvqDx5q6nUXf/M4e2 Q==; X-CSE-ConnectionGUID: tGP756QYSOu7fWOwiq//bQ== X-CSE-MsgGUID: 1yW1RMvASOOsOrWb82X1AA== X-IronPort-AV: E=McAfee;i="6600,9927,11054"; a="9503615" X-IronPort-AV: E=Sophos;i="6.07,226,1708416000"; d="scan'208";a="9503615" Received: from orviesa002.jf.intel.com ([10.64.159.142]) by fmvoesa113.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 24 Apr 2024 11:15:29 -0700 X-CSE-ConnectionGUID: 8F3Pj9/7Ssm3iAKMJnNPNA== X-CSE-MsgGUID: 6usnF/5qRN2DTreFur4b0Q== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.07,226,1708416000"; d="scan'208";a="55750179" Received: from agluck-desk3.sc.intel.com ([172.25.222.105]) by orviesa002-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 24 Apr 2024 11:15:29 -0700 From: Tony Luck To: Borislav Petkov , Tony Luck Cc: James Morse , Mauro Carvalho Chehab , Robert Richter , linux-edac@vger.kernel.org, linux-kernel@vger.kernel.org, patches@lists.linux.dev Subject: [PATCH v4 49/71] EDAC/i10nm: Switch to new Intel CPU model defines Date: Wed, 24 Apr 2024 11:15:28 -0700 Message-ID: <20240424181529.42102-1-tony.luck@intel.com> X-Mailer: git-send-email 2.44.0 In-Reply-To: <20240424181245.41141-1-tony.luck@intel.com> References: <20240424181245.41141-1-tony.luck@intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" New CPU #defines encode vendor and family as well as model. Signed-off-by: Tony Luck Acked-by: Hans de Goede --- drivers/edac/i10nm_base.c | 20 ++++++++++---------- 1 file changed, 10 insertions(+), 10 deletions(-) diff --git a/drivers/edac/i10nm_base.c b/drivers/edac/i10nm_base.c index 3fd22a1eb1a9..24dd896d9a9d 100644 --- a/drivers/edac/i10nm_base.c +++ b/drivers/edac/i10nm_base.c @@ -942,16 +942,16 @@ static struct res_config gnr_cfg =3D { }; =20 static const struct x86_cpu_id i10nm_cpuids[] =3D { - X86_MATCH_INTEL_FAM6_MODEL_STEPPINGS(ATOM_TREMONT_D, X86_STEPPINGS(0x0, 0= x3), &i10nm_cfg0), - X86_MATCH_INTEL_FAM6_MODEL_STEPPINGS(ATOM_TREMONT_D, X86_STEPPINGS(0x4, 0= xf), &i10nm_cfg1), - X86_MATCH_INTEL_FAM6_MODEL_STEPPINGS(ICELAKE_X, X86_STEPPINGS(0x0, 0x3),= &i10nm_cfg0), - X86_MATCH_INTEL_FAM6_MODEL_STEPPINGS(ICELAKE_X, X86_STEPPINGS(0x4, 0xf),= &i10nm_cfg1), - X86_MATCH_INTEL_FAM6_MODEL_STEPPINGS(ICELAKE_D, X86_STEPPINGS(0x0, 0xf),= &i10nm_cfg1), - X86_MATCH_INTEL_FAM6_MODEL_STEPPINGS(SAPPHIRERAPIDS_X, X86_STEPPINGS(0x0,= 0xf), &spr_cfg), - X86_MATCH_INTEL_FAM6_MODEL_STEPPINGS(EMERALDRAPIDS_X, X86_STEPPINGS(0x0, = 0xf), &spr_cfg), - X86_MATCH_INTEL_FAM6_MODEL_STEPPINGS(GRANITERAPIDS_X, X86_STEPPINGS(0x0, = 0xf), &gnr_cfg), - X86_MATCH_INTEL_FAM6_MODEL_STEPPINGS(ATOM_CRESTMONT_X, X86_STEPPINGS(0x0,= 0xf), &gnr_cfg), - X86_MATCH_INTEL_FAM6_MODEL_STEPPINGS(ATOM_CRESTMONT, X86_STEPPINGS(0x0, 0= xf), &gnr_cfg), + X86_MATCH_VFM_STEPPINGS(INTEL_ATOM_TREMONT_D, X86_STEPPINGS(0x0, 0x3), &i= 10nm_cfg0), + X86_MATCH_VFM_STEPPINGS(INTEL_ATOM_TREMONT_D, X86_STEPPINGS(0x4, 0xf), &i= 10nm_cfg1), + X86_MATCH_VFM_STEPPINGS(INTEL_ICELAKE_X, X86_STEPPINGS(0x0, 0x3), &i10nm_= cfg0), + X86_MATCH_VFM_STEPPINGS(INTEL_ICELAKE_X, X86_STEPPINGS(0x4, 0xf), &i10nm_= cfg1), + X86_MATCH_VFM_STEPPINGS(INTEL_ICELAKE_D, X86_STEPPINGS(0x0, 0xf), &i10nm_= cfg1), + X86_MATCH_VFM_STEPPINGS(INTEL_SAPPHIRERAPIDS_X, X86_STEPPINGS(0x0, 0xf), = &spr_cfg), + X86_MATCH_VFM_STEPPINGS(INTEL_EMERALDRAPIDS_X, X86_STEPPINGS(0x0, 0xf), &= spr_cfg), + X86_MATCH_VFM_STEPPINGS(INTEL_GRANITERAPIDS_X, X86_STEPPINGS(0x0, 0xf), &= gnr_cfg), + X86_MATCH_VFM_STEPPINGS(INTEL_ATOM_CRESTMONT_X, X86_STEPPINGS(0x0, 0xf), = &gnr_cfg), + X86_MATCH_VFM_STEPPINGS(INTEL_ATOM_CRESTMONT, X86_STEPPINGS(0x0, 0xf), &g= nr_cfg), {} }; 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charset="utf-8" New CPU #defines encode vendor and family as well as model. Signed-off-by: Tony Luck Acked-by: Hans de Goede --- drivers/edac/pnd2_edac.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/edac/pnd2_edac.c b/drivers/edac/pnd2_edac.c index 2afcd148fcf8..f93f2f2b1cf2 100644 --- a/drivers/edac/pnd2_edac.c +++ b/drivers/edac/pnd2_edac.c @@ -1511,8 +1511,8 @@ static struct dunit_ops dnv_ops =3D { }; =20 static const struct x86_cpu_id pnd2_cpuids[] =3D { - X86_MATCH_INTEL_FAM6_MODEL(ATOM_GOLDMONT, &apl_ops), - X86_MATCH_INTEL_FAM6_MODEL(ATOM_GOLDMONT_D, &dnv_ops), + X86_MATCH_VFM(INTEL_ATOM_GOLDMONT, &apl_ops), + X86_MATCH_VFM(INTEL_ATOM_GOLDMONT_D, &dnv_ops), { } }; MODULE_DEVICE_TABLE(x86cpu, pnd2_cpuids); --=20 2.44.0 From nobody Sat Jul 11 15:40:01 2026 Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.19]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 079211BF6DB; Wed, 24 Apr 2024 18:15:32 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=192.198.163.19 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1713982534; cv=none; b=H1eVT1zuTrspSocWpQWIeThk1zUrNxq5sCbIypF6XXtQc4NAwQ7XIXkkv0CpCUMFisXODRnw17U15JMzSEVzGC4i0fGHZ9aCIdOhA7Jfdqjry5mOyN72/SYnoJousYGdy1/UKeNFQYFOTzZz4jdRoNQgUQC9X6xXyTavdy0P9Hs= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1713982534; c=relaxed/simple; bh=K0SMUkbNdaQTs8egvbi/pMmubWEho1P85u2CzO6rIlk=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=kU8cyKgwOD5LYMOnfdmJTmbkRNP+D8CTzCempNCwahZVrgyqAqjEedDncTGoYmwYxQsr96hCJabMgMPOrR8rUwTRcOmFo+BuCGatdXZI+8BfITd/rS05iYoR+a3uoiTtE2HKieiSS/6Lv0yAlLCy1yJ/jYxMiaT53E7ZEQ8i2KU= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com; spf=pass smtp.mailfrom=intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=gvU8zX4V; arc=none smtp.client-ip=192.198.163.19 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="gvU8zX4V" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1713982533; x=1745518533; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=K0SMUkbNdaQTs8egvbi/pMmubWEho1P85u2CzO6rIlk=; b=gvU8zX4VVCeFSjBz/8YQMcH+ADHLplw1CW7BOXWF4k3pIOaBGV2Ldx9+ DNEYyQ7AijIaJuP9B9Qh+LbNya4VV+ZWIpJZlnc3zCQAP2yAC9parTThs fvV2KYAqjf8QVx6eh5hC9bvu1jlV7fruXksqTwQyMe7pQ2t1vHbdIV9Bc ijxuX3pB9yve31huNBY7i5fxdl1EyezCl5xbZXNNi1xCTCUPEqwUIWuI0 75lvtwae3eyUHvr568CQdMIrbiJYxOOptJSyodLaVdN4UkgepT3/vCgk4 uLVkjvtI2FuPOGHPGX503/VYw0Qx0kiy34d92IrVfarnw5EvmPNctKGDP g==; X-CSE-ConnectionGUID: n7I3iF4fSrm7gYjMZC4wvw== X-CSE-MsgGUID: hSgwgAT5QsCYFD3qTUlqgg== X-IronPort-AV: E=McAfee;i="6600,9927,11054"; a="9503628" X-IronPort-AV: E=Sophos;i="6.07,226,1708416000"; d="scan'208";a="9503628" Received: from orviesa002.jf.intel.com ([10.64.159.142]) by fmvoesa113.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 24 Apr 2024 11:15:32 -0700 X-CSE-ConnectionGUID: cgQ6Am4URKWlRgWxPx5IMg== X-CSE-MsgGUID: BvzoA1NXSPOHzeCI+T9qUQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.07,226,1708416000"; d="scan'208";a="55750193" Received: from agluck-desk3.sc.intel.com ([172.25.222.105]) by orviesa002-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 24 Apr 2024 11:15:31 -0700 From: Tony Luck To: Borislav Petkov , Tony Luck Cc: Qiuxu Zhuo , James Morse , Mauro Carvalho Chehab , Robert Richter , linux-edac@vger.kernel.org, linux-kernel@vger.kernel.org, patches@lists.linux.dev Subject: [PATCH v4 51/71] EDAC/sb_edac: Switch to new Intel CPU model defines Date: Wed, 24 Apr 2024 11:15:30 -0700 Message-ID: <20240424181530.42140-1-tony.luck@intel.com> X-Mailer: git-send-email 2.44.0 In-Reply-To: <20240424181245.41141-1-tony.luck@intel.com> References: <20240424181245.41141-1-tony.luck@intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" New CPU #defines encode vendor and family as well as model. Signed-off-by: Tony Luck Acked-by: Hans de Goede --- drivers/edac/sb_edac.c | 14 +++++++------- 1 file changed, 7 insertions(+), 7 deletions(-) diff --git a/drivers/edac/sb_edac.c b/drivers/edac/sb_edac.c index 26cca5a9322d..cbc92d3683e6 100644 --- a/drivers/edac/sb_edac.c +++ b/drivers/edac/sb_edac.c @@ -3546,13 +3546,13 @@ static int sbridge_register_mci(struct sbridge_dev = *sbridge_dev, enum type type) } =20 static const struct x86_cpu_id sbridge_cpuids[] =3D { - X86_MATCH_INTEL_FAM6_MODEL(SANDYBRIDGE_X, &pci_dev_descr_sbridge_table), - X86_MATCH_INTEL_FAM6_MODEL(IVYBRIDGE_X, &pci_dev_descr_ibridge_table), - X86_MATCH_INTEL_FAM6_MODEL(HASWELL_X, &pci_dev_descr_haswell_table), - X86_MATCH_INTEL_FAM6_MODEL(BROADWELL_X, &pci_dev_descr_broadwell_table), - X86_MATCH_INTEL_FAM6_MODEL(BROADWELL_D, &pci_dev_descr_broadwell_table), - X86_MATCH_INTEL_FAM6_MODEL(XEON_PHI_KNL, &pci_dev_descr_knl_table), - X86_MATCH_INTEL_FAM6_MODEL(XEON_PHI_KNM, &pci_dev_descr_knl_table), + X86_MATCH_VFM(INTEL_SANDYBRIDGE_X, &pci_dev_descr_sbridge_table), + X86_MATCH_VFM(INTEL_IVYBRIDGE_X, &pci_dev_descr_ibridge_table), + X86_MATCH_VFM(INTEL_HASWELL_X, &pci_dev_descr_haswell_table), + X86_MATCH_VFM(INTEL_BROADWELL_X, &pci_dev_descr_broadwell_table), + X86_MATCH_VFM(INTEL_BROADWELL_D, &pci_dev_descr_broadwell_table), + X86_MATCH_VFM(INTEL_XEON_PHI_KNL, &pci_dev_descr_knl_table), + X86_MATCH_VFM(INTEL_XEON_PHI_KNM, &pci_dev_descr_knl_table), { } }; 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charset="utf-8" New CPU #defines encode vendor and family as well as model. Signed-off-by: Tony Luck Acked-by: Hans de Goede --- drivers/edac/skx_base.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/edac/skx_base.c b/drivers/edac/skx_base.c index 0a862336a7ce..af3fa807acdb 100644 --- a/drivers/edac/skx_base.c +++ b/drivers/edac/skx_base.c @@ -164,7 +164,7 @@ static struct res_config skx_cfg =3D { }; =20 static const struct x86_cpu_id skx_cpuids[] =3D { - X86_MATCH_INTEL_FAM6_MODEL_STEPPINGS(SKYLAKE_X, X86_STEPPINGS(0x0, 0xf), = &skx_cfg), + X86_MATCH_VFM_STEPPINGS(INTEL_SKYLAKE_X, X86_STEPPINGS(0x0, 0xf), &skx_cf= g), { } }; MODULE_DEVICE_TABLE(x86cpu, skx_cpuids); --=20 2.44.0 From nobody Sat Jul 11 15:40:01 2026 Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.19]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id DB90F1C0DFD for ; Wed, 24 Apr 2024 18:15:34 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=192.198.163.19 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1713982536; cv=none; b=JHG2Ic2I8eRdcu7RqP5qONzMbGmL/YmFq9HbCRDG4T+qejsQeH+8GhwUZl/U6FiDQUEnIWbGKIb3ejVxzlmxhcWvT8gH38GARv/9rzdzI9OUPlZZMK1zIAWFO277KkwswvDcMtcUDcvdB1OJNj+KwysCE5lqJvTpwyhQCWak1MM= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1713982536; c=relaxed/simple; bh=xK5hwg6ILPkC2v4d4nuHc6WucRElJH7HgJqquuK12yY=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=hb0g8LybFE0kYJzJeWYdfbw5Uen+kdI9ZXDmkpEoms/XNGGlrueOJumsoYhfd5YrA39mMLTptzrrqHBD01fUWGqPwIKI2OJipBRnCM/CZiLlTDooetxki9BbUE/hrbj8OwGuvqfckOPACZpOMQMkNdbeEfBTFQXYP+QFDjMaruQ= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com; spf=pass smtp.mailfrom=intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=F/jpg0t4; arc=none smtp.client-ip=192.198.163.19 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="F/jpg0t4" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1713982535; x=1745518535; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=xK5hwg6ILPkC2v4d4nuHc6WucRElJH7HgJqquuK12yY=; b=F/jpg0t4vTwEpKlznAESztsUeBlVK3ro1IHap8nAgPwoS1cjes94QiZt qGRobq71EH+p5i7f25BgfmL5ggjVfCQ5vXmLlDeOVfrkK0FT49AIZY8qQ 8Wh9gU2CR/KLvmyQwlsCIk0teVNSuvx3nbHnIsBqjTB0s+SX2eReve/MN xYf3yHyrgp9nWfQprO8okmHkopt111ySsxdvNHwPSHo5YGsJIAWsakbcT xicwkaWFFeysf0z2lah/GN7i3HoK0TP68Vkz1BAtgWF+roiYOLZZhYa/J 1KeX4RdxAIrYXTd8TDef6U/eejUxwj8DbfXAOdbDmKdPK3t2o2DtDPPNf Q==; X-CSE-ConnectionGUID: vL8Smqe/Ri+Csd+HLn1Wgw== X-CSE-MsgGUID: zoPAOcR/RGaEPGaWBFETGA== X-IronPort-AV: E=McAfee;i="6600,9927,11054"; a="9503640" X-IronPort-AV: E=Sophos;i="6.07,226,1708416000"; d="scan'208";a="9503640" Received: from orviesa002.jf.intel.com ([10.64.159.142]) by fmvoesa113.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 24 Apr 2024 11:15:33 -0700 X-CSE-ConnectionGUID: g73wVqPSR2S9jaEoDl2w+g== X-CSE-MsgGUID: 7OARLnhRQjGS6vNr5SQNMA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.07,226,1708416000"; d="scan'208";a="55750215" Received: from agluck-desk3.sc.intel.com ([172.25.222.105]) by orviesa002-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 24 Apr 2024 11:15:33 -0700 From: Tony Luck To: Borislav Petkov , MyungJoo Ham , Chanwoo Choi , Hans de Goede , Chen-Yu Tsai Cc: linux-kernel@vger.kernel.org, patches@lists.linux.dev, Tony Luck Subject: [PATCH v4 53/71] extcon: axp288: Switch to new Intel CPU model defines Date: Wed, 24 Apr 2024 11:15:32 -0700 Message-ID: <20240424181532.42178-1-tony.luck@intel.com> X-Mailer: git-send-email 2.44.0 In-Reply-To: <20240424181245.41141-1-tony.luck@intel.com> References: <20240424181245.41141-1-tony.luck@intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" New CPU #defines encode vendor and family as well as model. Signed-off-by: Tony Luck Acked-by: Chanwoo Choi Acked-by: Hans de Goede --- drivers/extcon/extcon-axp288.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/extcon/extcon-axp288.c b/drivers/extcon/extcon-axp288.c index a703a8315634..d3bcbe839c09 100644 --- a/drivers/extcon/extcon-axp288.c +++ b/drivers/extcon/extcon-axp288.c @@ -108,7 +108,7 @@ struct axp288_extcon_info { }; =20 static const struct x86_cpu_id cherry_trail_cpu_ids[] =3D { - X86_MATCH_INTEL_FAM6_MODEL(ATOM_AIRMONT, NULL), + X86_MATCH_VFM(INTEL_ATOM_AIRMONT, NULL), {} }; =20 --=20 2.44.0 From nobody Sat Jul 11 15:40:01 2026 Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.19]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 3CE561C230A for ; Wed, 24 Apr 2024 18:15:35 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=192.198.163.19 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1713982536; cv=none; b=hmeH+IwHpDpVm/Dm0P9r+aTvW86QcNVCuy8zQIS1UKXrm8zd8OFU6GlMln6Scu/YdkOae/yUtfBcR5ZAFk1lrHjLQsceOGHe+MKjBdsrxMF8Tagu9iV+fDkhVJCJ6nPgWSasAo81NhmE7qnn5ZNSK8+gmg8q3PxC0VIjs1H+dXw= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1713982536; c=relaxed/simple; bh=t/ao4kMQjvb5Oyj2NN7I0cbLAgUqp9G5mS37WgG/glA=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=XOfpXH8Q9T4HUkJ/J2o/EkSuBwblO/8KpPTA6bv84OHU65ZombsjuAEwz3MZ7HeF8v9Xl7E1YmEAOeKPAmDlP5g+HjENetFEF6fk7HfXB7coZavmg7n489bn8hxEE0Z1et5lErWtBGEKWxK87h7xle6tpHTap0KuiIfutBRQ+ME= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com; spf=pass smtp.mailfrom=intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=LtGrqj2N; arc=none smtp.client-ip=192.198.163.19 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="LtGrqj2N" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1713982535; x=1745518535; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=t/ao4kMQjvb5Oyj2NN7I0cbLAgUqp9G5mS37WgG/glA=; b=LtGrqj2NRIIMh7qdVB9m2pF8q2LFI+oqTtxlCCbTQEnUr4g5ASCqAqZA 2wbDDmhZeC+RJL+NKecYNSg8n192yCNJiNyfL+J1I/4zrcI3/i+XTaAio xW/FWGyudGnSxHY3g1x8SJYvkHPcdU51hqmdUyDcmDHtKzVWxehi5juf6 6J/r/EESe0jpiJd7OlcUeYE4NKwpryxBV+JDbVjCqRVQaVSL0PSKyIsBK XvUGe1vPTCqxZLvbN03WA7SmllAB/vhSWLhu/vklEGNH3s8kXrfGQtQC2 XF4IxG+q0YZ3Xw38IcZqFVwx1sAy9FdwB7MDkXGIw8FJDhqObzqWTiuAt g==; X-CSE-ConnectionGUID: SzZQE+XFSVycm7oqR34zjg== X-CSE-MsgGUID: Qwif9WryRhKBPzxuz+5LFA== X-IronPort-AV: E=McAfee;i="6600,9927,11054"; a="9503647" X-IronPort-AV: E=Sophos;i="6.07,226,1708416000"; d="scan'208";a="9503647" Received: from orviesa002.jf.intel.com ([10.64.159.142]) by fmvoesa113.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 24 Apr 2024 11:15:34 -0700 X-CSE-ConnectionGUID: Pm2usB6YTlyIertnoLSiOg== X-CSE-MsgGUID: zoV8luwyT2+F/Vz8ck2PuQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.07,226,1708416000"; d="scan'208";a="55750223" Received: from agluck-desk3.sc.intel.com ([172.25.222.105]) by orviesa002-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 24 Apr 2024 11:15:34 -0700 From: Tony Luck To: Borislav Petkov , linux-kernel@vger.kernel.org Cc: Iwona Winiarska , openbmc@lists.ozlabs.org, patches@lists.linux.dev, Tony Luck Subject: [PATCH v4 54/71] peci: cpu: Switch to new Intel CPU model defines Date: Wed, 24 Apr 2024 11:15:33 -0700 Message-ID: <20240424181533.42197-1-tony.luck@intel.com> X-Mailer: git-send-email 2.44.0 In-Reply-To: <20240424181245.41141-1-tony.luck@intel.com> References: <20240424181245.41141-1-tony.luck@intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" New CPU #defines encode vendor and family as well as model. N.B. Copy some macros from x86 and the X86_VENDOR_INTEL define from because this code can be built for BMC's that are not based on x86 so accessing those header files is problematic. Signed-off-by: Tony Luck Acked-by: Hans de Goede --- include/linux/peci-cpu.h | 24 ++++++++++++++++++++++++ drivers/peci/cpu.c | 28 ++++++++++++++-------------- 2 files changed, 38 insertions(+), 14 deletions(-) diff --git a/include/linux/peci-cpu.h b/include/linux/peci-cpu.h index ff8ae9c26c80..601cdd086bf6 100644 --- a/include/linux/peci-cpu.h +++ b/include/linux/peci-cpu.h @@ -6,6 +6,30 @@ =20 #include =20 +/* Copied from x86 */ +#define X86_VENDOR_INTEL 0 + +/* Copied from x86 */ +#define VFM_MODEL_BIT 0 +#define VFM_FAMILY_BIT 8 +#define VFM_VENDOR_BIT 16 +#define VFM_RSVD_BIT 24 + +#define VFM_MODEL_MASK GENMASK(VFM_FAMILY_BIT - 1, VFM_MODEL_BIT) +#define VFM_FAMILY_MASK GENMASK(VFM_VENDOR_BIT - 1, VFM_FAMILY_BIT) +#define VFM_VENDOR_MASK GENMASK(VFM_RSVD_BIT - 1, VFM_VENDOR_BIT) + +#define VFM_MODEL(vfm) (((vfm) & VFM_MODEL_MASK) >> VFM_MODEL_BIT) +#define VFM_FAMILY(vfm) (((vfm) & VFM_FAMILY_MASK) >> VFM_FAMILY_BIT) +#define VFM_VENDOR(vfm) (((vfm) & VFM_VENDOR_MASK) >> VFM_VENDOR_BIT) + +#define VFM_MAKE(_vendor, _family, _model) ( \ + ((_model) << VFM_MODEL_BIT) | \ + ((_family) << VFM_FAMILY_BIT) | \ + ((_vendor) << VFM_VENDOR_BIT) \ +) +/* End of copied code */ + #include "../../arch/x86/include/asm/intel-family.h" =20 #define PECI_PCS_PKG_ID 0 /* Package Identifier Read */ diff --git a/drivers/peci/cpu.c b/drivers/peci/cpu.c index bd990acd92b8..8e8292c05551 100644 --- a/drivers/peci/cpu.c +++ b/drivers/peci/cpu.c @@ -294,38 +294,38 @@ peci_cpu_probe(struct peci_device *device, const stru= ct peci_device_id *id) =20 static const struct peci_device_id peci_cpu_device_ids[] =3D { { /* Haswell Xeon */ - .family =3D 6, - .model =3D INTEL_FAM6_HASWELL_X, + .family =3D VFM_FAMILY(INTEL_HASWELL_X), + .model =3D VFM_MODEL(INTEL_HASWELL_X), .data =3D "hsx", }, { /* Broadwell Xeon */ - .family =3D 6, - .model =3D INTEL_FAM6_BROADWELL_X, + .family =3D VFM_FAMILY(INTEL_BROADWELL_X), + .model =3D VFM_MODEL(INTEL_BROADWELL_X), .data =3D "bdx", }, { /* Broadwell Xeon D */ - .family =3D 6, - .model =3D INTEL_FAM6_BROADWELL_D, + .family =3D VFM_FAMILY(INTEL_BROADWELL_D), + .model =3D VFM_MODEL(INTEL_BROADWELL_D), .data =3D "bdxd", }, { /* Skylake Xeon */ - .family =3D 6, - .model =3D INTEL_FAM6_SKYLAKE_X, + .family =3D VFM_FAMILY(INTEL_SKYLAKE_X), + .model =3D VFM_MODEL(INTEL_SKYLAKE_X), .data =3D "skx", }, { /* Icelake Xeon */ - .family =3D 6, - .model =3D INTEL_FAM6_ICELAKE_X, + .family =3D VFM_FAMILY(INTEL_ICELAKE_X), + .model =3D VFM_MODEL(INTEL_ICELAKE_X), .data =3D "icx", }, { /* Icelake Xeon D */ - .family =3D 6, - .model =3D INTEL_FAM6_ICELAKE_D, + .family =3D VFM_FAMILY(INTEL_ICELAKE_D), + .model =3D VFM_MODEL(INTEL_ICELAKE_D), .data =3D "icxd", }, { /* Sapphire Rapids Xeon */ - .family =3D 6, - .model =3D INTEL_FAM6_SAPPHIRERAPIDS_X, + .family =3D VFM_FAMILY(INTEL_SAPPHIRERAPIDS_X), + .model =3D VFM_MODEL(INTEL_SAPPHIRERAPIDS_X), .data =3D "spr", }, { } --=20 2.44.0 From nobody Sat Jul 11 15:40:01 2026 Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.19]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B5F3E194C75; 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charset="utf-8" New CPU #defines encode vendor and family as well as model. Signed-off-by: Tony Luck Acked-by: Guenter Roeck Acked-by: Hans de Goede --- drivers/hwmon/peci/cputemp.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/hwmon/peci/cputemp.c b/drivers/hwmon/peci/cputemp.c index a812c15948d9..e8dafa748a41 100644 --- a/drivers/hwmon/peci/cputemp.c +++ b/drivers/hwmon/peci/cputemp.c @@ -361,9 +361,9 @@ static int init_core_mask(struct peci_cputemp *priv) =20 /* Get the RESOLVED_CORES register value */ switch (peci_dev->info.model) { - case INTEL_FAM6_ICELAKE_X: - case INTEL_FAM6_ICELAKE_D: - case INTEL_FAM6_SAPPHIRERAPIDS_X: + case VFM_MODEL(INTEL_ICELAKE_X): + case VFM_MODEL(INTEL_ICELAKE_D): + case VFM_MODEL(INTEL_SAPPHIRERAPIDS_X): ret =3D peci_ep_pci_local_read(peci_dev, 0, reg->bus, reg->dev, reg->func, reg->offset + 4, &data); if (ret) --=20 2.44.0 From nobody Sat Jul 11 15:40:01 2026 Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.19]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 6163F16EC1E; Wed, 24 Apr 2024 18:15:36 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=192.198.163.19 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1713982537; cv=none; b=BG5NHY4fdC56F8oSvndZ4ISIlWWklF5UDupyH2HsAm6y5aIOwZvP08+CvJqB98XEdkzf/tX6nRxChQcfuQXinz/RNdfyQqdWFdwOpbdLFEx0hlhxRzHcU1wUWKA1Dp/bCOeU9dK5smz6COy8GFuTlr27yjb7y75KdJ++Pb9kwkE= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1713982537; c=relaxed/simple; bh=26W7AK4Uyulx7e8OguFS/2MgsGW9fO1MZTL4z9xDJQs=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=cJJNp8gpErDfDhMKZqw862cd/Pgad+zViv1n7enkffRcK45wdH6txSPXgL+ty6RZzN1cgQo3Ultyizj3ecuUZtnRNa9QNuKGW8hwS9S9SDEziQnyrf1xCW2F6pPWg+Fakj+uT7bzEAaekN0xEE9AWZGjqBdoePmpLjGe7B2yhUk= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com; spf=pass smtp.mailfrom=intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=LZmNV8vB; arc=none smtp.client-ip=192.198.163.19 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="LZmNV8vB" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1713982536; x=1745518536; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=26W7AK4Uyulx7e8OguFS/2MgsGW9fO1MZTL4z9xDJQs=; b=LZmNV8vBqNBfcy9eQhepdO/nx4e8sMDeKoDCQePPPIsDHa/8fcsSmjo8 y+/uVSRf8Hsh8iIQU4nYU4D/Wn5Qk4lkFReRFFZlsw8EniBIRv+dTeKhJ wL6gQHoFlRd1/1yxMySV98Nu3Cep9KiNtWkuq28msy+DflsRaEx7LMym3 sF5DKyM7BYTH50dVbuEOVeskdZihQ0wQBUONn8NdIr94fZu9tX+cfPo7m fBwv39+cpgNOEUG7K64p6g/k5gaJR+svTgpSrNaemKM3rh+2vkvhE88qj E1DdFTTUe6POt4dECIRBBDZ41rjj7sTFIxbpqgYR7TRV7KUoUrrJ8GLz1 w==; X-CSE-ConnectionGUID: 9TsKiSfHTC2uItNPwX0IWA== X-CSE-MsgGUID: /Roi13xRTXKXlqS7ZteNwA== X-IronPort-AV: E=McAfee;i="6600,9927,11054"; a="9503662" X-IronPort-AV: E=Sophos;i="6.07,226,1708416000"; d="scan'208";a="9503662" Received: from orviesa002.jf.intel.com ([10.64.159.142]) by fmvoesa113.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 24 Apr 2024 11:15:36 -0700 X-CSE-ConnectionGUID: TpvtKG0xTJ2uPfmB6lYM4Q== X-CSE-MsgGUID: KiS/7+AmRAGQhXgz8JQpYg== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.07,226,1708416000"; d="scan'208";a="55750258" Received: from agluck-desk3.sc.intel.com ([172.25.222.105]) by orviesa002-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 24 Apr 2024 11:15:35 -0700 From: Tony Luck To: Borislav Petkov , Hans de Goede , =?UTF-8?q?Ilpo=20J=C3=A4rvinen?= Cc: platform-driver-x86@vger.kernel.org, linux-kernel@vger.kernel.org, patches@lists.linux.dev, Tony Luck Subject: [PATCH v4 56/71] platform/x86: intel_ips: Switch to new Intel CPU model defines Date: Wed, 24 Apr 2024 11:15:35 -0700 Message-ID: <20240424181535.42235-1-tony.luck@intel.com> X-Mailer: git-send-email 2.44.0 In-Reply-To: <20240424181245.41141-1-tony.luck@intel.com> References: <20240424181245.41141-1-tony.luck@intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" New CPU #defines encode vendor and family as well as model. Signed-off-by: Tony Luck Acked-by: Hans de Goede --- drivers/platform/x86/intel_ips.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/platform/x86/intel_ips.c b/drivers/platform/x86/intel_= ips.c index ba38649cc142..d95f686e0515 100644 --- a/drivers/platform/x86/intel_ips.c +++ b/drivers/platform/x86/intel_ips.c @@ -62,6 +62,7 @@ #include #include #include +#include #include "intel_ips.h" =20 #include @@ -1284,7 +1285,7 @@ static struct ips_mcp_limits *ips_detect_cpu(struct i= ps_driver *ips) struct ips_mcp_limits *limits =3D NULL; u16 tdp; =20 - if (!(boot_cpu_data.x86 =3D=3D 6 && boot_cpu_data.x86_model =3D=3D 37)) { + if (!(boot_cpu_data.x86_vfm =3D=3D INTEL_WESTMERE)) { dev_info(ips->dev, "Non-IPS CPU detected.\n"); return NULL; } --=20 2.44.0 From nobody Sat Jul 11 15:40:01 2026 Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.19]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 35F9116F0C1; Wed, 24 Apr 2024 18:15:37 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=192.198.163.19 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1713982538; cv=none; b=HGifzU/YElS2YUToKgOI/c+5ENDuQsK+MJmTfrjtr1HIR3xCkCAgUnTlx0pUac5p5ud51pDZIJoVG3G0VeeV1R5g4gGvEhLU3IxJOAM9Tw0JDG6gEwA7RKYLQtX5IE6uQFrbgAwbljBtp1zBrTkaFokT7qhssdEtTjrtYgFPHVs= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1713982538; c=relaxed/simple; bh=lMiePj5BLeBwTfmhtOWVl7Nr+Y6PBZ2sXOR4c241KGg=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=aAdvOee6YSIO/75aUCxZBx7IeKSsa08s9Ij7e0ZlVqgCcCHtNXgTN6N4Qq+d7tBnDECLymGeZA+zagvqM6yIV4+n0uv9rejvOXZCSQz95H83kZoknQSmBM1s0kkccymtFn33hXkeJEc2gH7feZ3Bm9kfDtyZV+Z70BFlAIW2fRc= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com; spf=pass smtp.mailfrom=intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=GoNyV2VL; arc=none smtp.client-ip=192.198.163.19 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="GoNyV2VL" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1713982537; x=1745518537; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=lMiePj5BLeBwTfmhtOWVl7Nr+Y6PBZ2sXOR4c241KGg=; b=GoNyV2VLtPQ8Py6GUFzIvcL7iushJBBV/rDNwHuGx2jZKtPaBK/eMQYv kpFwpWhSu2nf0MkWVydvvf3vQicKW0uJP3LfZEMo6vpRA7YRHHr0rRksc g3IWgyOQTOOsNJ6ODwxTXFsBakA+ibtlBOwRqYQsGaDnCDnCBONOeXVJK TAygUstHILnzUAPacIB7OE202v0XqFqqVFRD5xHIw2aqFPhWnI48ZlLw9 4QGiUOIqv7CKSYLWWp5+r2FSoFeLxByp2wuppkYbuKjTIydMJ4N5OMxX9 kv0fHkGg8GEirMJZLtMWSmqPDYaf5dyVo85nfsESWZtTzOjUH6IVItHPp A==; X-CSE-ConnectionGUID: +gU+dEzjQu+EYiiS8480aw== X-CSE-MsgGUID: R/iStO+YSpilWMHtGnkXXg== X-IronPort-AV: E=McAfee;i="6600,9927,11054"; a="9503665" X-IronPort-AV: E=Sophos;i="6.07,226,1708416000"; d="scan'208";a="9503665" Received: from orviesa002.jf.intel.com ([10.64.159.142]) by fmvoesa113.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 24 Apr 2024 11:15:37 -0700 X-CSE-ConnectionGUID: ieBqzDj+RyiG+d8oDjUmsQ== X-CSE-MsgGUID: eaYmgGRrQpCoSm0wRmwGBw== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.07,226,1708416000"; d="scan'208";a="55750286" Received: from agluck-desk3.sc.intel.com ([172.25.222.105]) by orviesa002-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 24 Apr 2024 11:15:36 -0700 From: Tony Luck To: Borislav Petkov , Rajneesh Bhardwaj , David E Box , Hans de Goede , =?UTF-8?q?Ilpo=20J=C3=A4rvinen?= Cc: platform-driver-x86@vger.kernel.org, linux-kernel@vger.kernel.org, patches@lists.linux.dev, Tony Luck Subject: [PATCH v4 57/71] platform/x86/intel/pmc: Switch to new Intel CPU model defines Date: Wed, 24 Apr 2024 11:15:36 -0700 Message-ID: <20240424181536.42254-1-tony.luck@intel.com> X-Mailer: git-send-email 2.44.0 In-Reply-To: <20240424181245.41141-1-tony.luck@intel.com> References: <20240424181245.41141-1-tony.luck@intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" New CPU #defines encode vendor and family as well as model. Signed-off-by: Tony Luck Acked-by: Hans de Goede --- drivers/platform/x86/intel/pmc/core.c | 46 +++++++++++++-------------- 1 file changed, 23 insertions(+), 23 deletions(-) diff --git a/drivers/platform/x86/intel/pmc/core.c b/drivers/platform/x86/i= ntel/pmc/core.c index 10c96c1a850a..054a56532e23 100644 --- a/drivers/platform/x86/intel/pmc/core.c +++ b/drivers/platform/x86/intel/pmc/core.c @@ -1255,29 +1255,29 @@ static void pmc_core_dbgfs_register(struct pmc_dev = *pmcdev) } =20 static const struct x86_cpu_id intel_pmc_core_ids[] =3D { - X86_MATCH_INTEL_FAM6_MODEL(SKYLAKE_L, spt_core_init), - X86_MATCH_INTEL_FAM6_MODEL(SKYLAKE, spt_core_init), - X86_MATCH_INTEL_FAM6_MODEL(KABYLAKE_L, spt_core_init), - X86_MATCH_INTEL_FAM6_MODEL(KABYLAKE, spt_core_init), - X86_MATCH_INTEL_FAM6_MODEL(CANNONLAKE_L, cnp_core_init), - X86_MATCH_INTEL_FAM6_MODEL(ICELAKE_L, icl_core_init), - X86_MATCH_INTEL_FAM6_MODEL(ICELAKE_NNPI, icl_core_init), - X86_MATCH_INTEL_FAM6_MODEL(COMETLAKE, cnp_core_init), - X86_MATCH_INTEL_FAM6_MODEL(COMETLAKE_L, cnp_core_init), - X86_MATCH_INTEL_FAM6_MODEL(TIGERLAKE_L, tgl_l_core_init), - X86_MATCH_INTEL_FAM6_MODEL(TIGERLAKE, tgl_core_init), - X86_MATCH_INTEL_FAM6_MODEL(ATOM_TREMONT, tgl_l_core_init), - X86_MATCH_INTEL_FAM6_MODEL(ATOM_TREMONT_L, icl_core_init), - X86_MATCH_INTEL_FAM6_MODEL(ROCKETLAKE, tgl_core_init), - X86_MATCH_INTEL_FAM6_MODEL(ALDERLAKE_L, tgl_l_core_init), - X86_MATCH_INTEL_FAM6_MODEL(ATOM_GRACEMONT, tgl_l_core_init), - X86_MATCH_INTEL_FAM6_MODEL(ALDERLAKE, adl_core_init), - X86_MATCH_INTEL_FAM6_MODEL(RAPTORLAKE_P, tgl_l_core_init), - X86_MATCH_INTEL_FAM6_MODEL(RAPTORLAKE, adl_core_init), - X86_MATCH_INTEL_FAM6_MODEL(RAPTORLAKE_S, adl_core_init), - X86_MATCH_INTEL_FAM6_MODEL(METEORLAKE_L, mtl_core_init), - X86_MATCH_INTEL_FAM6_MODEL(ARROWLAKE, arl_core_init), - X86_MATCH_INTEL_FAM6_MODEL(LUNARLAKE_M, lnl_core_init), + X86_MATCH_VFM(INTEL_SKYLAKE_L, spt_core_init), + X86_MATCH_VFM(INTEL_SKYLAKE, spt_core_init), + X86_MATCH_VFM(INTEL_KABYLAKE_L, spt_core_init), + X86_MATCH_VFM(INTEL_KABYLAKE, spt_core_init), + X86_MATCH_VFM(INTEL_CANNONLAKE_L, cnp_core_init), + X86_MATCH_VFM(INTEL_ICELAKE_L, icl_core_init), + X86_MATCH_VFM(INTEL_ICELAKE_NNPI, icl_core_init), + X86_MATCH_VFM(INTEL_COMETLAKE, cnp_core_init), + X86_MATCH_VFM(INTEL_COMETLAKE_L, cnp_core_init), + X86_MATCH_VFM(INTEL_TIGERLAKE_L, tgl_l_core_init), + X86_MATCH_VFM(INTEL_TIGERLAKE, tgl_core_init), + X86_MATCH_VFM(INTEL_ATOM_TREMONT, tgl_l_core_init), + X86_MATCH_VFM(INTEL_ATOM_TREMONT_L, icl_core_init), + X86_MATCH_VFM(INTEL_ROCKETLAKE, tgl_core_init), + X86_MATCH_VFM(INTEL_ALDERLAKE_L, tgl_l_core_init), + X86_MATCH_VFM(INTEL_ATOM_GRACEMONT, tgl_l_core_init), + X86_MATCH_VFM(INTEL_ALDERLAKE, adl_core_init), + X86_MATCH_VFM(INTEL_RAPTORLAKE_P, tgl_l_core_init), + X86_MATCH_VFM(INTEL_RAPTORLAKE, adl_core_init), + X86_MATCH_VFM(INTEL_RAPTORLAKE_S, adl_core_init), + X86_MATCH_VFM(INTEL_METEORLAKE_L, mtl_core_init), + X86_MATCH_VFM(INTEL_ARROWLAKE, arl_core_init), + X86_MATCH_VFM(INTEL_LUNARLAKE_M, lnl_core_init), {} }; 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charset="utf-8" New CPU #defines encode vendor and family as well as model. Signed-off-by: Tony Luck Acked-by: Hans de Goede --- drivers/platform/x86/intel/pmc/pltdrv.c | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) diff --git a/drivers/platform/x86/intel/pmc/pltdrv.c b/drivers/platform/x86= /intel/pmc/pltdrv.c index ddfba38c2104..22cfcd431987 100644 --- a/drivers/platform/x86/intel/pmc/pltdrv.c +++ b/drivers/platform/x86/intel/pmc/pltdrv.c @@ -35,14 +35,14 @@ static struct platform_device *pmc_core_device; * other list may grow, but this list should not. */ static const struct x86_cpu_id intel_pmc_core_platform_ids[] =3D { - X86_MATCH_INTEL_FAM6_MODEL(SKYLAKE_L, &pmc_core_device), - X86_MATCH_INTEL_FAM6_MODEL(SKYLAKE, &pmc_core_device), - X86_MATCH_INTEL_FAM6_MODEL(KABYLAKE_L, &pmc_core_device), - X86_MATCH_INTEL_FAM6_MODEL(KABYLAKE, &pmc_core_device), - X86_MATCH_INTEL_FAM6_MODEL(CANNONLAKE_L, &pmc_core_device), - X86_MATCH_INTEL_FAM6_MODEL(ICELAKE_L, &pmc_core_device), - X86_MATCH_INTEL_FAM6_MODEL(COMETLAKE, &pmc_core_device), - X86_MATCH_INTEL_FAM6_MODEL(COMETLAKE_L, &pmc_core_device), + X86_MATCH_VFM(INTEL_SKYLAKE_L, &pmc_core_device), + X86_MATCH_VFM(INTEL_SKYLAKE, &pmc_core_device), + X86_MATCH_VFM(INTEL_KABYLAKE_L, &pmc_core_device), + X86_MATCH_VFM(INTEL_KABYLAKE, &pmc_core_device), + X86_MATCH_VFM(INTEL_CANNONLAKE_L, &pmc_core_device), + X86_MATCH_VFM(INTEL_ICELAKE_L, &pmc_core_device), + X86_MATCH_VFM(INTEL_COMETLAKE, &pmc_core_device), + X86_MATCH_VFM(INTEL_COMETLAKE_L, &pmc_core_device), {} }; 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charset="utf-8" New CPU #defines encode vendor and family as well as model. Signed-off-by: Tony Luck Acked-by: Hans de Goede Reviewed-by: Kuppuswamy Sathyanarayanan --- drivers/platform/x86/intel_scu_wdt.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/platform/x86/intel_scu_wdt.c b/drivers/platform/x86/in= tel_scu_wdt.c index a5031a25632e..d0b6637861d3 100644 --- a/drivers/platform/x86/intel_scu_wdt.c +++ b/drivers/platform/x86/intel_scu_wdt.c @@ -50,7 +50,7 @@ static struct intel_mid_wdt_pdata tangier_pdata =3D { }; =20 static const struct x86_cpu_id intel_mid_cpu_ids[] =3D { - X86_MATCH_INTEL_FAM6_MODEL(ATOM_SILVERMONT_MID, &tangier_pdata), + X86_MATCH_VFM(INTEL_ATOM_SILVERMONT_MID, &tangier_pdata), {} }; =20 --=20 2.44.0 From nobody Sat Jul 11 15:40:01 2026 Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.19]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 64AB61C8FAE; Wed, 24 Apr 2024 18:15:40 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=192.198.163.19 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1713982541; cv=none; b=WPNgx9ewSssahaccjIjuPOrqHyYrb21qZJYrzZfBxFq8VyXBgE1eXUk2LHn7iC/vUPEbcyGRSFpumYRsp9MgvKnW/UZyh2bXLlCPDkGn8/4I7nH16znSezqcJfQLTk1dWqOZ3kKORg00sQTyLkx6LiWf+7KkDDVlbiTclRkoW0o= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1713982541; c=relaxed/simple; bh=zq3PVQPAcMWcn9vz87aBSrEUPTNktf+avk5R+71nh50=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=qcKyVNZTPfvERqLkBKk2oUYnrnr86RrG6WfQgXhBno6cMru+OdoTQqIs3Cjtb1z8XcVATg3oH+AO5XSPp9e3qyd1PrcenTvSoGrOI66BNz2nJ89PiJ33eKwqhPRdIh20WaPsNd/uCtPeBxgid9B5S4X6+V8dWEwiWM2638nNxwI= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com; spf=pass smtp.mailfrom=intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=J4ROe+QE; arc=none smtp.client-ip=192.198.163.19 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="J4ROe+QE" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1713982540; x=1745518540; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=zq3PVQPAcMWcn9vz87aBSrEUPTNktf+avk5R+71nh50=; b=J4ROe+QEUDlTYkQOBf2b6e+XC/sRAFCkm8h7OO9mmN39ALdLPH48TDO7 6jDEoCxzYw8rQpvVa57fLCQ8YeiCKGrJturf6P9CJmJbkxbxpSrUjeJuF 0xvWRrF1wEBsRHAp7KTQ7lHbwVLxNLeE80/TCG/XY+wGkhf6FdcwbqzH0 GtM22Eey29plslbl059Y97ai6q3qx985UK5erTUq03kaYFkyyyGJWDGqw 7+m0Vnjz9NtW9JJqfi16pJZ2EDBYd6kkl5L/o+cByKS/5439HDOZSaLH6 4o8Imw8HsuhUOsNC9jZhXDplV/iL+IZHofcWbr+BVg56Qkb5Qu9xSuqtJ g==; X-CSE-ConnectionGUID: O7AAwozaSgaCS2d6UShNaA== X-CSE-MsgGUID: 6To1xjM9SK6oShmHlkysvA== X-IronPort-AV: E=McAfee;i="6600,9927,11054"; a="9503685" X-IronPort-AV: E=Sophos;i="6.07,226,1708416000"; d="scan'208";a="9503685" Received: from orviesa002.jf.intel.com ([10.64.159.142]) by fmvoesa113.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 24 Apr 2024 11:15:39 -0700 X-CSE-ConnectionGUID: oVdKoGGKQtaObO59uusIfQ== X-CSE-MsgGUID: 1/zjBpQ8SWGxLILHsjFVdQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.07,226,1708416000"; d="scan'208";a="55750304" Received: from agluck-desk3.sc.intel.com ([172.25.222.105]) by orviesa002-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 24 Apr 2024 11:15:39 -0700 From: Tony Luck To: Borislav Petkov , Srinivas Pandruvada , Hans de Goede , =?UTF-8?q?Ilpo=20J=C3=A4rvinen?= Cc: platform-driver-x86@vger.kernel.org, linux-kernel@vger.kernel.org, patches@lists.linux.dev, Tony Luck Subject: [PATCH v4 60/71] platform/x86: ISST: Switch to new Intel CPU model defines Date: Wed, 24 Apr 2024 11:15:39 -0700 Message-ID: <20240424181539.42311-1-tony.luck@intel.com> X-Mailer: git-send-email 2.44.0 In-Reply-To: <20240424181245.41141-1-tony.luck@intel.com> References: <20240424181245.41141-1-tony.luck@intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" New CPU #defines encode vendor and family as well as model. Signed-off-by: Tony Luck Acked-by: Hans de Goede Acked-by: Srinivas Pandruvada --- drivers/platform/x86/intel/speed_select_if/isst_if_common.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/platform/x86/intel/speed_select_if/isst_if_common.c b/= drivers/platform/x86/intel/speed_select_if/isst_if_common.c index 08df9494603c..96f3b221b6c8 100644 --- a/drivers/platform/x86/intel/speed_select_if/isst_if_common.c +++ b/drivers/platform/x86/intel/speed_select_if/isst_if_common.c @@ -719,8 +719,8 @@ static struct miscdevice isst_if_char_driver =3D { }; =20 static const struct x86_cpu_id hpm_cpu_ids[] =3D { - X86_MATCH_INTEL_FAM6_MODEL(GRANITERAPIDS_X, NULL), - X86_MATCH_INTEL_FAM6_MODEL(ATOM_CRESTMONT_X, NULL), + X86_MATCH_VFM(INTEL_GRANITERAPIDS_X, NULL), + X86_MATCH_VFM(INTEL_ATOM_CRESTMONT_X, NULL), {} }; =20 --=20 2.44.0 From nobody Sat Jul 11 15:40:01 2026 Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.19]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id F124C1C9EA2; Wed, 24 Apr 2024 18:15:41 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=192.198.163.19 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1713982543; cv=none; b=N249SdG3vxs+TSmZkCP0HW59NI+uXpWy9zQhxMx0UKxUMUMMZmF8mgoO+POT6usQUOZONaz0R2CYAGdoYaIjeJKLF/ZFXD3Y/qBLbDt8JLwDrSP7G7gYtVMIcG/3r1KXaolrH+XOOwW8EwzcMrhOqhViTAANLUr4EM4a3utmXgk= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1713982543; c=relaxed/simple; bh=i5bcoBcmvU7uXKCZja5nQG8SX5zG7nFXavF27vF+S+o=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=RrUCRz+I6XnF4KnozuWJCgyiMt0WG0oXh/TvtQG7F5b9D7vVHt5rivBGuxGVGmDtj4PfivYn9IgHB+N5brpravRzoTlY4xOixW5fku2XlGi0fjn0VnzqW4gEycwc1P9vtqbbfl0cy2tKNMe52OKME/14K21G71xrAJF0FrBgp/o= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com; spf=pass smtp.mailfrom=intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=T2Af/BWh; arc=none smtp.client-ip=192.198.163.19 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="T2Af/BWh" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1713982542; x=1745518542; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=i5bcoBcmvU7uXKCZja5nQG8SX5zG7nFXavF27vF+S+o=; b=T2Af/BWhZ4pPZskSkHzLcZmzVJAEyYfG0bcQilEnhP+u6x5m9WdAndOW s2GsuMwca3TfXCQC3gcji+zxTEnHhY+v6mUOqgPzqOThnZjY8FC2oT2sz njij/CurHVI1j8eknz8oSBk6m9eEjVJr8RuaoEo1MwpSzMsu+AIozbO1Y 4VShgrhD0w2R+cA7QkAPVE8WhMu3JJ6atEdYwi+YcYerZ4hChGHgLFdvq jaT9lkrTOqiNrogsd2AdbTtDYnxe9x6i20vTENWcNJuzFi/QAIr4FlPpT cDEDs7GfvVYZJKsDzA2FlRDxIqDlvYnEI7OtIP3N4/bf1/vipSBud7KSG Q==; X-CSE-ConnectionGUID: fGsLIN9BTg+9bNPQEYZUjQ== X-CSE-MsgGUID: tlSXBgrWRM2/iwvoMJrRJQ== X-IronPort-AV: E=McAfee;i="6600,9927,11054"; a="9503691" X-IronPort-AV: E=Sophos;i="6.07,226,1708416000"; d="scan'208";a="9503691" Received: from orviesa002.jf.intel.com ([10.64.159.142]) by fmvoesa113.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 24 Apr 2024 11:15:40 -0700 X-CSE-ConnectionGUID: vv4dO+6LShGBxGm3l8f26A== X-CSE-MsgGUID: LP9lbvWLTHC4cdj+nEcVww== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.07,226,1708416000"; d="scan'208";a="55750309" Received: from agluck-desk3.sc.intel.com ([172.25.222.105]) by orviesa002-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 24 Apr 2024 11:15:40 -0700 From: Tony Luck To: Borislav Petkov , Srinivas Pandruvada , Hans de Goede , =?UTF-8?q?Ilpo=20J=C3=A4rvinen?= Cc: platform-driver-x86@vger.kernel.org, linux-kernel@vger.kernel.org, patches@lists.linux.dev, Tony Luck Subject: [PATCH v4 61/71] platform/x86: intel_speed_select_if: Switch to new Intel CPU model defines Date: Wed, 24 Apr 2024 11:15:40 -0700 Message-ID: <20240424181540.42330-1-tony.luck@intel.com> X-Mailer: git-send-email 2.44.0 In-Reply-To: <20240424181245.41141-1-tony.luck@intel.com> References: <20240424181245.41141-1-tony.luck@intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" New CPU #defines encode vendor and family as well as model. Signed-off-by: Tony Luck Acked-by: Hans de Goede Acked-by: Srinivas Pandruvada --- drivers/platform/x86/intel/speed_select_if/isst_if_mbox_msr.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/platform/x86/intel/speed_select_if/isst_if_mbox_msr.c = b/drivers/platform/x86/intel/speed_select_if/isst_if_mbox_msr.c index 1b6eab071068..6c36f7704fe7 100644 --- a/drivers/platform/x86/intel/speed_select_if/isst_if_mbox_msr.c +++ b/drivers/platform/x86/intel/speed_select_if/isst_if_mbox_msr.c @@ -161,7 +161,7 @@ static struct notifier_block isst_pm_nb =3D { }; =20 static const struct x86_cpu_id isst_if_cpu_ids[] =3D { - X86_MATCH_INTEL_FAM6_MODEL(SKYLAKE_X, NULL), + X86_MATCH_VFM(INTEL_SKYLAKE_X, NULL), {} }; MODULE_DEVICE_TABLE(x86cpu, isst_if_cpu_ids); --=20 2.44.0 From nobody Sat Jul 11 15:40:01 2026 Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.19]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 25C4416F0CE; Wed, 24 Apr 2024 18:15:42 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=192.198.163.19 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1713982543; cv=none; b=MF+urVn528l+2unrPOO9Oy5FpyKSLN/rRTI7gVkxlCAyk8zVIwEkbMK8/zOWfm3/q/sawiEiYJvzQW6RMMDNHip0lHFO/T2xds5+A0s5OOFCtKA7bc5FG4+G18hLPI1fc+++OV10dRExKNO2aWgDY73L46F1H2EhVYfNFNnA5PA= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1713982543; c=relaxed/simple; bh=xr6bb9OF0NXrEF0HgBC2BNEdfy38NpnLKwUrq7aiRyk=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=qDWuyRd11bZ7KiYGB3Bo+bIg2Hu+FSHHpYFdn3Qsvy52WDJ/p2yAp6tyEYylLxW9W9EuCnFJFRHahC1brM1HsTjrXZa1JpkBnoVWdXe6BHvTpAEMgKehor9ap0heRI0nYB2DAb8lW6tlzpFhnxgq/bKSM0pNNHirPKpNmaESBCs= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com; spf=pass smtp.mailfrom=intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=LKqJttDK; arc=none smtp.client-ip=192.198.163.19 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="LKqJttDK" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1713982542; x=1745518542; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=xr6bb9OF0NXrEF0HgBC2BNEdfy38NpnLKwUrq7aiRyk=; b=LKqJttDK9oNJhYMFvlFQRa4mF1/21CDCRBR+ZA06nC537UE4QmKhtZnf dxVvK4jA5dqMR9iXBtG3aYVSkJNWTbYWJ0bYYrxUx53u7WnGbLt+Wo5dY dxH3hQnuhl4GAYVrpPOixsuB11lloaqn6VoUSgiwee2cZyfJgA4lOIIRV 24yYURx2oprU7tUKIGudiPmmxvAA9gKMk7uyc9Zjbjr0Tcoz0vCeTfQ9I redWSoRsJE7IkdQLTKfAwHwGKq1iJZrTFTCTkVpH47pUn8lMQUQPP0z+l bR7t0QXzOpnolEgKvlyhmIuFpIOvwKRE66SjGc/KqJlLZpTlGaVa2+msd g==; X-CSE-ConnectionGUID: roFs/0MQSf6jKwXYXOxZkg== X-CSE-MsgGUID: BTvwKCOKT72p29IY2+RrOg== X-IronPort-AV: E=McAfee;i="6600,9927,11054"; a="9503700" X-IronPort-AV: E=Sophos;i="6.07,226,1708416000"; d="scan'208";a="9503700" Received: from orviesa002.jf.intel.com ([10.64.159.142]) by fmvoesa113.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 24 Apr 2024 11:15:41 -0700 X-CSE-ConnectionGUID: DFM+7oIXQaqCWdjnsJ+Khg== X-CSE-MsgGUID: fmDO2iL+S5aakTboRJ4C9w== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.07,226,1708416000"; d="scan'208";a="55750313" Received: from agluck-desk3.sc.intel.com ([172.25.222.105]) by orviesa002-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 24 Apr 2024 11:15:41 -0700 From: Tony Luck To: Borislav Petkov , Rajneesh Bhardwaj , "David E. Box" , Hans de Goede , =?UTF-8?q?Ilpo=20J=C3=A4rvinen?= Cc: platform-driver-x86@vger.kernel.org, linux-kernel@vger.kernel.org, patches@lists.linux.dev, Tony Luck Subject: [PATCH v4 62/71] platform/x86: intel_telemetry: Switch to new Intel CPU model defines Date: Wed, 24 Apr 2024 11:15:41 -0700 Message-ID: <20240424181541.42349-1-tony.luck@intel.com> X-Mailer: git-send-email 2.44.0 In-Reply-To: <20240424181245.41141-1-tony.luck@intel.com> References: <20240424181245.41141-1-tony.luck@intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" New CPU #defines encode vendor and family as well as model. Signed-off-by: Tony Luck Acked-by: Hans de Goede --- drivers/platform/x86/intel/telemetry/debugfs.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/platform/x86/intel/telemetry/debugfs.c b/drivers/platf= orm/x86/intel/telemetry/debugfs.c index 1d4d0fbfd63c..70e5736c44c7 100644 --- a/drivers/platform/x86/intel/telemetry/debugfs.c +++ b/drivers/platform/x86/intel/telemetry/debugfs.c @@ -308,8 +308,8 @@ static struct telemetry_debugfs_conf telem_apl_debugfs_= conf =3D { }; =20 static const struct x86_cpu_id telemetry_debugfs_cpu_ids[] =3D { - X86_MATCH_INTEL_FAM6_MODEL(ATOM_GOLDMONT, &telem_apl_debugfs_conf), - X86_MATCH_INTEL_FAM6_MODEL(ATOM_GOLDMONT_PLUS, &telem_apl_debugfs_conf), + X86_MATCH_VFM(INTEL_ATOM_GOLDMONT, &telem_apl_debugfs_conf), + X86_MATCH_VFM(INTEL_ATOM_GOLDMONT_PLUS, &telem_apl_debugfs_conf), {} }; MODULE_DEVICE_TABLE(x86cpu, telemetry_debugfs_cpu_ids); --=20 2.44.0 From nobody Sat Jul 11 15:40:01 2026 Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.19]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 6E6021C8FDA; Wed, 24 Apr 2024 18:15:43 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=192.198.163.19 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1713982545; cv=none; b=D9gjaUtyv3uC+tmOwAEdAz0nL8ptVUgOW+8UPsYbJu28Qerq8/8/eOUoGe9kEo0q1bjJO7n/AKmQHtb0UERQ5ILfaRpcZFsXb2WbCO4QRFcMz/kzSq27vZhQ4j2RXatNiBYtZ9MRR8RqOy1AD12oUjOCXDtJgJKqBk7WHQZf00A= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1713982545; c=relaxed/simple; bh=lGxY6/fpKVjagJiMiQslsjgDFgL5ZPdXodSr7eR0UbE=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=fDs/54858fiaRr6HDQTXT+vFaQFK8oHF8zv+JPTJWOegqXpRAaBs8o+FHhiT4q4VmiOab+MWdhmRDMQIsh/1JT11DbHDe/a99POKrX8U1GkiLzijgmyF+G0arwY7IxGdiwrmzwQDJAj2u+TTdNnj1Ju2xqjDXetQTYRroe7ccfU= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com; spf=pass smtp.mailfrom=intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=e8LnyUJO; arc=none smtp.client-ip=192.198.163.19 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="e8LnyUJO" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1713982543; x=1745518543; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=lGxY6/fpKVjagJiMiQslsjgDFgL5ZPdXodSr7eR0UbE=; b=e8LnyUJOEhhs7Iuow34O40EgnBvNbvdePbMtPl2b7qOCsFP7LCFOOche 52VVr7GqQEPZB3WouC61jKZHVTEpY601buw4Pg5QNXvioE7WMKQe7N7Q5 reVcuaPU2pRpGeXtfFl5z04fq9gDYFfu6k9j11RtVM4jPqxSCEUvrKKxc UICiqLzcZ1h5QlI3Us6k8p3THvIyXomL1vgFOUSl+r3/Is8p+8bjpLl2l Y7kjAz39jT6+mdj8m0SgsqAV+qd7W/c0KNmonhb3vHJ5Iq4jkUErnYukl F25MkB7THKxO8T6KatdRhS3ExZpOcgnECOL5VlNLt0674JGzrJq1oRN4t A==; X-CSE-ConnectionGUID: 3mLzCEvTQ8qlYhHK/vf4KQ== X-CSE-MsgGUID: 7KlF1o++ToG+3blqcDznpQ== X-IronPort-AV: E=McAfee;i="6600,9927,11054"; a="9503708" X-IronPort-AV: E=Sophos;i="6.07,226,1708416000"; d="scan'208";a="9503708" Received: from orviesa002.jf.intel.com ([10.64.159.142]) by fmvoesa113.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 24 Apr 2024 11:15:42 -0700 X-CSE-ConnectionGUID: Cad7/xTSRxy05dj+edwlJg== X-CSE-MsgGUID: MPlg/ATjQAixgaR1TFMaIg== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.07,226,1708416000"; d="scan'208";a="55750330" Received: from agluck-desk3.sc.intel.com ([172.25.222.105]) by orviesa002-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 24 Apr 2024 11:15:42 -0700 From: Tony Luck To: Borislav Petkov , Rajneesh Bhardwaj , "David E. Box" , Hans de Goede , =?UTF-8?q?Ilpo=20J=C3=A4rvinen?= Cc: platform-driver-x86@vger.kernel.org, linux-kernel@vger.kernel.org, patches@lists.linux.dev, Tony Luck Subject: [PATCH v4 63/71] platform/x86: intel: telemetry: Switch to new Intel CPU model defines Date: Wed, 24 Apr 2024 11:15:41 -0700 Message-ID: <20240424181541.42368-1-tony.luck@intel.com> X-Mailer: git-send-email 2.44.0 In-Reply-To: <20240424181245.41141-1-tony.luck@intel.com> References: <20240424181245.41141-1-tony.luck@intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" New CPU #defines encode vendor and family as well as model. Signed-off-by: Tony Luck Acked-by: Hans de Goede --- drivers/platform/x86/intel/telemetry/pltdrv.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/platform/x86/intel/telemetry/pltdrv.c b/drivers/platfo= rm/x86/intel/telemetry/pltdrv.c index 06311d0e9451..767a0bc6c7ad 100644 --- a/drivers/platform/x86/intel/telemetry/pltdrv.c +++ b/drivers/platform/x86/intel/telemetry/pltdrv.c @@ -177,8 +177,8 @@ static struct telemetry_plt_config telem_glk_config =3D= { }; =20 static const struct x86_cpu_id telemetry_cpu_ids[] =3D { - X86_MATCH_INTEL_FAM6_MODEL(ATOM_GOLDMONT, &telem_apl_config), - X86_MATCH_INTEL_FAM6_MODEL(ATOM_GOLDMONT_PLUS, &telem_glk_config), + X86_MATCH_VFM(INTEL_ATOM_GOLDMONT, &telem_apl_config), + X86_MATCH_VFM(INTEL_ATOM_GOLDMONT_PLUS, &telem_glk_config), {} }; =20 --=20 2.44.0 From nobody Sat Jul 11 15:40:01 2026 Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.19]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 5328B1CB307; Wed, 24 Apr 2024 18:15:44 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=192.198.163.19 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1713982545; cv=none; b=rBFoGIsHTmErr1nqHkig0oQZ9oeXICMcZnr8g0jNn7Z/ydcibfXydJMGnt2sw+pIxLBsV0lkE6L5Es33hKNM54un8euFfhPDZdjsy4ymkZ9Zt2EtIttD9tbouK361XUx5NfE4NVsqkCGG0ZIMBARDyvpYZWwT3O13XrcD01zvI8= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1713982545; c=relaxed/simple; bh=UGEw2wLj1K8vQaWrX5dXU0U1OAJhcpCUAILxYE5zspA=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=c1A3/Oz/XFrqRYlRSBnj8Q6vkM5yr3m4QI+WdqrYfdh1uZ3Nq296LUKD2/UBQ4wFJTeMHWxpHbdg+OCRZYWhmReTOMfe6iiRLHSEdSOWrM6nV5wN3pIUiNI72/8v4x7QJRYdbSCVYK1nXICMIxDi68VxKp8UadQ6fwk/jN2fBYA= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com; spf=pass smtp.mailfrom=intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=lWOA1poa; arc=none smtp.client-ip=192.198.163.19 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="lWOA1poa" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1713982544; x=1745518544; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=UGEw2wLj1K8vQaWrX5dXU0U1OAJhcpCUAILxYE5zspA=; b=lWOA1poaodkueGqKxqom+5jFzvxFPtKIW4TpriDMil46fd+WU4Y3CCiE /CvpMk2KID3V9HaCd3z4Buu9pOT2mGco9Ze+SwyQLP0J9Dn/77U1TycWh LvmJg6IZPHF76W844ZzNN8wwiPCjfqZhqhQNMfwMvGQL128W49ITyC2uw ZZjDgVcPUGLsTb62+NFFXVQbM7K5LfbdVMpB9MMNJOXfr6oZ6N4EYIZ9d rkJWQS6Y9GnPrYSwaQ6Xqp4IDZsFidCtMSbv54afybemsJ4qh6Idesbk6 qBAHxihAPef3fjbhW0uzeEB0yokcCrrEBznG40IjuwTGrtBI7/lX3sioG g==; X-CSE-ConnectionGUID: tMhfhN7dRruO7r+HrKkdvw== X-CSE-MsgGUID: EK3BsloQS1+FSGmQlqz9fA== X-IronPort-AV: E=McAfee;i="6600,9927,11054"; a="9503718" X-IronPort-AV: E=Sophos;i="6.07,226,1708416000"; d="scan'208";a="9503718" Received: from orviesa002.jf.intel.com ([10.64.159.142]) by fmvoesa113.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 24 Apr 2024 11:15:44 -0700 X-CSE-ConnectionGUID: 2fZ4DXG3TNSfHvPL4RcxTA== X-CSE-MsgGUID: DsC274P2QNG8L8Iv02HxVA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.07,226,1708416000"; d="scan'208";a="55750343" Received: from agluck-desk3.sc.intel.com ([172.25.222.105]) by orviesa002-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 24 Apr 2024 11:15:43 -0700 From: Tony Luck To: Borislav Petkov , Hans de Goede , =?UTF-8?q?Ilpo=20J=C3=A4rvinen?= Cc: Tony Luck , platform-driver-x86@vger.kernel.org, linux-kernel@vger.kernel.org, patches@lists.linux.dev Subject: [PATCH v4 64/71] platform/x86: intel_turbo_max_3: Switch to new Intel CPU model defines Date: Wed, 24 Apr 2024 11:15:43 -0700 Message-ID: <20240424181543.42388-1-tony.luck@intel.com> X-Mailer: git-send-email 2.44.0 In-Reply-To: <20240424181245.41141-1-tony.luck@intel.com> References: <20240424181245.41141-1-tony.luck@intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" New CPU #defines encode vendor and family as well as model. Signed-off-by: Tony Luck Acked-by: Hans de Goede --- drivers/platform/x86/intel/turbo_max_3.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/platform/x86/intel/turbo_max_3.c b/drivers/platform/x8= 6/intel/turbo_max_3.c index 892140b62898..79a0bcdeffb8 100644 --- a/drivers/platform/x86/intel/turbo_max_3.c +++ b/drivers/platform/x86/intel/turbo_max_3.c @@ -114,8 +114,8 @@ static int itmt_legacy_cpu_online(unsigned int cpu) } =20 static const struct x86_cpu_id itmt_legacy_cpu_ids[] =3D { - X86_MATCH_INTEL_FAM6_MODEL(BROADWELL_X, NULL), - X86_MATCH_INTEL_FAM6_MODEL(SKYLAKE_X, NULL), + X86_MATCH_VFM(INTEL_BROADWELL_X, NULL), + X86_MATCH_VFM(INTEL_SKYLAKE_X, NULL), {} }; =20 --=20 2.44.0 From nobody Sat Jul 11 15:40:01 2026 Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.19]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A45FE1CB32C; Wed, 24 Apr 2024 18:15:45 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=192.198.163.19 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1713982547; cv=none; b=D8mofyi3dVshNC5R/R8el9RrSOtKVQqFDzOqb89J4smoEuKLsJPuXcW48kXqmvBSQ+b6BNFY6FfIBOFXE1zjvd986ErMArT4CBMqzD1UJuNjuDLEoZeNFK1fvFCuI/AVS+Cqqtxmui/FJElg3/3cXtNuEUddZQ1ozhpyil0p6Bk= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1713982547; c=relaxed/simple; bh=LOzsD5IsD59gKdeksTuIW83sAKQTK/XFVhkG9cKUAsU=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=Gg3xesxRqq8fAi+ndyLPUO3LfsKrg+vbmhfZP3K+pjoqofvTMLUcN6HFPz/3TGiUNIXJOs9Mo5ezhHCeWAyWaQXzEXmF+6h4SlLAw3LRmyWhQWm9lXL7QGpu4rHqoGBxGWf0Apb0CATnM+nYZCLLZNfVQhPJn+fBrjXVd2C9YI4= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com; spf=pass smtp.mailfrom=intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=fgUp1svT; arc=none smtp.client-ip=192.198.163.19 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="fgUp1svT" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1713982545; x=1745518545; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=LOzsD5IsD59gKdeksTuIW83sAKQTK/XFVhkG9cKUAsU=; b=fgUp1svTlQRcY/tmqdjudGBuDK9Rcd/UAPtX/8ZW28uazaIzOxbLqa91 goT49f7RyZ1FJHnMF77TDmOV0KAnhZ4yYI457FBPoBRSw4TIbiEhiqpWR cqzlsVHLMi9UmoP7vNo8AjsUucJ974gvgVJw48xpD3yhF8kzAHoBb4EK/ igkq0jFRvYdtxTzJx12DkJFHatO5eX7aoNRqQYDVKQTkDKs3Fr4Q5Ly+d W75+d8F2X0n1K8HVY2JpCeYSRhy+iMnGLVXFYsLuYa918aYsuQRBY80oT AQSFCKqMMCypkrqTBPqPDAHCeYrRbpE4hSi8XFLjO0TxkeDZ/ESL4o4sN A==; X-CSE-ConnectionGUID: IqaPb8niS+C+DzghPLYc4A== X-CSE-MsgGUID: eZy/ZMKSQaSnnwst38AM5g== X-IronPort-AV: E=McAfee;i="6600,9927,11054"; a="9503724" X-IronPort-AV: E=Sophos;i="6.07,226,1708416000"; d="scan'208";a="9503724" Received: from orviesa002.jf.intel.com ([10.64.159.142]) by fmvoesa113.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 24 Apr 2024 11:15:45 -0700 X-CSE-ConnectionGUID: Sg/B6JySS/y51w8cThk6ug== X-CSE-MsgGUID: WSHipiGrRDa3mP6dHc/fFw== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.07,226,1708416000"; d="scan'208";a="55750350" Received: from agluck-desk3.sc.intel.com ([172.25.222.105]) by orviesa002-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 24 Apr 2024 11:15:44 -0700 From: Tony Luck To: Borislav Petkov , Srinivas Pandruvada , Hans de Goede , =?UTF-8?q?Ilpo=20J=C3=A4rvinen?= Cc: platform-driver-x86@vger.kernel.org, linux-kernel@vger.kernel.org, patches@lists.linux.dev, Tony Luck Subject: [PATCH v4 65/71] platform/x86: intel-uncore-freq: Switch to new Intel CPU model defines Date: Wed, 24 Apr 2024 11:15:44 -0700 Message-ID: <20240424181544.42407-1-tony.luck@intel.com> X-Mailer: git-send-email 2.44.0 In-Reply-To: <20240424181245.41141-1-tony.luck@intel.com> References: <20240424181245.41141-1-tony.luck@intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" New CPU #defines encode vendor and family as well as model. Signed-off-by: Tony Luck Acked-by: Hans de Goede Acked-by: Srinivas Pandruvada --- .../intel/uncore-frequency/uncore-frequency.c | 56 +++++++++---------- 1 file changed, 28 insertions(+), 28 deletions(-) diff --git a/drivers/platform/x86/intel/uncore-frequency/uncore-frequency.c= b/drivers/platform/x86/intel/uncore-frequency/uncore-frequency.c index b89c0dda9e5d..b80feaf5828f 100644 --- a/drivers/platform/x86/intel/uncore-frequency/uncore-frequency.c +++ b/drivers/platform/x86/intel/uncore-frequency/uncore-frequency.c @@ -197,34 +197,34 @@ static struct notifier_block uncore_pm_nb =3D { }; =20 static const struct x86_cpu_id intel_uncore_cpu_ids[] =3D { - X86_MATCH_INTEL_FAM6_MODEL(BROADWELL_G, NULL), - X86_MATCH_INTEL_FAM6_MODEL(BROADWELL_X, NULL), - X86_MATCH_INTEL_FAM6_MODEL(BROADWELL_D, NULL), - X86_MATCH_INTEL_FAM6_MODEL(SKYLAKE_X, NULL), - X86_MATCH_INTEL_FAM6_MODEL(ICELAKE_X, NULL), - X86_MATCH_INTEL_FAM6_MODEL(ICELAKE_D, NULL), - X86_MATCH_INTEL_FAM6_MODEL(SAPPHIRERAPIDS_X, NULL), - X86_MATCH_INTEL_FAM6_MODEL(EMERALDRAPIDS_X, NULL), - X86_MATCH_INTEL_FAM6_MODEL(KABYLAKE, NULL), - X86_MATCH_INTEL_FAM6_MODEL(KABYLAKE_L, NULL), - X86_MATCH_INTEL_FAM6_MODEL(COMETLAKE, NULL), - X86_MATCH_INTEL_FAM6_MODEL(COMETLAKE_L, NULL), - X86_MATCH_INTEL_FAM6_MODEL(CANNONLAKE_L, NULL), - X86_MATCH_INTEL_FAM6_MODEL(ICELAKE, NULL), - X86_MATCH_INTEL_FAM6_MODEL(ICELAKE_L, NULL), - X86_MATCH_INTEL_FAM6_MODEL(ROCKETLAKE, NULL), - X86_MATCH_INTEL_FAM6_MODEL(TIGERLAKE, NULL), - X86_MATCH_INTEL_FAM6_MODEL(TIGERLAKE_L, NULL), - X86_MATCH_INTEL_FAM6_MODEL(ALDERLAKE, NULL), - X86_MATCH_INTEL_FAM6_MODEL(ALDERLAKE_L, NULL), - X86_MATCH_INTEL_FAM6_MODEL(RAPTORLAKE, NULL), - X86_MATCH_INTEL_FAM6_MODEL(RAPTORLAKE_P, NULL), - X86_MATCH_INTEL_FAM6_MODEL(RAPTORLAKE_S, NULL), - X86_MATCH_INTEL_FAM6_MODEL(METEORLAKE, NULL), - X86_MATCH_INTEL_FAM6_MODEL(METEORLAKE_L, NULL), - X86_MATCH_INTEL_FAM6_MODEL(ARROWLAKE, NULL), - X86_MATCH_INTEL_FAM6_MODEL(ARROWLAKE_H, NULL), - X86_MATCH_INTEL_FAM6_MODEL(LUNARLAKE_M, NULL), + X86_MATCH_VFM(INTEL_BROADWELL_G, NULL), + X86_MATCH_VFM(INTEL_BROADWELL_X, NULL), + X86_MATCH_VFM(INTEL_BROADWELL_D, NULL), + X86_MATCH_VFM(INTEL_SKYLAKE_X, NULL), + X86_MATCH_VFM(INTEL_ICELAKE_X, NULL), + X86_MATCH_VFM(INTEL_ICELAKE_D, NULL), + X86_MATCH_VFM(INTEL_SAPPHIRERAPIDS_X, NULL), + X86_MATCH_VFM(INTEL_EMERALDRAPIDS_X, NULL), + X86_MATCH_VFM(INTEL_KABYLAKE, NULL), + X86_MATCH_VFM(INTEL_KABYLAKE_L, NULL), + X86_MATCH_VFM(INTEL_COMETLAKE, NULL), + X86_MATCH_VFM(INTEL_COMETLAKE_L, NULL), + X86_MATCH_VFM(INTEL_CANNONLAKE_L, NULL), + X86_MATCH_VFM(INTEL_ICELAKE, NULL), + X86_MATCH_VFM(INTEL_ICELAKE_L, NULL), + X86_MATCH_VFM(INTEL_ROCKETLAKE, NULL), + X86_MATCH_VFM(INTEL_TIGERLAKE, NULL), + X86_MATCH_VFM(INTEL_TIGERLAKE_L, NULL), + X86_MATCH_VFM(INTEL_ALDERLAKE, NULL), + X86_MATCH_VFM(INTEL_ALDERLAKE_L, NULL), + X86_MATCH_VFM(INTEL_RAPTORLAKE, NULL), + X86_MATCH_VFM(INTEL_RAPTORLAKE_P, NULL), + X86_MATCH_VFM(INTEL_RAPTORLAKE_S, NULL), + X86_MATCH_VFM(INTEL_METEORLAKE, NULL), + X86_MATCH_VFM(INTEL_METEORLAKE_L, NULL), + X86_MATCH_VFM(INTEL_ARROWLAKE, NULL), + X86_MATCH_VFM(INTEL_ARROWLAKE_H, NULL), + X86_MATCH_VFM(INTEL_LUNARLAKE_M, NULL), {} }; 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charset="utf-8" New CPU #defines encode vendor and family as well as model. Signed-off-by: Tony Luck Acked-by: Hans de Goede --- drivers/platform/x86/p2sb.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/platform/x86/p2sb.c b/drivers/platform/x86/p2sb.c index 3d66e1d4eb1f..8cfbf0bbd346 100644 --- a/drivers/platform/x86/p2sb.c +++ b/drivers/platform/x86/p2sb.c @@ -24,7 +24,7 @@ #define SPI_DEVFN_GOLDMONT PCI_DEVFN(13, 2) =20 static const struct x86_cpu_id p2sb_cpu_ids[] =3D { - X86_MATCH_INTEL_FAM6_MODEL(ATOM_GOLDMONT, P2SB_DEVFN_GOLDMONT), + X86_MATCH_VFM(INTEL_ATOM_GOLDMONT, P2SB_DEVFN_GOLDMONT), {} }; =20 --=20 2.44.0 From nobody Sat Jul 11 15:40:01 2026 Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.19]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D0171200136; Wed, 24 Apr 2024 18:15:47 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=192.198.163.19 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1713982549; cv=none; b=hrzXq7FrR1aEeWSB+kPJZ1/6Nv79YfzLXEDQefGL12Zo8vtYJv7HsYN1xa3GeFiTz4OfkF2rrXFkViG71v8owrY68CNq0J9lZmbwbxkwJniYvfY/Y2/skZhygpJAgxeIOm4k27OqxiMiC7dYMW339d0GDNPU5IyDHkTmXvdXlOk= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1713982549; c=relaxed/simple; bh=tuc2bJNVfoJEYlt7uobgAji+MBXQbVAFmZXBeLnr2IY=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=D6nSDAe/8m5A4+7td2sP9ZhNWE1h6eg7sFN5Jf5SBhMXxprmLLJ2w5gOD9Y6ClA0MRbBF49j/qQnm7ETQMdFJEgUcWeYbHem3VUkjfoKwfnovpig+wnho3DDCK0Q+4RmGxVsa8OavnScdi/evxFQgXgMI43I2afAJB2yi76uhEg= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com; spf=pass smtp.mailfrom=intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=mpghOwef; arc=none smtp.client-ip=192.198.163.19 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="mpghOwef" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1713982548; x=1745518548; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=tuc2bJNVfoJEYlt7uobgAji+MBXQbVAFmZXBeLnr2IY=; b=mpghOwefjT5XFTKhnFvUx4RLwNBaqsrYpd8LN+2tVAUaYLBng9L6hMeJ OJD7ujx5m8ZMffuN2QXyN0xE1XeBS8O4M0ZbyLH59cKv1417J6KuW8NHe Z7NJQu3xtQPKZF91fNa2SerzXwBQMVunkLu4oHk+YLBcyPmKG2uBPhbVb c+n0h6XXOj+73VRjr/tc5UF8bZObsV6XWd+7Ang8g9H5M3yklrwYz+k82 BPZFTPEn8z+HeBFKLWh09lVx90MacHkTn7uGTSe4dV66An7IxjVXezNiE RiD0JrqBUxV4wPiv6ulfgscRCiIYt4LquHzRShc/LIV72KehexwKiDQDW w==; X-CSE-ConnectionGUID: qPNv8KGXROW36tdjppPvOA== X-CSE-MsgGUID: qxbadtIiRZuSETUWEz/gag== X-IronPort-AV: E=McAfee;i="6600,9927,11054"; a="9503732" X-IronPort-AV: E=Sophos;i="6.07,226,1708416000"; d="scan'208";a="9503732" Received: from orviesa002.jf.intel.com ([10.64.159.142]) by fmvoesa113.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 24 Apr 2024 11:15:47 -0700 X-CSE-ConnectionGUID: MiD0ufA1RiGCOfFZdskV4g== X-CSE-MsgGUID: wNR2dLrvSQeMTQmioWEzRg== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.07,226,1708416000"; d="scan'208";a="55750381" Received: from agluck-desk3.sc.intel.com ([172.25.222.105]) by orviesa002-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 24 Apr 2024 11:15:47 -0700 From: Tony Luck To: Borislav Petkov , Hans de Goede , Mauro Carvalho Chehab Cc: Sakari Ailus , Greg Kroah-Hartman , Andy Shevchenko , Tony Luck , linux-media@vger.kernel.org, linux-staging@lists.linux.dev, linux-kernel@vger.kernel.org, patches@lists.linux.dev Subject: [PATCH v4 67/71] media: atomisp: Switch to new Intel CPU model defines Date: Wed, 24 Apr 2024 11:15:46 -0700 Message-ID: <20240424181546.42446-1-tony.luck@intel.com> X-Mailer: git-send-email 2.44.0 In-Reply-To: <20240424181245.41141-1-tony.luck@intel.com> References: <20240424181245.41141-1-tony.luck@intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" New CPU #defines encode vendor and family as well as model. Signed-off-by: Tony Luck Acked-by: Hans de Goede Reviewed-by: Andy Shevchenko --- .../atomisp/include/linux/atomisp_platform.h | 27 ++++++++----------- 1 file changed, 11 insertions(+), 16 deletions(-) diff --git a/drivers/staging/media/atomisp/include/linux/atomisp_platform.h= b/drivers/staging/media/atomisp/include/linux/atomisp_platform.h index 487ef5846c24..70bab3d1bc2f 100644 --- a/drivers/staging/media/atomisp/include/linux/atomisp_platform.h +++ b/drivers/staging/media/atomisp/include/linux/atomisp_platform.h @@ -18,7 +18,7 @@ #ifndef ATOMISP_PLATFORM_H_ #define ATOMISP_PLATFORM_H_ =20 -#include +#include #include =20 #include @@ -217,22 +217,17 @@ void atomisp_unregister_subdev(struct v4l2_subdev *su= bdev); int v4l2_get_acpi_sensor_info(struct device *dev, char **module_id_str); =20 /* API from old platform_camera.h, new CPUID implementation */ -#define __IS_SOC(x) (boot_cpu_data.x86_vendor =3D=3D X86_VENDOR_INTEL && \ - boot_cpu_data.x86 =3D=3D 6 && \ - boot_cpu_data.x86_model =3D=3D (x)) -#define __IS_SOCS(x,y) (boot_cpu_data.x86_vendor =3D=3D X86_VENDOR_INTEL &= & \ - boot_cpu_data.x86 =3D=3D 6 && \ - (boot_cpu_data.x86_model =3D=3D (x) || \ - boot_cpu_data.x86_model =3D=3D (y))) - -#define IS_MFLD __IS_SOC(INTEL_FAM6_ATOM_SALTWELL_MID) -#define IS_BYT __IS_SOC(INTEL_FAM6_ATOM_SILVERMONT) -#define IS_CHT __IS_SOC(INTEL_FAM6_ATOM_AIRMONT) -#define IS_MRFD __IS_SOC(INTEL_FAM6_ATOM_SILVERMONT_MID) -#define IS_MOFD __IS_SOC(INTEL_FAM6_ATOM_AIRMONT_MID) +#define __IS_SOC(x) (boot_cpu_data.x86_vfm =3D=3D x) +#define __IS_SOCS(x, y) (boot_cpu_data.x86_vfm =3D=3D x || boot_cpu_data.x= 86_vfm =3D=3D y) + +#define IS_MFLD __IS_SOC(INTEL_ATOM_SALTWELL_MID) +#define IS_BYT __IS_SOC(INTEL_ATOM_SILVERMONT) +#define IS_CHT __IS_SOC(INTEL_ATOM_AIRMONT) +#define IS_MRFD __IS_SOC(INTEL_ATOM_SILVERMONT_MID) +#define IS_MOFD __IS_SOC(INTEL_ATOM_AIRMONT_MID) =20 /* Both CHT and MOFD come with ISP2401 */ -#define IS_ISP2401 __IS_SOCS(INTEL_FAM6_ATOM_AIRMONT, \ - INTEL_FAM6_ATOM_AIRMONT_MID) +#define IS_ISP2401 __IS_SOCS(INTEL_ATOM_AIRMONT, \ + INTEL_ATOM_AIRMONT_MID) =20 #endif /* ATOMISP_PLATFORM_H_ */ --=20 2.44.0 From nobody Sat Jul 11 15:40:01 2026 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.16]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 645B520FA88; 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a="9756053" X-IronPort-AV: E=Sophos;i="6.07,226,1708416000"; d="scan'208";a="9756053" Received: from orviesa009.jf.intel.com ([10.64.159.149]) by orvoesa108.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 24 Apr 2024 11:15:51 -0700 X-CSE-ConnectionGUID: T9nCikZuQKGmObTt2tD5Xw== X-CSE-MsgGUID: DLFKgAyLRaOzpNGLtJ2BRg== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.07,226,1708416000"; d="scan'208";a="24751186" Received: from agluck-desk3.sc.intel.com ([172.25.222.105]) by orviesa009-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 24 Apr 2024 11:15:51 -0700 From: Tony Luck To: Borislav Petkov , Jaroslav Kysela , Takashi Iwai Cc: Cezary Rojewski , Pierre-Louis Bossart , Liam Girdwood , Peter Ujfalusi , Bard Liao , Ranjani Sridharan , Kai Vehmanen , Mark Brown , =?UTF-8?q?Amadeusz=20S=C5=82awi=C5=84ski?= , Krzysztof Kozlowski , Kuninori Morimoto , Tony Luck , alsa-devel@alsa-project.org, linux-sound@vger.kernel.org, linux-kernel@vger.kernel.org, patches@lists.linux.dev Subject: [PATCH v4 68/71] ASoC: Intel: avs: es8336: Switch to new Intel CPU model defines Date: Wed, 24 Apr 2024 11:15:50 -0700 Message-ID: <20240424181550.42466-1-tony.luck@intel.com> X-Mailer: git-send-email 2.44.0 In-Reply-To: <20240424181245.41141-1-tony.luck@intel.com> References: <20240424181245.41141-1-tony.luck@intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" New CPU #defines encode vendor and family as well as model. Signed-off-by: Tony Luck Acked-by: Hans de Goede Acked-by: Mark Brown Reviewed-by: Amadeusz S=C5=82awi=C5=84ski --- sound/soc/intel/avs/boards/es8336.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/sound/soc/intel/avs/boards/es8336.c b/sound/soc/intel/avs/boar= ds/es8336.c index 5c90a6007577..3d5d4685a668 100644 --- a/sound/soc/intel/avs/boards/es8336.c +++ b/sound/soc/intel/avs/boards/es8336.c @@ -18,7 +18,7 @@ #include #include #include -#include +#include #include "../utils.h" =20 #define ES8336_CODEC_DAI "ES8316 HiFi" @@ -153,9 +153,9 @@ static int avs_es8336_hw_params(struct snd_pcm_substrea= m *substream, int clk_freq; int ret; =20 - switch (boot_cpu_data.x86_model) { - case INTEL_FAM6_KABYLAKE_L: - case INTEL_FAM6_KABYLAKE: + switch (boot_cpu_data.x86_vfm) { + case INTEL_KABYLAKE_L: + case INTEL_KABYLAKE: clk_freq =3D 24000000; break; default: --=20 2.44.0 From nobody Sat Jul 11 15:40:01 2026 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.16]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 9D22B200133; Wed, 24 Apr 2024 18:15:52 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.16 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1713982554; cv=none; b=QmfTAV4BNG+T6lhpbhPAz2aTa1TUB6M14IUUfOaR8GJ6FwGAeHusLiQFPZj61dlBueDeUV4sX1uTwMgMeBZith4HbCJO/TEQUdiYuAYyjZE/jvSxcvL4k04q0bj3n0wx9YDVDF2MsajnnXPYCmUqIVNanJNvWSOb+2jGkVcB/n8= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1713982554; c=relaxed/simple; bh=cqyzuAeGvuhZYodMb9AblLQW+gSz+JxsTr7KnJrT2no=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=XDX5bqqSbuhwzG6xomvNtoTSBEEBPkuwXED9tEySujT8FcG6mPzKyaK8OHw1i9y6bgnG06lUZ5GDKgfRxbnfk02KlIldFIHODB9U3XXCIkeUtSQaCLPpCqKp7ZnPveFEwcu82/FciXjD/mXGp2O9N2dh+oyjEtg6DIMZ6sSjf0U= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com; spf=pass smtp.mailfrom=intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=IO96u5qG; arc=none smtp.client-ip=198.175.65.16 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="IO96u5qG" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1713982552; x=1745518552; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=cqyzuAeGvuhZYodMb9AblLQW+gSz+JxsTr7KnJrT2no=; b=IO96u5qGEU8ou99rBylwxCR9i7qzs/zYGSLfn3Dyj4q2onrAmjSSMfcg b6iunNfRjyj+SDneHrjtgcIq3jf2QxvmsFbzUMZM3d5aV0JdMudDmcmTZ K/GoII+G+UUNROOcbxmKhpYmbBuoOfr/x7qOYuxAFUmsQonMcNxAS6oRR TlgD899KWRNpJVhWtjfkHTYN68yD1lyDfuvnbfsIz6lUYgEs3ShA4a+F/ BbfvLnSYGasB0NksLfSzkLwZhzHlEiq7nvvUtn9hfmr0UuUDqclA4qwgr V+Sy8tSf9rcpVUrP/tQtKA5KYuJEoESmpktzRslFtqF1ihVXVImNSciMG g==; X-CSE-ConnectionGUID: Xpg3ir11Q6W6LT0yEyVLpg== X-CSE-MsgGUID: WaCnQyvATGueyvp8SYSLyQ== X-IronPort-AV: E=McAfee;i="6600,9927,11054"; a="9756064" X-IronPort-AV: E=Sophos;i="6.07,226,1708416000"; d="scan'208";a="9756064" Received: from orviesa009.jf.intel.com ([10.64.159.149]) by orvoesa108.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 24 Apr 2024 11:15:52 -0700 X-CSE-ConnectionGUID: t9CQo1P9SQWV6lxhtd7B2w== X-CSE-MsgGUID: wkqUrdg7R5uzIjUmvw3Mvg== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.07,226,1708416000"; d="scan'208";a="24751198" Received: from agluck-desk3.sc.intel.com ([172.25.222.105]) by orviesa009-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 24 Apr 2024 11:15:52 -0700 From: Tony Luck To: Borislav Petkov , Thomas Gleixner , Dave Hansen , x86@kernel.org Cc: Peter Zijlstra , Ingo Molnar , Arnaldo Carvalho de Melo , Namhyung Kim , Mark Rutland , Alexander Shishkin , Jiri Olsa , Ian Rogers , Adrian Hunter , "H. Peter Anvin" , linux-perf-users@vger.kernel.org, linux-kernel@vger.kernel.org, patches@lists.linux.dev, Tony Luck Subject: [PATCH v4 69/71] perf/x86/rapl: Switch to new Intel CPU model defines Date: Wed, 24 Apr 2024 11:15:51 -0700 Message-ID: <20240424181551.42485-1-tony.luck@intel.com> X-Mailer: git-send-email 2.44.0 In-Reply-To: <20240424181245.41141-1-tony.luck@intel.com> References: <20240424181245.41141-1-tony.luck@intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" New CPU #defines encode vendor and family as well as model. Signed-off-by: Tony Luck Acked-by: Hans de Goede --- arch/x86/events/rapl.c | 84 +++++++++++++++++++++--------------------- 1 file changed, 42 insertions(+), 42 deletions(-) diff --git a/arch/x86/events/rapl.c b/arch/x86/events/rapl.c index fb2b1961e5a3..45b62ef451aa 100644 --- a/arch/x86/events/rapl.c +++ b/arch/x86/events/rapl.c @@ -766,48 +766,48 @@ static struct rapl_model model_amd_hygon =3D { }; =20 static const struct x86_cpu_id rapl_model_match[] __initconst =3D { - X86_MATCH_FEATURE(X86_FEATURE_RAPL, &model_amd_hygon), - X86_MATCH_INTEL_FAM6_MODEL(SANDYBRIDGE, &model_snb), - X86_MATCH_INTEL_FAM6_MODEL(SANDYBRIDGE_X, &model_snbep), - X86_MATCH_INTEL_FAM6_MODEL(IVYBRIDGE, &model_snb), - X86_MATCH_INTEL_FAM6_MODEL(IVYBRIDGE_X, &model_snbep), - X86_MATCH_INTEL_FAM6_MODEL(HASWELL, &model_hsw), - X86_MATCH_INTEL_FAM6_MODEL(HASWELL_X, &model_hsx), - X86_MATCH_INTEL_FAM6_MODEL(HASWELL_L, &model_hsw), - X86_MATCH_INTEL_FAM6_MODEL(HASWELL_G, &model_hsw), - X86_MATCH_INTEL_FAM6_MODEL(BROADWELL, &model_hsw), - X86_MATCH_INTEL_FAM6_MODEL(BROADWELL_G, &model_hsw), - X86_MATCH_INTEL_FAM6_MODEL(BROADWELL_X, &model_hsx), - X86_MATCH_INTEL_FAM6_MODEL(BROADWELL_D, &model_hsx), - X86_MATCH_INTEL_FAM6_MODEL(XEON_PHI_KNL, &model_knl), - X86_MATCH_INTEL_FAM6_MODEL(XEON_PHI_KNM, &model_knl), - X86_MATCH_INTEL_FAM6_MODEL(SKYLAKE_L, &model_skl), - X86_MATCH_INTEL_FAM6_MODEL(SKYLAKE, &model_skl), - X86_MATCH_INTEL_FAM6_MODEL(SKYLAKE_X, &model_hsx), - X86_MATCH_INTEL_FAM6_MODEL(KABYLAKE_L, &model_skl), - X86_MATCH_INTEL_FAM6_MODEL(KABYLAKE, &model_skl), - X86_MATCH_INTEL_FAM6_MODEL(CANNONLAKE_L, &model_skl), - X86_MATCH_INTEL_FAM6_MODEL(ATOM_GOLDMONT, &model_hsw), - X86_MATCH_INTEL_FAM6_MODEL(ATOM_GOLDMONT_D, &model_hsw), - X86_MATCH_INTEL_FAM6_MODEL(ATOM_GOLDMONT_PLUS, &model_hsw), - X86_MATCH_INTEL_FAM6_MODEL(ICELAKE_L, &model_skl), - X86_MATCH_INTEL_FAM6_MODEL(ICELAKE, &model_skl), - X86_MATCH_INTEL_FAM6_MODEL(ICELAKE_D, &model_hsx), - X86_MATCH_INTEL_FAM6_MODEL(ICELAKE_X, &model_hsx), - X86_MATCH_INTEL_FAM6_MODEL(COMETLAKE_L, &model_skl), - X86_MATCH_INTEL_FAM6_MODEL(COMETLAKE, &model_skl), - X86_MATCH_INTEL_FAM6_MODEL(TIGERLAKE_L, &model_skl), - X86_MATCH_INTEL_FAM6_MODEL(TIGERLAKE, &model_skl), - X86_MATCH_INTEL_FAM6_MODEL(ALDERLAKE, &model_skl), - X86_MATCH_INTEL_FAM6_MODEL(ALDERLAKE_L, &model_skl), - X86_MATCH_INTEL_FAM6_MODEL(ATOM_GRACEMONT, &model_skl), - X86_MATCH_INTEL_FAM6_MODEL(SAPPHIRERAPIDS_X, &model_spr), - X86_MATCH_INTEL_FAM6_MODEL(EMERALDRAPIDS_X, &model_spr), - X86_MATCH_INTEL_FAM6_MODEL(RAPTORLAKE, &model_skl), - X86_MATCH_INTEL_FAM6_MODEL(RAPTORLAKE_P, &model_skl), - X86_MATCH_INTEL_FAM6_MODEL(RAPTORLAKE_S, &model_skl), - X86_MATCH_INTEL_FAM6_MODEL(METEORLAKE, &model_skl), - X86_MATCH_INTEL_FAM6_MODEL(METEORLAKE_L, &model_skl), + X86_MATCH_FEATURE(X86_FEATURE_RAPL, &model_amd_hygon), + X86_MATCH_VFM(INTEL_SANDYBRIDGE, &model_snb), + X86_MATCH_VFM(INTEL_SANDYBRIDGE_X, &model_snbep), + X86_MATCH_VFM(INTEL_IVYBRIDGE, &model_snb), + X86_MATCH_VFM(INTEL_IVYBRIDGE_X, &model_snbep), + X86_MATCH_VFM(INTEL_HASWELL, &model_hsw), + X86_MATCH_VFM(INTEL_HASWELL_X, &model_hsx), + X86_MATCH_VFM(INTEL_HASWELL_L, &model_hsw), + X86_MATCH_VFM(INTEL_HASWELL_G, &model_hsw), + X86_MATCH_VFM(INTEL_BROADWELL, &model_hsw), + X86_MATCH_VFM(INTEL_BROADWELL_G, &model_hsw), + X86_MATCH_VFM(INTEL_BROADWELL_X, &model_hsx), + X86_MATCH_VFM(INTEL_BROADWELL_D, &model_hsx), + X86_MATCH_VFM(INTEL_XEON_PHI_KNL, &model_knl), + X86_MATCH_VFM(INTEL_XEON_PHI_KNM, &model_knl), + X86_MATCH_VFM(INTEL_SKYLAKE_L, &model_skl), + X86_MATCH_VFM(INTEL_SKYLAKE, &model_skl), + X86_MATCH_VFM(INTEL_SKYLAKE_X, &model_hsx), + X86_MATCH_VFM(INTEL_KABYLAKE_L, &model_skl), + X86_MATCH_VFM(INTEL_KABYLAKE, &model_skl), + X86_MATCH_VFM(INTEL_CANNONLAKE_L, &model_skl), + X86_MATCH_VFM(INTEL_ATOM_GOLDMONT, &model_hsw), + X86_MATCH_VFM(INTEL_ATOM_GOLDMONT_D, &model_hsw), + X86_MATCH_VFM(INTEL_ATOM_GOLDMONT_PLUS, &model_hsw), + X86_MATCH_VFM(INTEL_ICELAKE_L, &model_skl), + X86_MATCH_VFM(INTEL_ICELAKE, &model_skl), + X86_MATCH_VFM(INTEL_ICELAKE_D, &model_hsx), + X86_MATCH_VFM(INTEL_ICELAKE_X, &model_hsx), + X86_MATCH_VFM(INTEL_COMETLAKE_L, &model_skl), + X86_MATCH_VFM(INTEL_COMETLAKE, &model_skl), + X86_MATCH_VFM(INTEL_TIGERLAKE_L, &model_skl), + X86_MATCH_VFM(INTEL_TIGERLAKE, &model_skl), + X86_MATCH_VFM(INTEL_ALDERLAKE, &model_skl), + X86_MATCH_VFM(INTEL_ALDERLAKE_L, &model_skl), + X86_MATCH_VFM(INTEL_ATOM_GRACEMONT, &model_skl), + X86_MATCH_VFM(INTEL_SAPPHIRERAPIDS_X, &model_spr), + X86_MATCH_VFM(INTEL_EMERALDRAPIDS_X, &model_spr), + X86_MATCH_VFM(INTEL_RAPTORLAKE, &model_skl), + X86_MATCH_VFM(INTEL_RAPTORLAKE_P, &model_skl), + X86_MATCH_VFM(INTEL_RAPTORLAKE_S, &model_skl), + X86_MATCH_VFM(INTEL_METEORLAKE, &model_skl), + X86_MATCH_VFM(INTEL_METEORLAKE_L, &model_skl), {}, }; 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Peter Anvin" , Tony Luck , linux-kernel@vger.kernel.org, patches@lists.linux.dev Subject: [PATCH v4 70/71] x86/cpu/vfm: Delete X86_MATCH_INTEL_FAM6_MODEL[_STEPPING]() macros Date: Wed, 24 Apr 2024 11:15:52 -0700 Message-ID: <20240424181552.42505-1-tony.luck@intel.com> X-Mailer: git-send-email 2.44.0 In-Reply-To: <20240424181245.41141-1-tony.luck@intel.com> References: <20240424181245.41141-1-tony.luck@intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" These macros have been replaced by X86_MATCH_VFM[_STEPPING]() Signed-off-by: Tony Luck Acked-by: Hans de Goede --- arch/x86/include/asm/cpu_device_id.h | 20 -------------------- 1 file changed, 20 deletions(-) diff --git a/arch/x86/include/asm/cpu_device_id.h b/arch/x86/include/asm/cp= u_device_id.h index cac33812c609..92b54e320294 100644 --- a/arch/x86/include/asm/cpu_device_id.h +++ b/arch/x86/include/asm/cpu_device_id.h @@ -187,26 +187,6 @@ #define X86_MATCH_VENDOR_FAM(vendor, family, data) \ X86_MATCH_VENDOR_FAM_MODEL(vendor, family, X86_MODEL_ANY, data) =20 -/** - * X86_MATCH_INTEL_FAM6_MODEL - Match vendor INTEL, family 6 and model - * @model: The model name without the INTEL_FAM6_ prefix or ANY - * The model name is expanded to INTEL_FAM6_@model internally - * @data: Driver specific data or NULL. The internal storage - * format is unsigned long. The supplied value, pointer - * etc. is casted to unsigned long internally. - * - * The vendor is set to INTEL, the family to 6 and all other missing - * arguments of X86_MATCH_VENDOR_FAM_MODEL_FEATURE() are set to wildcards. - * - * See X86_MATCH_VENDOR_FAM_MODEL_FEATURE() for further information. - */ -#define X86_MATCH_INTEL_FAM6_MODEL(model, data) \ - X86_MATCH_VENDOR_FAM_MODEL(INTEL, 6, INTEL_FAM6_##model, data) - -#define X86_MATCH_INTEL_FAM6_MODEL_STEPPINGS(model, steppings, data) \ - X86_MATCH_VENDOR_FAM_MODEL_STEPPINGS_FEATURE(INTEL, 6, INTEL_FAM6_##model= , \ - steppings, X86_FEATURE_ANY, data) - /** * X86_MATCH_VFM - Match encoded vendor/family/model * @vfm: Encoded 8-bits each for vendor, family, model --=20 2.44.0 From nobody Sat Jul 11 15:40:01 2026 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.16]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id BFF9220FAB2 for ; Wed, 24 Apr 2024 18:15:54 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.16 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1713982556; cv=none; b=A0gr6RStmiu0pUSZLS4Yy3dd9jFPK1SpKm227+UteNIC0UBSoEplg0/UgHmRfH9Qz9NVNTBwP/fwDhHVHSyOJzLtscvyoDfzl8tjYdudR9V46HwbsPQa3IwvQsC33Lf0Iw74vruUH1G+Gvb64RMrK5v5LBxmZD33VLlmSd47UOg= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1713982556; c=relaxed/simple; bh=DG8cr7rk4xOq94LLqhelPZm3zqtB92Ey59ukepvPlu0=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=o8strBQzVaAeJt8EF2lk5g4wJgqt+sk+gOyslHjXWiJwPAaUfAFxgujCjtz57n3sh4AdOcjTtoTt8EsYBkPp/oTDG1CjwlkeYTiAIn9pv0MDgZhtiNaupDqcqgmj/QaYHkZ7HaF38b2DxOQIXSUz7q3HZqWnmRy7XVbGwURXfZQ= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com; spf=pass smtp.mailfrom=intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=KAzpWePc; arc=none smtp.client-ip=198.175.65.16 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="KAzpWePc" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1713982555; x=1745518555; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=DG8cr7rk4xOq94LLqhelPZm3zqtB92Ey59ukepvPlu0=; b=KAzpWePcnVduIO+rMHPucAnG5jRtArUFoIy77y939M5sUFUc4Zg2sykW +F1viR9RNsGUruu8ZhPzUKKAAvPd21AwHdV8XjWl+MaDZNCjr6vka/j8M 89LsyBaOYJml0ttHo36CStD+mGDUD3jyU8pXCdJFKPa/b0J9iKPaK5aof 1W9ZcOEqA/1nSv5U9vPK+epfOerXBFn68VhJJmQk8gNZN0fuJ2R0wv8oC a1Gmeyn7lCBoxrtKkhj8klrVFpSFf1pIvS2RMoPj9G9OVKHI5aYME8kua R9D+hij8bYoC4pD3XmXto/JsQN85ISZC0npoZ+BkO1AeQ22JVKvDh0t4z g==; X-CSE-ConnectionGUID: wNYTBGnpQZWS+4zBi0OKuQ== X-CSE-MsgGUID: yoNBFNuxSouw7uSWCNb29Q== X-IronPort-AV: E=McAfee;i="6600,9927,11054"; a="9756087" X-IronPort-AV: E=Sophos;i="6.07,226,1708416000"; d="scan'208";a="9756087" Received: from orviesa009.jf.intel.com ([10.64.159.149]) by orvoesa108.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 24 Apr 2024 11:15:54 -0700 X-CSE-ConnectionGUID: jrMm8IjLQZ69hvfSNZ8DzA== X-CSE-MsgGUID: 3FsC76spQaCoiWia4wDO9Q== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.07,226,1708416000"; d="scan'208";a="24751223" Received: from agluck-desk3.sc.intel.com ([172.25.222.105]) by orviesa009-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 24 Apr 2024 11:15:55 -0700 From: Tony Luck To: Borislav Petkov , Thomas Gleixner , Ingo Molnar , Dave Hansen Cc: Tony Luck , x86@kernel.org, "H. Peter Anvin" , linux-kernel@vger.kernel.org, patches@lists.linux.dev Subject: [PATCH v4 71/71] x86/cpu/vfm: Delete all the *_FAM6_ CPU #defines Date: Wed, 24 Apr 2024 11:15:53 -0700 Message-ID: <20240424181554.42524-1-tony.luck@intel.com> X-Mailer: git-send-email 2.44.0 In-Reply-To: <20240424181245.41141-1-tony.luck@intel.com> References: <20240424181245.41141-1-tony.luck@intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" All code has been converted to use the vendor/family/model versions. Signed-off-by: Tony Luck Acked-by: Hans de Goede --- arch/x86/include/asm/intel-family.h | 85 +---------------------------- 1 file changed, 2 insertions(+), 83 deletions(-) diff --git a/arch/x86/include/asm/intel-family.h b/arch/x86/include/asm/int= el-family.h index f81a851c46dc..f7289094a483 100644 --- a/arch/x86/include/asm/intel-family.h +++ b/arch/x86/include/asm/intel-family.h @@ -10,7 +10,7 @@ * that group keep the CPUID for the variants sorted by model number. * * The defined symbol names have the following form: - * INTEL_FAM6{OPTFAMILY}_{MICROARCH}{OPTDIFF} + * INTEL_{OPTFAMILY}_{MICROARCH}{OPTDIFF} * where: * OPTFAMILY Describes the family of CPUs that this belongs to. Default * is assumed to be "_CORE" (and should be omitted). Other values @@ -42,215 +42,134 @@ =20 #define IFM(_fam, _model) VFM_MAKE(X86_VENDOR_INTEL, _fam, _model) =20 -/* Wildcard match for FAM6 so X86_MATCH_INTEL_FAM6_MODEL(ANY) works */ -#define INTEL_FAM6_ANY X86_MODEL_ANY -/* Wildcard match for FAM6 so X86_MATCH_VFM(ANY) works */ +/* Wildcard match so X86_MATCH_VFM(ANY) works */ #define INTEL_ANY IFM(X86_FAMILY_ANY, X86_MODEL_ANY) =20 -#define INTEL_FAM6_CORE_YONAH 0x0E #define INTEL_CORE_YONAH IFM(6, 0x0E) =20 -#define INTEL_FAM6_CORE2_MEROM 0x0F #define INTEL_CORE2_MEROM IFM(6, 0x0F) -#define INTEL_FAM6_CORE2_MEROM_L 0x16 #define INTEL_CORE2_MEROM_L IFM(6, 0x16) -#define INTEL_FAM6_CORE2_PENRYN 0x17 #define INTEL_CORE2_PENRYN IFM(6, 0x17) -#define INTEL_FAM6_CORE2_DUNNINGTON 0x1D #define INTEL_CORE2_DUNNINGTON IFM(6, 0x1D) =20 -#define INTEL_FAM6_NEHALEM 0x1E #define INTEL_NEHALEM IFM(6, 0x1E) -#define INTEL_FAM6_NEHALEM_G 0x1F /* Auburndale / Havendale */ #define INTEL_NEHALEM_G IFM(6, 0x1F) /* Auburndale / Havendale */ -#define INTEL_FAM6_NEHALEM_EP 0x1A #define INTEL_NEHALEM_EP IFM(6, 0x1A) -#define INTEL_FAM6_NEHALEM_EX 0x2E #define INTEL_NEHALEM_EX IFM(6, 0x2E) =20 -#define INTEL_FAM6_WESTMERE 0x25 #define INTEL_WESTMERE IFM(6, 0x25) -#define INTEL_FAM6_WESTMERE_EP 0x2C #define INTEL_WESTMERE_EP IFM(6, 0x2C) -#define INTEL_FAM6_WESTMERE_EX 0x2F #define INTEL_WESTMERE_EX IFM(6, 0x2F) =20 -#define INTEL_FAM6_SANDYBRIDGE 0x2A #define INTEL_SANDYBRIDGE IFM(6, 0x2A) -#define INTEL_FAM6_SANDYBRIDGE_X 0x2D #define INTEL_SANDYBRIDGE_X IFM(6, 0x2D) -#define INTEL_FAM6_IVYBRIDGE 0x3A #define INTEL_IVYBRIDGE IFM(6, 0x3A) -#define INTEL_FAM6_IVYBRIDGE_X 0x3E #define INTEL_IVYBRIDGE_X IFM(6, 0x3E) =20 -#define INTEL_FAM6_HASWELL 0x3C #define INTEL_HASWELL IFM(6, 0x3C) -#define INTEL_FAM6_HASWELL_X 0x3F #define INTEL_HASWELL_X IFM(6, 0x3F) -#define INTEL_FAM6_HASWELL_L 0x45 #define INTEL_HASWELL_L IFM(6, 0x45) -#define INTEL_FAM6_HASWELL_G 0x46 #define INTEL_HASWELL_G IFM(6, 0x46) =20 -#define INTEL_FAM6_BROADWELL 0x3D #define INTEL_BROADWELL IFM(6, 0x3D) -#define INTEL_FAM6_BROADWELL_G 0x47 #define INTEL_BROADWELL_G IFM(6, 0x47) -#define INTEL_FAM6_BROADWELL_X 0x4F #define INTEL_BROADWELL_X IFM(6, 0x4F) -#define INTEL_FAM6_BROADWELL_D 0x56 #define INTEL_BROADWELL_D IFM(6, 0x56) =20 -#define INTEL_FAM6_SKYLAKE_L 0x4E /* Sky Lake */ #define INTEL_SKYLAKE_L IFM(6, 0x4E) /* Sky Lake */ -#define INTEL_FAM6_SKYLAKE 0x5E /* Sky Lake */ #define INTEL_SKYLAKE IFM(6, 0x5E) /* Sky Lake */ -#define INTEL_FAM6_SKYLAKE_X 0x55 /* Sky Lake */ #define INTEL_SKYLAKE_X IFM(6, 0x55) /* Sky Lake */ /* CASCADELAKE_X 0x55 Sky Lake -- s: 7 */ /* COOPERLAKE_X 0x55 Sky Lake -- s: 11 */ =20 -#define INTEL_FAM6_KABYLAKE_L 0x8E /* Sky Lake */ #define INTEL_KABYLAKE_L IFM(6, 0x8E) /* Sky Lake */ /* AMBERLAKE_L 0x8E Sky Lake -- s: 9 */ /* COFFEELAKE_L 0x8E Sky Lake -- s: 10 */ /* WHISKEYLAKE_L 0x8E Sky Lake -- s: 11,12 */ =20 -#define INTEL_FAM6_KABYLAKE 0x9E /* Sky Lake */ #define INTEL_KABYLAKE IFM(6, 0x9E) /* Sky Lake */ /* COFFEELAKE 0x9E Sky Lake -- s: 10-13 */ =20 -#define INTEL_FAM6_COMETLAKE 0xA5 /* Sky Lake */ #define INTEL_COMETLAKE IFM(6, 0xA5) /* Sky Lake */ -#define INTEL_FAM6_COMETLAKE_L 0xA6 /* Sky Lake */ #define INTEL_COMETLAKE_L IFM(6, 0xA6) /* Sky Lake */ =20 -#define INTEL_FAM6_CANNONLAKE_L 0x66 /* Palm Cove */ #define INTEL_CANNONLAKE_L IFM(6, 0x66) /* Palm Cove */ =20 -#define INTEL_FAM6_ICELAKE_X 0x6A /* Sunny Cove */ #define INTEL_ICELAKE_X IFM(6, 0x6A) /* Sunny Cove */ -#define INTEL_FAM6_ICELAKE_D 0x6C /* Sunny Cove */ #define INTEL_ICELAKE_D IFM(6, 0x6C) /* Sunny Cove */ -#define INTEL_FAM6_ICELAKE 0x7D /* Sunny Cove */ #define INTEL_ICELAKE IFM(6, 0x7D) /* Sunny Cove */ -#define INTEL_FAM6_ICELAKE_L 0x7E /* Sunny Cove */ #define INTEL_ICELAKE_L IFM(6, 0x7E) /* Sunny Cove */ -#define INTEL_FAM6_ICELAKE_NNPI 0x9D /* Sunny Cove */ #define INTEL_ICELAKE_NNPI IFM(6, 0x9D) /* Sunny Cove */ =20 -#define INTEL_FAM6_ROCKETLAKE 0xA7 /* Cypress Cove */ #define INTEL_ROCKETLAKE IFM(6, 0xA7) /* Cypress Cove */ =20 -#define INTEL_FAM6_TIGERLAKE_L 0x8C /* Willow Cove */ #define INTEL_TIGERLAKE_L IFM(6, 0x8C) /* Willow Cove */ -#define INTEL_FAM6_TIGERLAKE 0x8D /* Willow Cove */ #define INTEL_TIGERLAKE IFM(6, 0x8D) /* Willow Cove */ =20 -#define INTEL_FAM6_SAPPHIRERAPIDS_X 0x8F /* Golden Cove */ #define INTEL_SAPPHIRERAPIDS_X IFM(6, 0x8F) /* Golden Cove */ =20 -#define INTEL_FAM6_EMERALDRAPIDS_X 0xCF #define INTEL_EMERALDRAPIDS_X IFM(6, 0xCF) =20 -#define INTEL_FAM6_GRANITERAPIDS_X 0xAD #define INTEL_GRANITERAPIDS_X IFM(6, 0xAD) -#define INTEL_FAM6_GRANITERAPIDS_D 0xAE #define INTEL_GRANITERAPIDS_D IFM(6, 0xAE) =20 /* "Hybrid" Processors (P-Core/E-Core) */ =20 -#define INTEL_FAM6_LAKEFIELD 0x8A /* Sunny Cove / Tremont */ #define INTEL_LAKEFIELD IFM(6, 0x8A) /* Sunny Cove / Tremont */ =20 -#define INTEL_FAM6_ALDERLAKE 0x97 /* Golden Cove / Gracemont */ #define INTEL_ALDERLAKE IFM(6, 0x97) /* Golden Cove / Gracemont */ -#define INTEL_FAM6_ALDERLAKE_L 0x9A /* Golden Cove / Gracemont */ #define INTEL_ALDERLAKE_L IFM(6, 0x9A) /* Golden Cove / Gracemont */ =20 -#define INTEL_FAM6_RAPTORLAKE 0xB7 /* Raptor Cove / Enhanced Gracemont */ #define INTEL_RAPTORLAKE IFM(6, 0xB7) /* Raptor Cove / Enhanced Gracemont= */ -#define INTEL_FAM6_RAPTORLAKE_P 0xBA #define INTEL_RAPTORLAKE_P IFM(6, 0xBA) -#define INTEL_FAM6_RAPTORLAKE_S 0xBF #define INTEL_RAPTORLAKE_S IFM(6, 0xBF) =20 -#define INTEL_FAM6_METEORLAKE 0xAC #define INTEL_METEORLAKE IFM(6, 0xAC) -#define INTEL_FAM6_METEORLAKE_L 0xAA #define INTEL_METEORLAKE_L IFM(6, 0xAA) =20 -#define INTEL_FAM6_ARROWLAKE_H 0xC5 #define INTEL_ARROWLAKE_H IFM(6, 0xC5) -#define INTEL_FAM6_ARROWLAKE 0xC6 #define INTEL_ARROWLAKE IFM(6, 0xC6) -#define INTEL_FAM6_ARROWLAKE_U 0xB5 #define INTEL_ARROWLAKE_U IFM(6, 0xB5) =20 -#define INTEL_FAM6_LUNARLAKE_M 0xBD #define INTEL_LUNARLAKE_M IFM(6, 0xBD) =20 /* "Small Core" Processors (Atom/E-Core) */ =20 -#define INTEL_FAM6_ATOM_BONNELL 0x1C /* Diamondville, Pineview */ #define INTEL_ATOM_BONNELL IFM(6, 0x1C) /* Diamondville, Pineview */ -#define INTEL_FAM6_ATOM_BONNELL_MID 0x26 /* Silverthorne, Lincroft */ #define INTEL_ATOM_BONNELL_MID IFM(6, 0x26) /* Silverthorne, Lincroft */ =20 -#define INTEL_FAM6_ATOM_SALTWELL 0x36 /* Cedarview */ #define INTEL_ATOM_SALTWELL IFM(6, 0x36) /* Cedarview */ -#define INTEL_FAM6_ATOM_SALTWELL_MID 0x27 /* Penwell */ #define INTEL_ATOM_SALTWELL_MID IFM(6, 0x27) /* Penwell */ -#define INTEL_FAM6_ATOM_SALTWELL_TABLET 0x35 /* Cloverview */ #define INTEL_ATOM_SALTWELL_TABLET IFM(6, 0x35) /* Cloverview */ =20 -#define INTEL_FAM6_ATOM_SILVERMONT 0x37 /* Bay Trail, Valleyview */ #define INTEL_ATOM_SILVERMONT IFM(6, 0x37) /* Bay Trail, Valleyview */ -#define INTEL_FAM6_ATOM_SILVERMONT_D 0x4D /* Avaton, Rangely */ #define INTEL_ATOM_SILVERMONT_D IFM(6, 0x4D) /* Avaton, Rangely */ -#define INTEL_FAM6_ATOM_SILVERMONT_MID 0x4A /* Merriefield */ #define INTEL_ATOM_SILVERMONT_MID IFM(6, 0x4A) /* Merriefield */ =20 -#define INTEL_FAM6_ATOM_AIRMONT 0x4C /* Cherry Trail, Braswell */ #define INTEL_ATOM_AIRMONT IFM(6, 0x4C) /* Cherry Trail, Braswell */ -#define INTEL_FAM6_ATOM_AIRMONT_MID 0x5A /* Moorefield */ #define INTEL_ATOM_AIRMONT_MID IFM(6, 0x5A) /* Moorefield */ -#define INTEL_FAM6_ATOM_AIRMONT_NP 0x75 /* Lightning Mountain */ #define INTEL_ATOM_AIRMONT_NP IFM(6, 0x75) /* Lightning Mountain */ =20 -#define INTEL_FAM6_ATOM_GOLDMONT 0x5C /* Apollo Lake */ #define INTEL_ATOM_GOLDMONT IFM(6, 0x5C) /* Apollo Lake */ -#define INTEL_FAM6_ATOM_GOLDMONT_D 0x5F /* Denverton */ #define INTEL_ATOM_GOLDMONT_D IFM(6, 0x5F) /* Denverton */ =20 /* Note: the micro-architecture is "Goldmont Plus" */ -#define INTEL_FAM6_ATOM_GOLDMONT_PLUS 0x7A /* Gemini Lake */ #define INTEL_ATOM_GOLDMONT_PLUS IFM(6, 0x7A) /* Gemini Lake */ =20 -#define INTEL_FAM6_ATOM_TREMONT_D 0x86 /* Jacobsville */ #define INTEL_ATOM_TREMONT_D IFM(6, 0x86) /* Jacobsville */ -#define INTEL_FAM6_ATOM_TREMONT 0x96 /* Elkhart Lake */ #define INTEL_ATOM_TREMONT IFM(6, 0x96) /* Elkhart Lake */ -#define INTEL_FAM6_ATOM_TREMONT_L 0x9C /* Jasper Lake */ #define INTEL_ATOM_TREMONT_L IFM(6, 0x9C) /* Jasper Lake */ =20 -#define INTEL_FAM6_ATOM_GRACEMONT 0xBE /* Alderlake N */ #define INTEL_ATOM_GRACEMONT IFM(6, 0xBE) /* Alderlake N */ =20 -#define INTEL_FAM6_ATOM_CRESTMONT_X 0xAF /* Sierra Forest */ #define INTEL_ATOM_CRESTMONT_X IFM(6, 0xAF) /* Sierra Forest */ -#define INTEL_FAM6_ATOM_CRESTMONT 0xB6 /* Grand Ridge */ #define INTEL_ATOM_CRESTMONT IFM(6, 0xB6) /* Grand Ridge */ =20 -#define INTEL_FAM6_ATOM_DARKMONT_X 0xDD /* Clearwater Forest */ #define INTEL_ATOM_DARKMONT_X IFM(6, 0xDD) /* Clearwater Forest */ =20 /* Xeon Phi */ =20 -#define INTEL_FAM6_XEON_PHI_KNL 0x57 /* Knights Landing */ #define INTEL_XEON_PHI_KNL IFM(6, 0x57) /* Knights Landing */ -#define INTEL_FAM6_XEON_PHI_KNM 0x85 /* Knights Mill */ #define INTEL_XEON_PHI_KNM IFM(6, 0x85) /* Knights Mill */ =20 /* Family 5 */ --=20 2.44.0