From nobody Mon Jun 10 04:54:12 2024 Received: from mailgw01.mediatek.com (unknown [60.244.123.138]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 53BE4339A1; Wed, 24 Apr 2024 03:04:23 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=60.244.123.138 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1713927866; cv=none; b=Nn1GArESgKC6wj/hTIEpwi04tdg7l7TEnlF81AU576sAyg8dLBOCnlUqz8te2nxQ4a8E3lUm95jkRo1IX4cgh/SVmspGPuG+EWzf7YXvuvV8CUkz6JapUwgm0DC1lIENruanOZM/07ZsSXeu9FfLrWpbA5M8Ati6dGWOgYnRXVk= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1713927866; c=relaxed/simple; bh=TxQHHD8ReW3yKrct5j+9dICT7Gj2PjIjiCUfAWik3tI=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=at55p7Jc1jCmk8bvPcImhg1niBC1WZR8fLUfqERcy3W9YDUANKdRaNeAqziSTlVhqFkh0LZkXuItVoMRFzcpGqr5AOPv7NcjVzckKI+PiuvmPiHdHXPYPAkyejnORo8BhdJ6/BdDHI3v0xQU4LnUC8qvy3FOOZyCE9VVsvlKIp4= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=mediatek.com; spf=pass smtp.mailfrom=mediatek.com; dkim=pass (1024-bit key) header.d=mediatek.com header.i=@mediatek.com header.b=D933Vinz; arc=none smtp.client-ip=60.244.123.138 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=mediatek.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=mediatek.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=mediatek.com header.i=@mediatek.com header.b="D933Vinz" X-UUID: 575f6a6e01e711efb8927bc1f75efef4-20240424 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Type:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=YVDy5/ZsVM8z4DOMITGRoXpjJasjzOPGDsnn36hyu4g=; b=D933VinzE674GWPK/IWs01BE6LAX3dMgZRG6qLjIgy0UVZwQZzKR+0+AQM0q1d+aj75UWvn5cLjSAHXDUfp6yF5h9vobztapaDVzPZNyxmF7rxUa1ZqH/afrjpwooFLrL7C3fbkpjeHSyUQIn3WlK9AzqfuEMrMhOiUZoLrWwCw=; X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.38,REQID:146e1982-69cf-45ff-a786-c3ae0b2e57e6,IP:0,U RL:0,TC:0,Content:0,EDM:0,RT:0,SF:0,FILE:0,BULK:0,RULE:Release_Ham,ACTION: release,TS:0 X-CID-META: VersionHash:82c5f88,CLOUDID:80d646fb-ed05-4274-9204-014369d201e8,B ulkID:nil,BulkQuantity:0,Recheck:0,SF:102,TC:nil,Content:0,EDM:-3,IP:nil,U RL:0,File:nil,RT:nil,Bulk:nil,QS:nil,BEC:nil,COL:0,OSI:0,OSA:0,AV:0,LES:1, SPR:NO,DKR:0,DKP:0,BRR:0,BRE:0 X-CID-BVR: 0 X-CID-BAS: 0,_,0,_ X-CID-FACTOR: TF_CID_SPAM_SNR X-UUID: 575f6a6e01e711efb8927bc1f75efef4-20240424 Received: from mtkmbs10n1.mediatek.inc [(172.21.101.34)] by mailgw01.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-GCM-SHA384 256/256) with ESMTP id 131397520; Wed, 24 Apr 2024 11:04:18 +0800 Received: from mtkmbs13n2.mediatek.inc (172.21.101.108) by mtkmbs10n1.mediatek.inc (172.21.101.34) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.26; Wed, 24 Apr 2024 11:04:15 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkmbs13n2.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.1118.26 via Frontend Transport; Wed, 24 Apr 2024 11:04:15 +0800 From: Olivia Wen To: Bjorn Andersson , Mathieu Poirier , Rob Herring CC: Krzysztof Kozlowski , Conor Dooley , Matthias Brugger , AngeloGioacchino Del Regno , "Tinghan Shen" , , , , , , , , , , Subject: [PATCH v3 1/4] dt-bindings: remoteproc: mediatek: Support MT8188 dual-core SCP Date: Wed, 24 Apr 2024 11:03:48 +0800 Message-ID: <20240424030351.5294-2-olivia.wen@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20240424030351.5294-1-olivia.wen@mediatek.com> References: <20240424030351.5294-1-olivia.wen@mediatek.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-TM-AS-Product-Ver: SMEX-14.0.0.3152-9.1.1006-23728.005 X-TM-AS-Result: No-10--0.711500-8.000000 X-TMASE-MatchedRID: eTEFbZ6VJO5jVtAwIy+afmHn2exfZC4LdER46uj876/oFeE5MSxNMeLz NWBegCW2wgn7iDBesS0nRE+fI6etkpar3ceJGClgN1rcfctnT3I4Cy/AjbisqpGJB31mduCgnJw vO47B+KCM47hkifH+EQ6x/CJdSYheO29r+zoVSuuTp+MobLNv/ICE5xpCtDRTUbJFyh4XXyqYo/ TPOlMB4bCh3zE4wqa8DUCRr8oin+k= X-TM-AS-User-Approved-Sender: No X-TM-AS-User-Blocked-Sender: No X-TMASE-Result: 10--0.711500-8.000000 X-TMASE-Version: SMEX-14.0.0.3152-9.1.1006-23728.005 X-TM-SNTS-SMTP: 51EDF03EB993C1CB263B9901CEAEEBE8EED93A620167DDC423AC0563D5D95B982000:8 X-MTK: N Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Under different applications, the MT8188 SCP can be used as single-core or dual-core. Signed-off-by: Olivia Wen Acked-by: Krzysztof Kozlowski Reviewed-by: AngeloGioacchino Del Regno --- Documentation/devicetree/bindings/remoteproc/mtk,scp.yaml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/remoteproc/mtk,scp.yaml b/Do= cumentation/devicetree/bindings/remoteproc/mtk,scp.yaml index 507f98f..c5dc3c2 100644 --- a/Documentation/devicetree/bindings/remoteproc/mtk,scp.yaml +++ b/Documentation/devicetree/bindings/remoteproc/mtk,scp.yaml @@ -19,6 +19,7 @@ properties: - mediatek,mt8183-scp - mediatek,mt8186-scp - mediatek,mt8188-scp + - mediatek,mt8188-scp-dual - mediatek,mt8192-scp - mediatek,mt8195-scp - mediatek,mt8195-scp-dual @@ -194,6 +195,7 @@ allOf: properties: compatible: enum: + - mediatek,mt8188-scp-dual - mediatek,mt8195-scp-dual then: properties: --=20 2.6.4 From nobody Mon Jun 10 04:54:12 2024 Received: from mailgw02.mediatek.com (unknown [210.61.82.184]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 9109A84DF9; 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Wed, 24 Apr 2024 11:04:17 +0800 Received: from mtkmbs13n2.mediatek.inc (172.21.101.108) by mtkmbs13n2.mediatek.inc (172.21.101.108) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.26; Wed, 24 Apr 2024 11:04:15 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkmbs13n2.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.1118.26 via Frontend Transport; Wed, 24 Apr 2024 11:04:15 +0800 From: Olivia Wen To: Bjorn Andersson , Mathieu Poirier , Rob Herring CC: Krzysztof Kozlowski , Conor Dooley , Matthias Brugger , AngeloGioacchino Del Regno , Tinghan Shen , , , , , , , , , , Subject: [PATCH v3 2/4] remoteproc: mediatek: Support MT8188 SCP core 1 Date: Wed, 24 Apr 2024 11:03:49 +0800 Message-ID: <20240424030351.5294-3-olivia.wen@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20240424030351.5294-1-olivia.wen@mediatek.com> References: <20240424030351.5294-1-olivia.wen@mediatek.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MTK: N Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" MT8188 SCP has two RISC-V cores which is similar to MT8195 but without L1TCM. We've added MT8188-specific functions to configure L1TCM in multicore setups. Signed-off-by: Olivia Wen Reviewed-by: AngeloGioacchino Del Regno --- drivers/remoteproc/mtk_scp.c | 146 +++++++++++++++++++++++++++++++++++++++= +++- 1 file changed, 143 insertions(+), 3 deletions(-) diff --git a/drivers/remoteproc/mtk_scp.c b/drivers/remoteproc/mtk_scp.c index 6751829..6295148 100644 --- a/drivers/remoteproc/mtk_scp.c +++ b/drivers/remoteproc/mtk_scp.c @@ -471,6 +471,86 @@ static int mt8186_scp_before_load(struct mtk_scp *scp) return 0; } =20 +static int mt8188_scp_l2tcm_on(struct mtk_scp *scp) +{ + struct mtk_scp_of_cluster *scp_cluster =3D scp->cluster; + + mutex_lock(&scp_cluster->cluster_lock); + + if (scp_cluster->l2tcm_refcnt =3D=3D 0) { + /* clear SPM interrupt, SCP2SPM_IPC_CLR */ + writel(0xff, scp->cluster->reg_base + MT8192_SCP2SPM_IPC_CLR); + + /* Power on L2TCM */ + scp_sram_power_on(scp->cluster->reg_base + MT8192_L2TCM_SRAM_PD_0, 0); + scp_sram_power_on(scp->cluster->reg_base + MT8192_L2TCM_SRAM_PD_1, 0); + scp_sram_power_on(scp->cluster->reg_base + MT8192_L2TCM_SRAM_PD_2, 0); + scp_sram_power_on(scp->cluster->reg_base + MT8192_L1TCM_SRAM_PDN, 0); + } + + scp_cluster->l2tcm_refcnt +=3D 1; + + mutex_unlock(&scp_cluster->cluster_lock); + + return 0; +} + +static int mt8188_scp_before_load(struct mtk_scp *scp) +{ + writel(1, scp->cluster->reg_base + MT8192_CORE0_SW_RSTN_SET); + + mt8188_scp_l2tcm_on(scp); + + scp_sram_power_on(scp->cluster->reg_base + MT8192_CPU0_SRAM_PD, 0); + + /* enable MPU for all memory regions */ + writel(0xff, scp->cluster->reg_base + MT8192_CORE0_MEM_ATT_PREDEF); + + return 0; +} + +static int mt8188_scp_c1_before_load(struct mtk_scp *scp) +{ + u32 sec_ctrl; + struct mtk_scp *scp_c0; + struct mtk_scp_of_cluster *scp_cluster =3D scp->cluster; + + scp->data->scp_reset_assert(scp); + + mt8188_scp_l2tcm_on(scp); + + scp_sram_power_on(scp->cluster->reg_base + MT8195_CPU1_SRAM_PD, 0); + + /* enable MPU for all memory regions */ + writel(0xff, scp->cluster->reg_base + MT8195_CORE1_MEM_ATT_PREDEF); + + /* + * The L2TCM_OFFSET_RANGE and L2TCM_OFFSET shift the destination address + * on SRAM when SCP core 1 accesses SRAM. + * + * This configuration solves booting the SCP core 0 and core 1 from + * different SRAM address because core 0 and core 1 both boot from + * the head of SRAM by default. this must be configured before boot SCP c= ore 1. + * + * The value of L2TCM_OFFSET_RANGE is from the viewpoint of SCP core 1. + * When SCP core 1 issues address within the range (L2TCM_OFFSET_RANGE), + * the address will be added with a fixed offset (L2TCM_OFFSET) on the bu= s. + * The shift action is tranparent to software. + */ + writel(0, scp->cluster->reg_base + MT8195_L2TCM_OFFSET_RANGE_0_LOW); + writel(scp->sram_size, scp->cluster->reg_base + MT8195_L2TCM_OFFSET_RANGE= _0_HIGH); + + scp_c0 =3D list_first_entry(&scp_cluster->mtk_scp_list, struct mtk_scp, e= lem); + writel(scp->sram_phys - scp_c0->sram_phys, scp->cluster->reg_base + MT819= 5_L2TCM_OFFSET); + + /* enable SRAM offset when fetching instruction and data */ + sec_ctrl =3D readl(scp->cluster->reg_base + MT8195_SEC_CTRL); + sec_ctrl |=3D MT8195_CORE_OFFSET_ENABLE_I | MT8195_CORE_OFFSET_ENABLE_D; + writel(sec_ctrl, scp->cluster->reg_base + MT8195_SEC_CTRL); + + return 0; +} + static int mt8192_scp_before_load(struct mtk_scp *scp) { /* clear SPM interrupt, SCP2SPM_IPC_CLR */ @@ -717,6 +797,47 @@ static void mt8183_scp_stop(struct mtk_scp *scp) writel(0, scp->cluster->reg_base + MT8183_WDT_CFG); } =20 +static void mt8188_scp_l2tcm_off(struct mtk_scp *scp) +{ + struct mtk_scp_of_cluster *scp_cluster =3D scp->cluster; + + mutex_lock(&scp_cluster->cluster_lock); + + if (scp_cluster->l2tcm_refcnt > 0) + scp_cluster->l2tcm_refcnt -=3D 1; + + if (scp_cluster->l2tcm_refcnt =3D=3D 0) { + /* Power off L2TCM */ + scp_sram_power_off(scp->cluster->reg_base + MT8192_L2TCM_SRAM_PD_0, 0); + scp_sram_power_off(scp->cluster->reg_base + MT8192_L2TCM_SRAM_PD_1, 0); + scp_sram_power_off(scp->cluster->reg_base + MT8192_L2TCM_SRAM_PD_2, 0); + scp_sram_power_off(scp->cluster->reg_base + MT8192_L1TCM_SRAM_PDN, 0); + } + + mutex_unlock(&scp_cluster->cluster_lock); +} + +static void mt8188_scp_stop(struct mtk_scp *scp) +{ + mt8188_scp_l2tcm_off(scp); + + scp_sram_power_off(scp->cluster->reg_base + MT8192_CPU0_SRAM_PD, 0); + + /* Disable SCP watchdog */ + writel(0, scp->cluster->reg_base + MT8192_CORE0_WDT_CFG); +} + +static void mt8188_scp_c1_stop(struct mtk_scp *scp) +{ + mt8188_scp_l2tcm_off(scp); + + /* Power off CPU SRAM */ + scp_sram_power_off(scp->cluster->reg_base + MT8195_CPU1_SRAM_PD, 0); + + /* Disable SCP watchdog */ + writel(0, scp->cluster->reg_base + MT8195_CORE1_WDT_CFG); +} + static void mt8192_scp_stop(struct mtk_scp *scp) { /* Disable SRAM clock */ @@ -1264,16 +1385,28 @@ static const struct mtk_scp_of_data mt8186_of_data = =3D { =20 static const struct mtk_scp_of_data mt8188_of_data =3D { .scp_clk_get =3D mt8195_scp_clk_get, - .scp_before_load =3D mt8192_scp_before_load, - .scp_irq_handler =3D mt8192_scp_irq_handler, + .scp_before_load =3D mt8188_scp_before_load, + .scp_irq_handler =3D mt8195_scp_irq_handler, .scp_reset_assert =3D mt8192_scp_reset_assert, .scp_reset_deassert =3D mt8192_scp_reset_deassert, - .scp_stop =3D mt8192_scp_stop, + .scp_stop =3D mt8188_scp_stop, .scp_da_to_va =3D mt8192_scp_da_to_va, .host_to_scp_reg =3D MT8192_GIPC_IN_SET, .host_to_scp_int_bit =3D MT8192_HOST_IPC_INT_BIT, }; =20 +static const struct mtk_scp_of_data mt8188_of_data_c1 =3D { + .scp_clk_get =3D mt8195_scp_clk_get, + .scp_before_load =3D mt8188_scp_c1_before_load, + .scp_irq_handler =3D mt8195_scp_c1_irq_handler, + .scp_reset_assert =3D mt8195_scp_c1_reset_assert, + .scp_reset_deassert =3D mt8195_scp_c1_reset_deassert, + .scp_stop =3D mt8188_scp_c1_stop, + .scp_da_to_va =3D mt8192_scp_da_to_va, + .host_to_scp_reg =3D MT8192_GIPC_IN_SET, + .host_to_scp_int_bit =3D MT8195_CORE1_HOST_IPC_INT_BIT, +}; + static const struct mtk_scp_of_data mt8192_of_data =3D { .scp_clk_get =3D mt8192_scp_clk_get, .scp_before_load =3D mt8192_scp_before_load, @@ -1310,6 +1443,12 @@ static const struct mtk_scp_of_data mt8195_of_data_c= 1 =3D { .host_to_scp_int_bit =3D MT8195_CORE1_HOST_IPC_INT_BIT, }; =20 +static const struct mtk_scp_of_data *mt8188_of_data_cores[] =3D { + &mt8188_of_data, + &mt8188_of_data_c1, + NULL +}; + static const struct mtk_scp_of_data *mt8195_of_data_cores[] =3D { &mt8195_of_data, &mt8195_of_data_c1, @@ -1320,6 +1459,7 @@ static const struct of_device_id mtk_scp_of_match[] = =3D { { .compatible =3D "mediatek,mt8183-scp", .data =3D &mt8183_of_data }, { .compatible =3D "mediatek,mt8186-scp", .data =3D &mt8186_of_data }, { .compatible =3D "mediatek,mt8188-scp", .data =3D &mt8188_of_data }, + { .compatible =3D "mediatek,mt8188-scp-dual", .data =3D &mt8188_of_data_c= ores }, { .compatible =3D "mediatek,mt8192-scp", .data =3D &mt8192_of_data }, { .compatible =3D "mediatek,mt8195-scp", .data =3D &mt8195_of_data }, { .compatible =3D "mediatek,mt8195-scp-dual", .data =3D &mt8195_of_data_c= ores }, --=20 2.6.4 From nobody Mon Jun 10 04:54:12 2024 Received: from mailgw02.mediatek.com (unknown [210.61.82.184]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E98511292E9; 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charset="utf-8" The SCP on different chips will require different DRAM sizes and IPI shared buffer sizes based on varying requirements. Signed-off-by: Olivia Wen Reviewed-by: AngeloGioacchino Del Regno --- drivers/remoteproc/mtk_common.h | 11 ++++-- drivers/remoteproc/mtk_scp.c | 84 +++++++++++++++++++++++++++++++-----= ---- drivers/remoteproc/mtk_scp_ipi.c | 7 +++- 3 files changed, 79 insertions(+), 23 deletions(-) diff --git a/drivers/remoteproc/mtk_common.h b/drivers/remoteproc/mtk_commo= n.h index 6d7736a..fd5c539 100644 --- a/drivers/remoteproc/mtk_common.h +++ b/drivers/remoteproc/mtk_common.h @@ -78,7 +78,6 @@ #define MT8195_L2TCM_OFFSET 0x850d0 =20 #define SCP_FW_VER_LEN 32 -#define SCP_SHARE_BUFFER_SIZE 288 =20 struct scp_run { u32 signaled; @@ -97,6 +96,11 @@ struct scp_ipi_desc { =20 struct mtk_scp; =20 +struct mtk_scp_sizes_data { + size_t max_dram_size; + size_t ipi_share_buffer_size; +}; + struct mtk_scp_of_data { int (*scp_clk_get)(struct mtk_scp *scp); int (*scp_before_load)(struct mtk_scp *scp); @@ -110,6 +114,7 @@ struct mtk_scp_of_data { u32 host_to_scp_int_bit; =20 size_t ipi_buf_offset; + const struct mtk_scp_sizes_data *scp_sizes; }; =20 struct mtk_scp_of_cluster { @@ -141,10 +146,10 @@ struct mtk_scp { struct scp_ipi_desc ipi_desc[SCP_IPI_MAX]; bool ipi_id_ack[SCP_IPI_MAX]; wait_queue_head_t ack_wq; + u8 *share_buf; =20 void *cpu_addr; dma_addr_t dma_addr; - size_t dram_size; =20 struct rproc_subdev *rpmsg_subdev; =20 @@ -162,7 +167,7 @@ struct mtk_scp { struct mtk_share_obj { u32 id; u32 len; - u8 share_buf[SCP_SHARE_BUFFER_SIZE]; + u8 *share_buf; }; =20 void scp_memcpy_aligned(void __iomem *dst, const void *src, unsigned int l= en); diff --git a/drivers/remoteproc/mtk_scp.c b/drivers/remoteproc/mtk_scp.c index 6295148..e281d28 100644 --- a/drivers/remoteproc/mtk_scp.c +++ b/drivers/remoteproc/mtk_scp.c @@ -20,7 +20,6 @@ #include "mtk_common.h" #include "remoteproc_internal.h" =20 -#define MAX_CODE_SIZE 0x500000 #define SECTION_NAME_IPI_BUFFER ".ipi_buffer" =20 /** @@ -94,14 +93,15 @@ static void scp_ipi_handler(struct mtk_scp *scp) { struct mtk_share_obj __iomem *rcv_obj =3D scp->recv_buf; struct scp_ipi_desc *ipi_desc =3D scp->ipi_desc; - u8 tmp_data[SCP_SHARE_BUFFER_SIZE]; scp_ipi_handler_t handler; u32 id =3D readl(&rcv_obj->id); u32 len =3D readl(&rcv_obj->len); + const struct mtk_scp_sizes_data *scp_sizes; =20 - if (len > SCP_SHARE_BUFFER_SIZE) { - dev_err(scp->dev, "ipi message too long (len %d, max %d)", len, - SCP_SHARE_BUFFER_SIZE); + scp_sizes =3D scp->data->scp_sizes; + if (len > scp_sizes->ipi_share_buffer_size) { + dev_err(scp->dev, "ipi message too long (len %d, max %zd)", len, + scp_sizes->ipi_share_buffer_size); return; } if (id >=3D SCP_IPI_MAX) { @@ -117,8 +117,9 @@ static void scp_ipi_handler(struct mtk_scp *scp) return; } =20 - memcpy_fromio(tmp_data, &rcv_obj->share_buf, len); - handler(tmp_data, len, ipi_desc[id].priv); + memset(scp->share_buf, 0, scp_sizes->ipi_share_buffer_size); + memcpy_fromio(scp->share_buf, &rcv_obj->share_buf, len); + handler(scp->share_buf, len, ipi_desc[id].priv); scp_ipi_unlock(scp, id); =20 scp->ipi_id_ack[id] =3D true; @@ -133,6 +134,8 @@ static int scp_ipi_init(struct mtk_scp *scp, const stru= ct firmware *fw) { int ret; size_t buf_sz, offset; + size_t share_buf_offset; + const struct mtk_scp_sizes_data *scp_sizes; =20 /* read the ipi buf addr from FW itself first */ ret =3D scp_elf_read_ipi_buf_addr(scp, fw, &offset); @@ -152,12 +155,15 @@ static int scp_ipi_init(struct mtk_scp *scp, const st= ruct firmware *fw) return -EOVERFLOW; } =20 + scp_sizes =3D scp->data->scp_sizes; scp->recv_buf =3D (struct mtk_share_obj __iomem *) (scp->sram_base + offset); + share_buf_offset =3D sizeof(scp->recv_buf->id) + + sizeof(scp->recv_buf->len) + scp_sizes->ipi_share_buffer_size; scp->send_buf =3D (struct mtk_share_obj __iomem *) - (scp->sram_base + offset + sizeof(*scp->recv_buf)); - memset_io(scp->recv_buf, 0, sizeof(*scp->recv_buf)); - memset_io(scp->send_buf, 0, sizeof(*scp->send_buf)); + (scp->sram_base + offset + share_buf_offset); + memset_io(scp->recv_buf, 0, share_buf_offset); + memset_io(scp->send_buf, 0, share_buf_offset); =20 return 0; } @@ -741,14 +747,16 @@ static int scp_start(struct rproc *rproc) static void *mt8183_scp_da_to_va(struct mtk_scp *scp, u64 da, size_t len) { int offset; + const struct mtk_scp_sizes_data *scp_sizes; =20 + scp_sizes =3D scp->data->scp_sizes; if (da < scp->sram_size) { offset =3D da; if (offset >=3D 0 && (offset + len) <=3D scp->sram_size) return (void __force *)scp->sram_base + offset; - } else if (scp->dram_size) { + } else if (scp_sizes->max_dram_size) { offset =3D da - scp->dma_addr; - if (offset >=3D 0 && (offset + len) <=3D scp->dram_size) + if (offset >=3D 0 && (offset + len) <=3D scp_sizes->max_dram_size) return scp->cpu_addr + offset; } =20 @@ -758,7 +766,9 @@ static void *mt8183_scp_da_to_va(struct mtk_scp *scp, u= 64 da, size_t len) static void *mt8192_scp_da_to_va(struct mtk_scp *scp, u64 da, size_t len) { int offset; + const struct mtk_scp_sizes_data *scp_sizes; =20 + scp_sizes =3D scp->data->scp_sizes; if (da >=3D scp->sram_phys && (da + len) <=3D scp->sram_phys + scp->sram_size) { offset =3D da - scp->sram_phys; @@ -774,9 +784,9 @@ static void *mt8192_scp_da_to_va(struct mtk_scp *scp, u= 64 da, size_t len) } =20 /* optional memory region */ - if (scp->dram_size && + if (scp_sizes->max_dram_size && da >=3D scp->dma_addr && - (da + len) <=3D scp->dma_addr + scp->dram_size) { + (da + len) <=3D scp->dma_addr + scp_sizes->max_dram_size) { offset =3D da - scp->dma_addr; return scp->cpu_addr + offset; } @@ -997,6 +1007,7 @@ EXPORT_SYMBOL_GPL(scp_mapping_dm_addr); static int scp_map_memory_region(struct mtk_scp *scp) { int ret; + const struct mtk_scp_sizes_data *scp_sizes; =20 ret =3D of_reserved_mem_device_init(scp->dev); =20 @@ -1012,8 +1023,8 @@ static int scp_map_memory_region(struct mtk_scp *scp) } =20 /* Reserved SCP code size */ - scp->dram_size =3D MAX_CODE_SIZE; - scp->cpu_addr =3D dma_alloc_coherent(scp->dev, scp->dram_size, + scp_sizes =3D scp->data->scp_sizes; + scp->cpu_addr =3D dma_alloc_coherent(scp->dev, scp_sizes->max_dram_size, &scp->dma_addr, GFP_KERNEL); if (!scp->cpu_addr) return -ENOMEM; @@ -1023,10 +1034,13 @@ static int scp_map_memory_region(struct mtk_scp *sc= p) =20 static void scp_unmap_memory_region(struct mtk_scp *scp) { - if (scp->dram_size =3D=3D 0) + const struct mtk_scp_sizes_data *scp_sizes; + + scp_sizes =3D scp->data->scp_sizes; + if (scp_sizes->max_dram_size =3D=3D 0) return; =20 - dma_free_coherent(scp->dev, scp->dram_size, scp->cpu_addr, + dma_free_coherent(scp->dev, scp_sizes->max_dram_size, scp->cpu_addr, scp->dma_addr); of_reserved_mem_device_release(scp->dev); } @@ -1090,6 +1104,7 @@ static struct mtk_scp *scp_rproc_init(struct platform= _device *pdev, struct resource *res; const char *fw_name =3D "scp.img"; int ret, i; + const struct mtk_scp_sizes_data *scp_sizes; =20 ret =3D rproc_of_parse_firmware(dev, 0, &fw_name); if (ret < 0 && ret !=3D -EINVAL) @@ -1137,6 +1152,13 @@ static struct mtk_scp *scp_rproc_init(struct platfor= m_device *pdev, goto release_dev_mem; } =20 + scp_sizes =3D scp->data->scp_sizes; + scp->share_buf =3D kzalloc(scp_sizes->ipi_share_buffer_size, GFP_KERNEL); + if (!scp->share_buf) { + dev_err(dev, "Failed to allocate IPI share buffer\n"); + goto release_dev_mem; + } + init_waitqueue_head(&scp->run.wq); init_waitqueue_head(&scp->ack_wq); =20 @@ -1156,6 +1178,8 @@ static struct mtk_scp *scp_rproc_init(struct platform= _device *pdev, remove_subdev: scp_remove_rpmsg_subdev(scp); scp_ipi_unregister(scp, SCP_IPI_INIT); + kfree(scp->share_buf); + scp->share_buf =3D NULL; release_dev_mem: scp_unmap_memory_region(scp); for (i =3D 0; i < SCP_IPI_MAX; i++) @@ -1171,6 +1195,8 @@ static void scp_free(struct mtk_scp *scp) =20 scp_remove_rpmsg_subdev(scp); scp_ipi_unregister(scp, SCP_IPI_INIT); + kfree(scp->share_buf); + scp->share_buf =3D NULL; scp_unmap_memory_region(scp); for (i =3D 0; i < SCP_IPI_MAX; i++) mutex_destroy(&scp->ipi_desc[i].lock); @@ -1357,6 +1383,21 @@ static void scp_remove(struct platform_device *pdev) mutex_destroy(&scp_cluster->cluster_lock); } =20 +static const struct mtk_scp_sizes_data default_scp_sizes =3D { + .max_dram_size =3D 0x500000, + .ipi_share_buffer_size =3D 288, +}; + +static const struct mtk_scp_sizes_data mt8188_scp_sizes =3D { + .max_dram_size =3D 0x500000, + .ipi_share_buffer_size =3D 600, +}; + +static const struct mtk_scp_sizes_data mt8188_scp_c1_sizes =3D { + .max_dram_size =3D 0xA00000, + .ipi_share_buffer_size =3D 600, +}; + static const struct mtk_scp_of_data mt8183_of_data =3D { .scp_clk_get =3D mt8183_scp_clk_get, .scp_before_load =3D mt8183_scp_before_load, @@ -1368,6 +1409,7 @@ static const struct mtk_scp_of_data mt8183_of_data = =3D { .host_to_scp_reg =3D MT8183_HOST_TO_SCP, .host_to_scp_int_bit =3D MT8183_HOST_IPC_INT_BIT, .ipi_buf_offset =3D 0x7bdb0, + .scp_sizes =3D &default_scp_sizes, }; =20 static const struct mtk_scp_of_data mt8186_of_data =3D { @@ -1381,6 +1423,7 @@ static const struct mtk_scp_of_data mt8186_of_data = =3D { .host_to_scp_reg =3D MT8183_HOST_TO_SCP, .host_to_scp_int_bit =3D MT8183_HOST_IPC_INT_BIT, .ipi_buf_offset =3D 0x3bdb0, + .scp_sizes =3D &default_scp_sizes, }; =20 static const struct mtk_scp_of_data mt8188_of_data =3D { @@ -1393,6 +1436,7 @@ static const struct mtk_scp_of_data mt8188_of_data = =3D { .scp_da_to_va =3D mt8192_scp_da_to_va, .host_to_scp_reg =3D MT8192_GIPC_IN_SET, .host_to_scp_int_bit =3D MT8192_HOST_IPC_INT_BIT, + .scp_sizes =3D &mt8188_scp_sizes, }; =20 static const struct mtk_scp_of_data mt8188_of_data_c1 =3D { @@ -1405,6 +1449,7 @@ static const struct mtk_scp_of_data mt8188_of_data_c1= =3D { .scp_da_to_va =3D mt8192_scp_da_to_va, .host_to_scp_reg =3D MT8192_GIPC_IN_SET, .host_to_scp_int_bit =3D MT8195_CORE1_HOST_IPC_INT_BIT, + .scp_sizes =3D &mt8188_scp_c1_sizes, }; =20 static const struct mtk_scp_of_data mt8192_of_data =3D { @@ -1417,6 +1462,7 @@ static const struct mtk_scp_of_data mt8192_of_data = =3D { .scp_da_to_va =3D mt8192_scp_da_to_va, .host_to_scp_reg =3D MT8192_GIPC_IN_SET, .host_to_scp_int_bit =3D MT8192_HOST_IPC_INT_BIT, + .scp_sizes =3D &default_scp_sizes, }; =20 static const struct mtk_scp_of_data mt8195_of_data =3D { @@ -1429,6 +1475,7 @@ static const struct mtk_scp_of_data mt8195_of_data = =3D { .scp_da_to_va =3D mt8192_scp_da_to_va, .host_to_scp_reg =3D MT8192_GIPC_IN_SET, .host_to_scp_int_bit =3D MT8192_HOST_IPC_INT_BIT, + .scp_sizes =3D &default_scp_sizes, }; =20 static const struct mtk_scp_of_data mt8195_of_data_c1 =3D { @@ -1441,6 +1488,7 @@ static const struct mtk_scp_of_data mt8195_of_data_c1= =3D { .scp_da_to_va =3D mt8192_scp_da_to_va, .host_to_scp_reg =3D MT8192_GIPC_IN_SET, .host_to_scp_int_bit =3D MT8195_CORE1_HOST_IPC_INT_BIT, + .scp_sizes =3D &default_scp_sizes, }; =20 static const struct mtk_scp_of_data *mt8188_of_data_cores[] =3D { diff --git a/drivers/remoteproc/mtk_scp_ipi.c b/drivers/remoteproc/mtk_scp_= ipi.c index cd0b601..c068227 100644 --- a/drivers/remoteproc/mtk_scp_ipi.c +++ b/drivers/remoteproc/mtk_scp_ipi.c @@ -162,10 +162,13 @@ int scp_ipi_send(struct mtk_scp *scp, u32 id, void *b= uf, unsigned int len, struct mtk_share_obj __iomem *send_obj =3D scp->send_buf; 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charset="utf-8" Integrate the imgsys core architecture driver for image processing on the MT8188 platform. Signed-off-by: Olivia Wen Reviewed-by: AngeloGioacchino Del Regno --- include/linux/remoteproc/mtk_scp.h | 1 + 1 file changed, 1 insertion(+) diff --git a/include/linux/remoteproc/mtk_scp.h b/include/linux/remoteproc/= mtk_scp.h index 7c2b7cc9..344ff41 100644 --- a/include/linux/remoteproc/mtk_scp.h +++ b/include/linux/remoteproc/mtk_scp.h @@ -43,6 +43,7 @@ enum scp_ipi_id { SCP_IPI_CROS_HOST_CMD, SCP_IPI_VDEC_LAT, SCP_IPI_VDEC_CORE, + SCP_IPI_IMGSYS_CMD, SCP_IPI_NS_SERVICE =3D 0xFF, SCP_IPI_MAX =3D 0x100, }; --=20 2.6.4