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charset="utf-8" The IVO t109nw41 is a 11.0" WUXGA TFT LCD panel, use hx83102 controller which fits in nicely with the existing panel-himax-hx83102 driver. Hence, we add a new compatible with panel specific config. Signed-off-by: Cong Yang --- Chage since V3: - inital cmds use lowercasehex. V2: https://lore.kernel.org/all/20240422090310.3311429-8-yangcong5@huaqin.c= orp-partner.google.com --- drivers/gpu/drm/panel/panel-himax-hx83102.c | 172 ++++++++++++++++++++ 1 file changed, 172 insertions(+) diff --git a/drivers/gpu/drm/panel/panel-himax-hx83102.c b/drivers/gpu/drm/= panel/panel-himax-hx83102.c index ea433d0c86f9..96c637c7ae2c 100644 --- a/drivers/gpu/drm/panel/panel-himax-hx83102.c +++ b/drivers/gpu/drm/panel/panel-himax-hx83102.c @@ -24,6 +24,7 @@ #define HX83102_SETPOWER 0xb1 #define HX83102_SETDISP 0xb2 #define HX83102_SETCYC 0xb4 +#define HX83102_UNKNOWN6 0xb6 #define HX83102_SETEXTC 0xb9 #define HX83102_SETMIPI 0xba #define HX83102_SETVDC 0xbc @@ -392,6 +393,152 @@ static int boe_nv110wum_init_cmd(struct hx83102 *ctx) return 0; }; =20 +static int ivo_t109nw41_init_cmd(struct hx83102 *ctx) +{ + struct mipi_dsi_device *dsi =3D ctx->dsi; + + msleep(60); + + mipi_dsi_dcs_write_seq(dsi, HX83102_SETEXTC, 0x83, 0x10, 0x21, 0x55, 0x00= ); + + mipi_dsi_dcs_write_seq(dsi, HX83102_SETPOWER, 0x2c, 0xed, 0xed, 0x27, 0xe= 7, 0x42, 0xf5, 0x39, + 0x36, 0x36, 0x36, 0x36, 0x32, 0x8b, 0x11, 0x65, 0x00, 0x88, 0xfa, = 0xff, + 0xff, 0x8f, 0xff, 0x08, 0xd6, 0x33); + + mipi_dsi_dcs_write_seq(dsi, HX83102_SETDISP, 0x00, 0x47, 0xb0, 0x80, 0x00= , 0x12, 0x71, 0x3c, + 0xa3, 0x22, 0x20, 0x00, 0x00, 0x88, 0x01); + + mipi_dsi_dcs_write_seq(dsi, HX83102_SETCYC, 0x35, 0x35, 0x43, 0x43, 0x35,= 0x35, 0x30, 0x7a, + 0x30, 0x7a, 0x01, 0x9d); + + mipi_dsi_dcs_write_seq(dsi, HX83102_UNKNOWN6, 0x34, 0x34, 0x03); + + mipi_dsi_dcs_write_seq(dsi, HX83102_SETSPCCMD, 0xcd); + + mipi_dsi_dcs_write_seq(dsi, HX83102_SETMIPI, 0x84); + + mipi_dsi_dcs_write_seq(dsi, HX83102_SETSPCCMD, 0x3f); + + mipi_dsi_dcs_write_seq(dsi, HX83102_SETVDC, 0x1b, 0x04); + + mipi_dsi_dcs_write_seq(dsi, HX83102_UNKNOWN1, 0x20); + + mipi_dsi_dcs_write_seq(dsi, HX83102_SETPTBA, 0xfc, 0xc4); + + mipi_dsi_dcs_write_seq(dsi, HX83102_SETSTBA, 0x34, 0x34, 0x22, 0x11, 0x22= , 0xa0, 0x31, 0x08, + 0xf5, 0x03); + + mipi_dsi_dcs_write_seq(dsi, HX83102_SETSPCCMD, 0xcc); + + mipi_dsi_dcs_write_seq(dsi, HX83102_SETTCON, 0x80); + + mipi_dsi_dcs_write_seq(dsi, HX83102_SETSPCCMD, 0x3f); + + mipi_dsi_dcs_write_seq(dsi, HX83102_SETSPCCMD, 0xc6); + + mipi_dsi_dcs_write_seq(dsi, HX83102_SETRAMDMY, 0x97); + + mipi_dsi_dcs_write_seq(dsi, HX83102_SETSPCCMD, 0x3f); + + mipi_dsi_dcs_write_seq(dsi, HX83102_SETPWM, 0x00, 0x1e, 0x13, 0x88, 0x01); + + mipi_dsi_dcs_write_seq(dsi, HX83102_SETCLOCK, 0x08, 0x13, 0x07, 0x00, 0x0= f, 0x34); + + mipi_dsi_dcs_write_seq(dsi, HX83102_SETPANEL, 0x02, 0x03, 0x44); + + mipi_dsi_dcs_write_seq(dsi, HX83102_SETSPCCMD, 0xc4); + + mipi_dsi_dcs_write_seq(dsi, HX83102_SETCASCADE, 0x03); + + mipi_dsi_dcs_write_seq(dsi, HX83102_SETSPCCMD, 0x3f); + + mipi_dsi_dcs_write_seq(dsi, HX83102_SETPCTRL, 0x07, 0x06, 0x00, 0x02, 0x0= 4, 0x2c, 0xff); + + mipi_dsi_dcs_write_seq(dsi, HX83102_SETGIP0, 0x06, 0x00, 0x00, 0x00, 0x00= , 0x08, 0x08, 0x08, + 0x08, 0x37, 0x07, 0x64, 0x7c, 0x11, 0x11, 0x03, 0x03, 0x32, 0x10, = 0x0e, + 0x00, 0x0e, 0x32, 0x17, 0x97, 0x07, 0x97, 0x32, 0x00, 0x02, 0x00, = 0x02, + 0x00, 0x00); + + mipi_dsi_dcs_write_seq(dsi, HX83102_SETGIP1, 0x25, 0x24, 0x25, 0x24, 0x18= , 0x18, 0x18, 0x18, + 0x07, 0x06, 0x07, 0x06, 0x05, 0x04, 0x05, 0x04, 0x03, 0x02, 0x03, = 0x02, + 0x01, 0x00, 0x01, 0x00, 0xa8, 0xa8, 0xa8, 0xa8, 0x29, 0x29, 0x29, = 0x29, + 0x21, 0x20, 0x21, 0x20, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, = 0x18); + + mipi_dsi_dcs_write_seq(dsi, HX83102_SETGIP3, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa= , 0xa0, 0xaa, 0xaa, + 0xaa, 0xaa, 0xaa, 0xa0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, = 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, = 0x00, + 0x00, 0x00, 0x00, 0x00); + + mipi_dsi_dcs_write_seq(dsi, HX83102_SETTP1, 0x07, 0x10, 0x10, 0x1a, 0x26,= 0x9e, 0x00, 0x4f, + 0xa0, 0x14, 0x14, 0x00, 0x00, 0x00, 0x00, 0x12, 0x0a, 0x02, 0x02, = 0x00, + 0x33, 0x02, 0x04, 0x18, 0x01); + + mipi_dsi_dcs_write_seq(dsi, HX83102_SETBANK, 0x01); + + mipi_dsi_dcs_write_seq(dsi, HX83102_SETPOWER, 0x01, 0x7f, 0x11, 0xfd); + + mipi_dsi_dcs_write_seq(dsi, HX83102_SETCLOCK, 0x86); + + mipi_dsi_dcs_write_seq(dsi, HX83102_SETGIP3, 0x00, 0x00, 0x00, 0x00, 0x00= , 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xa0, 0xaa, = 0xaa, + 0xaa, 0xaa, 0xaa, 0xa0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, = 0x00, + 0x00, 0x00, 0x00, 0x00); + + mipi_dsi_dcs_write_seq(dsi, HX83102_SETTP1, 0x02, 0x00, 0x2b, 0x01, 0x7e,= 0x0f, 0x7e, 0x10, + 0xa0, 0x00, 0x00, 0x77, 0x00, 0x00, 0x00); + + mipi_dsi_dcs_write_seq(dsi, HX83102_SETBANK, 0x02); + + mipi_dsi_dcs_write_seq(dsi, HX83102_SETPTBA, 0xf2); + + mipi_dsi_dcs_write_seq(dsi, HX83102_SETCLOCK, 0x03, 0x07, 0x00, 0x10, 0x7= 9); + + mipi_dsi_dcs_write_seq(dsi, HX83102_SETGIP3, 0xff, 0xff, 0xff, 0xff, 0xfa= , 0xa0, + 0xff, 0xff, 0xff, 0xff, 0xfa, 0xa0); + + mipi_dsi_dcs_write_seq(dsi, HX83102_SETTP1, 0xfe, 0x01, 0xfe, 0x01, 0xfe,= 0x01, 0x00, 0x00, + 0x00, 0x23, 0x00, 0x23, 0x81, 0x02, 0x40, 0x00, 0x20, 0x6e, 0x02, = 0x01, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00); + + mipi_dsi_dcs_write_seq(dsi, HX83102_SETBANK, 0x03); + + mipi_dsi_dcs_write_seq(dsi, HX83102_SETSPCCMD, 0xaa, 0xaa, 0xaa, 0xaa, 0x= aa, 0xa0, 0xaa, 0xaa, + 0xaa, 0xaa, 0xaa, 0xa0, 0xff, 0xff, 0xff, 0xff, 0xfa, 0xa0, 0xff, = 0xff, + 0xff, 0xff, 0xfa, 0xa0, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xa0, 0xaa, = 0xaa, + 0xaa, 0xaa, 0xaa, 0xa0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, = 0x00, + 0x00, 0x00, 0x00, 0x00); + + mipi_dsi_dcs_write_seq(dsi, HX83102_SETSPCCMD, 0xc6); + + mipi_dsi_dcs_write_seq(dsi, HX83102_SETCYC, 0x03, 0xff, 0xf8); + + mipi_dsi_dcs_write_seq(dsi, HX83102_SETSPCCMD, 0x3f); + + mipi_dsi_dcs_write_seq(dsi, HX83102_UNKNOWN5, 0x00); + + mipi_dsi_dcs_write_seq(dsi, HX83102_SETBANK, 0x00); + + mipi_dsi_dcs_write_seq(dsi, HX83102_SETSPCCMD, 0xc4); + + mipi_dsi_dcs_write_seq(dsi, HX83102_SETMIPI, 0x96); + + mipi_dsi_dcs_write_seq(dsi, HX83102_SETSPCCMD, 0x3f); + + mipi_dsi_dcs_write_seq(dsi, HX83102_SETBANK, 0x01); + + mipi_dsi_dcs_write_seq(dsi, HX83102_SETSPCCMD, 0xc5); + + mipi_dsi_dcs_write_seq(dsi, HX83102_SETMIPI, 0x4f); + + mipi_dsi_dcs_write_seq(dsi, HX83102_SETSPCCMD, 0x3f); + + mipi_dsi_dcs_write_seq(dsi, HX83102_SETBANK, 0x00); + + msleep(60); + + return 0; +}; + static const struct drm_display_mode starry_mode =3D { .clock =3D 162680, .hdisplay =3D 1200, @@ -436,6 +583,28 @@ static const struct hx83102_panel_desc boe_nv110wum_de= sc =3D { .init_cmds =3D boe_nv110wum_init_cmd, }; =20 +static const struct drm_display_mode ivo_t109nw41_default_mode =3D { + .clock =3D 166400, + .hdisplay =3D 1200, + .hsync_start =3D 1200 + 75, + .hsync_end =3D 1200 + 75 + 20, + .htotal =3D 1200 + 75 + 20 + 55, + .vdisplay =3D 1920, + .vsync_start =3D 1920 + 115, + .vsync_end =3D 1920 + 115 + 8, + .vtotal =3D 1920 + 115 + 8 + 12, + .type =3D DRM_MODE_TYPE_DRIVER | DRM_MODE_TYPE_PREFERRED, +}; + +static const struct hx83102_panel_desc ivo_t109nw41_desc =3D { + .modes =3D &ivo_t109nw41_default_mode, + .size =3D { + .width_mm =3D 147, + .height_mm =3D 235, + }, + .init_cmds =3D ivo_t109nw41_init_cmd, +}; + static int hx83102_enable(struct drm_panel *panel) { struct hx83102 *ctx =3D panel_to_hx83102(panel); @@ -695,6 +864,9 @@ static const struct of_device_id hx83102_of_match[] =3D= { { .compatible =3D "boe,nv110wum-l60", .data =3D &boe_nv110wum_desc }, + { .compatible =3D "ivo,t109nw41", + .data =3D &ivo_t109nw41_desc + }, { .compatible =3D "starry,himax83102-j02", .data =3D &starry_desc }, --=20 2.25.1