From nobody Tue Feb 10 01:36:04 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 76C161EB35; Wed, 24 Apr 2024 18:42:37 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1713984157; cv=none; b=uQri0APMYsa5B+Xw822ka1Og+cqRRwIwo5NqD+EtHFCrpCPNZ0tSSclTHDisIDKOfiX773pL81uhQtj9Ns8gDo1lGFqPazg6IoFGqLkpM34MorhIM21UpIJB8zikF3MRax6k0fS+YHW1JO/hztBm55+ynv+bIkxl2eZQN5yeJaM= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1713984157; c=relaxed/simple; bh=bLiUe4moyKKH90U2xoSensh+q7h45gvLvLdZm1uIZvQ=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=bAVFrpw0oaqcTlMGKtZJ8lgInOPpnBCqiZ0bfqJAbVjK8zu+rPTsgVbAyHZaReoAQw+X9PPrMeCb/HFoSYDEHf1ycJYNnq4BdJBz3rR0Xgz6l2lM5JCLVVMaYvghhqEyCm8xPew972X+VLVjQoY6zVNh1lIuwWcxOCyf2BsF2C4= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=G1p+EUKh; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="G1p+EUKh" Received: by smtp.kernel.org (Postfix) with ESMTPS id ECE57C4AF08; Wed, 24 Apr 2024 18:42:36 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1713984157; bh=bLiUe4moyKKH90U2xoSensh+q7h45gvLvLdZm1uIZvQ=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=G1p+EUKhCf9NsW20OQf+bY3DOTplhr0cOL90oZC9i4eYzowIXXZ/5z2yYfjcR+hxz lvmQ/kP+aUJ2fpNhAMCe+teFV5q88ZMmJ7yQyl37QvCElARyuloeT40PKHfuwG/1dA AAgOzc/iy+ff8oyEhbGLbVu5wvPbOwecX/PrdzRhpMUXPoJzypGZR5h7JeCS4Iy3pC IcE6Njs466J3YWJfchupodCcOSHzlBlKe+sGBs9GxengrtvYPxZT0NAkd6cxUpdc2i vJtooCziZs2ZrLtlg1eG7PGw1NYWqbgxyeQKw5ZZtMsJoJyPmLqxQFNXI3fUIIKS95 6F2Nrdnf67UlQ== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id E0368C19F53; Wed, 24 Apr 2024 18:42:36 +0000 (UTC) From: =?utf-8?q?Duje_Mihanovi=C4=87_via_B4_Relay?= Date: Wed, 24 Apr 2024 20:42:34 +0200 Subject: [PATCH v10 07/12] clk: mmp: Add Marvell PXA1908 APMU driver Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20240424-pxa1908-lkml-v10-7-36cdfb5841f9@skole.hr> References: <20240424-pxa1908-lkml-v10-0-36cdfb5841f9@skole.hr> In-Reply-To: <20240424-pxa1908-lkml-v10-0-36cdfb5841f9@skole.hr> To: Michael Turquette , Stephen Boyd , Linus Walleij , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Tony Lindgren , Haojian Zhuang , =?utf-8?q?Duje_Mihanovi=C4=87?= , Lubomir Rintel , Catalin Marinas , Will Deacon , Kees Cook , Tony Luck , "Guilherme G. Piccoli" , Rob Herring Cc: phone-devel@vger.kernel.org, ~postmarketos/upstreaming@lists.sr.ht, Karel Balej , David Wronek , linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org X-Mailer: b4 0.13.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=5652; i=duje.mihanovic@skole.hr; h=from:subject:message-id; bh=6r805AprFAq1fRtT/s2vqVEnpV7Fc3os3sHotGUGCl4=; b=owEBbQKS/ZANAwAIAZoRnrBCLZbhAcsmYgBmKVKUV+GFOl79hRJMr5zw/RTJtR7MevJtOKL0l BADXweTiVuJAjMEAAEIAB0WIQRT351NnD/hEPs2LXiaEZ6wQi2W4QUCZilSlAAKCRCaEZ6wQi2W 4Sx6D/9Dwqguv8jLw03kuO7r+5wRBb18/Mu2gcxrJoZywiuNpMwyNVZos6EEluQxi1RUP312URx ZEGAZLBlDS6S1G146rZBNM1yCUHbcs+B42Hdrf0FGkoiHFlVOM9YwZDhPnFPBHZ+fiq7C/1gIeH 8nG0AFHen5x3RjmSD2VC2D5Ot5AQHXx24xfACg5r1z4uhmuFOanoj1LdaPJ+6+p++ENXfCXlCA0 EBFOjqOULhGJ8GExi02Jnp80W7nyXyA/S6US/CTYw2XwgbJ2mNnHvCQze3cvrEDqc21rbQKP2V4 40uTZVP1LUWR6oy0D9CX76GG0paqjjxZCJGboKsrcUiYXbxYJMWN8V/lw7pI6VKfiZ5av77fLNL klKEkLzMxvj+vob6wVtS5mWdNkmeKdQGVnCCoK88HbhOoyyN+cLH4xRjU3Pb5wHttRI/xgD0b7N n/auKhX7vgxrTKNH2TWjby/SyUwTWMLzyKsM7gK89jjHjWV4lOBX5jzq3uGtN4FdAREeeA0CyGR JqKwWOkSr9jMfvN0UWhAbBc+YdTUz3mpzjh+6wp6lR3BItM7lbbEmu3U8OtLfgeM1TX6n4XAuvJ CarcD+BQ3CRbUQFhTRMK09X1VOH4Fennb7OsE44BxVvXvdWWls8r8f6D3g+gI6utvaEQjo39Mso 8TYhzi8zJOzxxtw== X-Developer-Key: i=duje.mihanovic@skole.hr; a=openpgp; fpr=53DF9D4D9C3FE110FB362D789A119EB0422D96E1 X-Endpoint-Received: by B4 Relay for duje.mihanovic@skole.hr/default with auth_id=112 X-Original-From: =?utf-8?q?Duje_Mihanovi=C4=87?= Reply-To: duje.mihanovic@skole.hr From: Duje Mihanovi=C4=87 Add driver for the APMU controller block found on Marvell's PXA1908 SoC. This driver is incomplete, lacking support for (at least) GPU, VPU, DSI and CCIC (camera related) clocks. Signed-off-by: Duje Mihanovi=C4=87 --- drivers/clk/mmp/Makefile | 2 +- drivers/clk/mmp/clk-pxa1908-apmu.c | 123 +++++++++++++++++++++++++++++++++= ++++ 2 files changed, 124 insertions(+), 1 deletion(-) diff --git a/drivers/clk/mmp/Makefile b/drivers/clk/mmp/Makefile index 038bcd4d035e..a8b1a4b08824 100644 --- a/drivers/clk/mmp/Makefile +++ b/drivers/clk/mmp/Makefile @@ -11,4 +11,4 @@ obj-$(CONFIG_MACH_MMP_DT) +=3D clk-of-pxa168.o clk-of-pxa= 910.o obj-$(CONFIG_COMMON_CLK_MMP2) +=3D clk-of-mmp2.o clk-pll.o pwr-island.o obj-$(CONFIG_COMMON_CLK_MMP2_AUDIO) +=3D clk-audio.o =20 -obj-$(CONFIG_ARCH_MMP) +=3D clk-of-pxa1928.o clk-pxa1908-apbc.o clk-pxa190= 8-apbcp.o +obj-$(CONFIG_ARCH_MMP) +=3D clk-of-pxa1928.o clk-pxa1908-apbc.o clk-pxa190= 8-apbcp.o clk-pxa1908-apmu.o diff --git a/drivers/clk/mmp/clk-pxa1908-apmu.c b/drivers/clk/mmp/clk-pxa19= 08-apmu.c new file mode 100644 index 000000000000..693254539063 --- /dev/null +++ b/drivers/clk/mmp/clk-pxa1908-apmu.c @@ -0,0 +1,123 @@ +// SPDX-License-Identifier: GPL-2.0-only +#include +#include +#include +#include +#include +#include + +#include + +#include "clk.h" + +#define APMU_CLK_GATE_CTRL 0x40 +#define APMU_CCIC1 0x24 +#define APMU_ISP 0x38 +#define APMU_DSI1 0x44 +#define APMU_DISP1 0x4c +#define APMU_CCIC0 0x50 +#define APMU_SDH0 0x54 +#define APMU_SDH1 0x58 +#define APMU_USB 0x5c +#define APMU_NF 0x60 +#define APMU_VPU 0xa4 +#define APMU_GC 0xcc +#define APMU_SDH2 0xe0 +#define APMU_GC2D 0xf4 +#define APMU_TRACE 0x108 +#define APMU_DVC_DFC_DEBUG 0x140 + +#define APMU_NR_CLKS 17 + +struct pxa1908_clk_unit { + struct mmp_clk_unit unit; + void __iomem *base; +}; + +static DEFINE_SPINLOCK(pll1_lock); +static struct mmp_param_general_gate_clk pll1_gate_clks[] =3D { + {PXA1908_CLK_PLL1_D2_GATE, "pll1_d2_gate", "pll1_d2", 0, APMU_CLK_GATE_CT= RL, 29, 0, &pll1_lock}, + {PXA1908_CLK_PLL1_416_GATE, "pll1_416_gate", "pll1_416", 0, APMU_CLK_GATE= _CTRL, 27, 0, &pll1_lock}, + {PXA1908_CLK_PLL1_624_GATE, "pll1_624_gate", "pll1_624", 0, APMU_CLK_GATE= _CTRL, 26, 0, &pll1_lock}, + {PXA1908_CLK_PLL1_832_GATE, "pll1_832_gate", "pll1_832", 0, APMU_CLK_GATE= _CTRL, 30, 0, &pll1_lock}, + {PXA1908_CLK_PLL1_1248_GATE, "pll1_1248_gate", "pll1_1248", 0, APMU_CLK_G= ATE_CTRL, 28, 0, &pll1_lock}, +}; + +static DEFINE_SPINLOCK(sdh0_lock); +static DEFINE_SPINLOCK(sdh1_lock); +static DEFINE_SPINLOCK(sdh2_lock); + +static const char * const sdh_parent_names[] =3D {"pll1_416", "pll1_624"}; + +static struct mmp_clk_mix_config sdh_mix_config =3D { + .reg_info =3D DEFINE_MIX_REG_INFO(3, 8, 2, 6, 11), +}; + +static struct mmp_param_gate_clk apmu_gate_clks[] =3D { + {PXA1908_CLK_USB, "usb_clk", NULL, 0, APMU_USB, 0x9, 0x9, 0x1, 0, NULL}, + {PXA1908_CLK_SDH0, "sdh0_clk", "sdh0_mix_clk", CLK_SET_RATE_PARENT | CLK_= SET_RATE_UNGATE, APMU_SDH0, 0x12, 0x12, 0x0, 0, &sdh0_lock}, + {PXA1908_CLK_SDH1, "sdh1_clk", "sdh1_mix_clk", CLK_SET_RATE_PARENT | CLK_= SET_RATE_UNGATE, APMU_SDH1, 0x12, 0x12, 0x0, 0, &sdh1_lock}, + {PXA1908_CLK_SDH2, "sdh2_clk", "sdh2_mix_clk", CLK_SET_RATE_PARENT | CLK_= SET_RATE_UNGATE, APMU_SDH2, 0x12, 0x12, 0x0, 0, &sdh2_lock} +}; + +static void pxa1908_axi_periph_clk_init(struct pxa1908_clk_unit *pxa_unit) +{ + struct mmp_clk_unit *unit =3D &pxa_unit->unit; + + mmp_register_general_gate_clks(unit, pll1_gate_clks, + pxa_unit->base, ARRAY_SIZE(pll1_gate_clks)); + + sdh_mix_config.reg_info.reg_clk_ctrl =3D pxa_unit->base + APMU_SDH0; + mmp_clk_register_mix(NULL, "sdh0_mix_clk", sdh_parent_names, + ARRAY_SIZE(sdh_parent_names), CLK_SET_RATE_PARENT, + &sdh_mix_config, &sdh0_lock); + sdh_mix_config.reg_info.reg_clk_ctrl =3D pxa_unit->base + APMU_SDH1; + mmp_clk_register_mix(NULL, "sdh1_mix_clk", sdh_parent_names, + ARRAY_SIZE(sdh_parent_names), CLK_SET_RATE_PARENT, + &sdh_mix_config, &sdh1_lock); + sdh_mix_config.reg_info.reg_clk_ctrl =3D pxa_unit->base + APMU_SDH2; + mmp_clk_register_mix(NULL, "sdh2_mix_clk", sdh_parent_names, + ARRAY_SIZE(sdh_parent_names), CLK_SET_RATE_PARENT, + &sdh_mix_config, &sdh2_lock); + + mmp_register_gate_clks(unit, apmu_gate_clks, pxa_unit->base, + ARRAY_SIZE(apmu_gate_clks)); +} + +static int pxa1908_apmu_probe(struct platform_device *pdev) +{ + struct pxa1908_clk_unit *pxa_unit; + + pxa_unit =3D devm_kzalloc(&pdev->dev, sizeof(*pxa_unit), GFP_KERNEL); + if (IS_ERR(pxa_unit)) + return PTR_ERR(pxa_unit); + + pxa_unit->base =3D devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(pxa_unit->base)) + return PTR_ERR(pxa_unit->base); + + mmp_clk_init(pdev->dev.of_node, &pxa_unit->unit, APMU_NR_CLKS); + + pxa1908_axi_periph_clk_init(pxa_unit); + + return 0; +} + +static const struct of_device_id pxa1908_apmu_match_table[] =3D { + { .compatible =3D "marvell,pxa1908-apmu" }, + { } +}; +MODULE_DEVICE_TABLE(of, pxa1908_apmu_match_table); + +static struct platform_driver pxa1908_apmu_driver =3D { + .probe =3D pxa1908_apmu_probe, + .driver =3D { + .name =3D "pxa1908-apmu", + .of_match_table =3D pxa1908_apmu_match_table + } +}; +module_platform_driver(pxa1908_apmu_driver); + +MODULE_AUTHOR("Duje Mihanovi=C4=87 "); +MODULE_DESCRIPTION("Marvell PXA1908 APMU Clock Driver"); +MODULE_LICENSE("GPL"); --=20 2.44.0