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charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20240424-dispcc-dp-clocks-v2-2-b44038f3fa96@linaro.org> References: <20240424-dispcc-dp-clocks-v2-0-b44038f3fa96@linaro.org> In-Reply-To: <20240424-dispcc-dp-clocks-v2-0-b44038f3fa96@linaro.org> To: Bjorn Andersson , Michael Turquette , Stephen Boyd , Konrad Dybcio , Konrad Dybcio , Neil Armstrong Cc: linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, Luca Weiss X-Mailer: b4 0.13.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=1973; i=dmitry.baryshkov@linaro.org; h=from:subject:message-id; bh=mmpz/wbHDRDW8GXi4f/Kh4tJEWD2H5kJEpj0vD29QCA=; b=owEBbQGS/pANAwAKAYs8ij4CKSjVAcsmYgBmKGLRxO41CkbrfP/anarHJu9uaguFaqMi0IZTA PU2km/d/seJATMEAAEKAB0WIQRMcISVXLJjVvC4lX+LPIo+Aiko1QUCZihi0QAKCRCLPIo+Aiko 1aVdB/96X0iiZjshy2kzTustfxyKgqGNazxxs9Q/tAO5uZOnN/lXtDx+GoVk4LCnLmzrB42z9DE prWUP6PlrjinsLM7xgBd0iVjYPD7p+olHm+n3pXcfY3TYryrDl0s2cLTqKFdRGYT3ACXp1kNUU/ 8QvcmdJGiIGm15pYUnxdw+thJWztkbNz66QnL5EWmFQUEfA9av5PUE0W+hN8j8RUfqP/rSD5bUE iV4fWhYHbRKMaFiLf83FX5IVSGoHcA9b6sdxndsK3tr7dekdUGcoAyj7Zmr7ap/lAtUciZEuAhU NK/sHPL1Srqgm6jnyCYHEMH6chokj+O0Ue8+17KP53xP6wsj X-Developer-Key: i=dmitry.baryshkov@linaro.org; a=openpgp; fpr=8F88381DD5C873E4AE487DA5199BF1243632046A On SM6350 DisplayPort link clocks use frequency tables inherited from the vendor kernel, it is not applicable in the upstream kernel. Drop frequency tables and use clk_byte2_ops for those clocks. This fixes frequency selection in the OPP core (which otherwise attempts to use invalid 810 KHz as DP link rate), also fixing the following message: msm-dp-display ae90000.displayport-controller: _opp_config_clk_single: fail= ed to set clock rate: -22 Fixes: 837519775f1d ("clk: qcom: Add display clock controller driver for SM= 6350") Reviewed-by: Neil Armstrong Tested-by: Luca Weiss Reviewed-by: Konrad Dybcio Signed-off-by: Dmitry Baryshkov --- drivers/clk/qcom/dispcc-sm6350.c | 11 +---------- 1 file changed, 1 insertion(+), 10 deletions(-) diff --git a/drivers/clk/qcom/dispcc-sm6350.c b/drivers/clk/qcom/dispcc-sm6= 350.c index 839435362010..e4b7464c4d0e 100644 --- a/drivers/clk/qcom/dispcc-sm6350.c +++ b/drivers/clk/qcom/dispcc-sm6350.c @@ -221,26 +221,17 @@ static struct clk_rcg2 disp_cc_mdss_dp_crypto_clk_src= =3D { }, }; =20 -static const struct freq_tbl ftbl_disp_cc_mdss_dp_link_clk_src[] =3D { - F(162000, P_DP_PHY_PLL_LINK_CLK, 1, 0, 0), - F(270000, P_DP_PHY_PLL_LINK_CLK, 1, 0, 0), - F(540000, P_DP_PHY_PLL_LINK_CLK, 1, 0, 0), - F(810000, P_DP_PHY_PLL_LINK_CLK, 1, 0, 0), - { } -}; - static struct clk_rcg2 disp_cc_mdss_dp_link_clk_src =3D { .cmd_rcgr =3D 0x10f8, .mnd_width =3D 0, .hid_width =3D 5, .parent_map =3D disp_cc_parent_map_0, - .freq_tbl =3D ftbl_disp_cc_mdss_dp_link_clk_src, .clkr.hw.init =3D &(struct clk_init_data){ .name =3D "disp_cc_mdss_dp_link_clk_src", .parent_data =3D disp_cc_parent_data_0, .num_parents =3D ARRAY_SIZE(disp_cc_parent_data_0), .flags =3D CLK_SET_RATE_PARENT | CLK_GET_RATE_NOCACHE, - .ops =3D &clk_rcg2_ops, + .ops =3D &clk_byte2_ops, }, }; =20 --=20 2.39.2