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charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20240424-dispcc-dp-clocks-v2-1-b44038f3fa96@linaro.org> References: <20240424-dispcc-dp-clocks-v2-0-b44038f3fa96@linaro.org> In-Reply-To: <20240424-dispcc-dp-clocks-v2-0-b44038f3fa96@linaro.org> To: Bjorn Andersson , Michael Turquette , Stephen Boyd , Konrad Dybcio , Konrad Dybcio , Neil Armstrong Cc: linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org X-Mailer: b4 0.13.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=3434; i=dmitry.baryshkov@linaro.org; h=from:subject:message-id; bh=1TNV+A/4m11S1W9ZXAXoZL1N6Y2XAKcktMUgBdQ0cZU=; b=owEBbQGS/pANAwAKAYs8ij4CKSjVAcsmYgBmKGLR1RppQVh11o6eHfRn4+pGpEJL2EBItT12m E743opng3iJATMEAAEKAB0WIQRMcISVXLJjVvC4lX+LPIo+Aiko1QUCZihi0QAKCRCLPIo+Aiko 1ZgmCACnupbT6UvuvpjZfG+ihUUa7OqyePSSQ/fKiiYfTvwYTFDztFxlnBIQOcxB2BThNbxs3vN LKFDpx1U/x1OKzGCKyhJZCdZ8t9u61z3VIzmpk6pGiv/OTY84PEzI2DvFmjHG3imD3ib2Bz3MGs hA///9L+BYj7udt3gc8aMRTfJE0JjTSkjiGB9CFV9teQQTCixHkuMOb4D4s+n1c6t3TOZ2H/ZkM QrPIImvd7HgKbSiNJl6pKEr8yJ4X09d64ABEitRCZWvCKOtWUKdQktmB4zDjT6I+1438hjhzT1i RitpADWgEm8OJhjkD99y85L/ri/YcaDg3xYsQNwzUIRiUARB X-Developer-Key: i=dmitry.baryshkov@linaro.org; a=openpgp; fpr=8F88381DD5C873E4AE487DA5199BF1243632046A On SM8450 DisplayPort link clocks use frequency tables inherited from the vendor kernel, it is not applicable in the upstream kernel. Drop frequency tables and use clk_byte2_ops for those clocks. This fixes frequency selection in the OPP core (which otherwise attempts to use invalid 810 KHz as DP link rate), also fixing the following message: msm-dp-display ae90000.displayport-controller: _opp_config_clk_single: fail= ed to set clock rate: -22 Fixes: 16fb89f92ec4 ("clk: qcom: Add support for Display Clock Controller o= n SM8450") Reviewed-by: Neil Armstrong Reviewed-by: Konrad Dybcio Signed-off-by: Dmitry Baryshkov --- drivers/clk/qcom/dispcc-sm8450.c | 20 ++++---------------- 1 file changed, 4 insertions(+), 16 deletions(-) diff --git a/drivers/clk/qcom/dispcc-sm8450.c b/drivers/clk/qcom/dispcc-sm8= 450.c index 92e9c4e7b13d..49bb4f58c391 100644 --- a/drivers/clk/qcom/dispcc-sm8450.c +++ b/drivers/clk/qcom/dispcc-sm8450.c @@ -309,26 +309,17 @@ static struct clk_rcg2 disp_cc_mdss_dptx0_aux_clk_src= =3D { }, }; =20 -static const struct freq_tbl ftbl_disp_cc_mdss_dptx0_link_clk_src[] =3D { - F(162000, P_DP0_PHY_PLL_LINK_CLK, 1, 0, 0), - F(270000, P_DP0_PHY_PLL_LINK_CLK, 1, 0, 0), - F(540000, P_DP0_PHY_PLL_LINK_CLK, 1, 0, 0), - F(810000, P_DP0_PHY_PLL_LINK_CLK, 1, 0, 0), - { } -}; - static struct clk_rcg2 disp_cc_mdss_dptx0_link_clk_src =3D { .cmd_rcgr =3D 0x819c, .mnd_width =3D 0, .hid_width =3D 5, .parent_map =3D disp_cc_parent_map_3, - .freq_tbl =3D ftbl_disp_cc_mdss_dptx0_link_clk_src, .clkr.hw.init =3D &(struct clk_init_data) { .name =3D "disp_cc_mdss_dptx0_link_clk_src", .parent_data =3D disp_cc_parent_data_3, .num_parents =3D ARRAY_SIZE(disp_cc_parent_data_3), .flags =3D CLK_SET_RATE_PARENT, - .ops =3D &clk_rcg2_ops, + .ops =3D &clk_byte2_ops, }, }; =20 @@ -382,13 +373,12 @@ static struct clk_rcg2 disp_cc_mdss_dptx1_link_clk_sr= c =3D { .mnd_width =3D 0, .hid_width =3D 5, .parent_map =3D disp_cc_parent_map_3, - .freq_tbl =3D ftbl_disp_cc_mdss_dptx0_link_clk_src, .clkr.hw.init =3D &(struct clk_init_data) { .name =3D "disp_cc_mdss_dptx1_link_clk_src", .parent_data =3D disp_cc_parent_data_3, .num_parents =3D ARRAY_SIZE(disp_cc_parent_data_3), .flags =3D CLK_SET_RATE_PARENT, - .ops =3D &clk_rcg2_ops, + .ops =3D &clk_byte2_ops, }, }; =20 @@ -442,13 +432,12 @@ static struct clk_rcg2 disp_cc_mdss_dptx2_link_clk_sr= c =3D { .mnd_width =3D 0, .hid_width =3D 5, .parent_map =3D disp_cc_parent_map_3, - .freq_tbl =3D ftbl_disp_cc_mdss_dptx0_link_clk_src, .clkr.hw.init =3D &(struct clk_init_data) { .name =3D "disp_cc_mdss_dptx2_link_clk_src", .parent_data =3D disp_cc_parent_data_3, .num_parents =3D ARRAY_SIZE(disp_cc_parent_data_3), .flags =3D CLK_SET_RATE_PARENT, - .ops =3D &clk_rcg2_ops, + .ops =3D &clk_byte2_ops, }, }; =20 @@ -502,13 +491,12 @@ static struct clk_rcg2 disp_cc_mdss_dptx3_link_clk_sr= c =3D { .mnd_width =3D 0, .hid_width =3D 5, .parent_map =3D disp_cc_parent_map_3, - .freq_tbl =3D ftbl_disp_cc_mdss_dptx0_link_clk_src, .clkr.hw.init =3D &(struct clk_init_data) { .name =3D "disp_cc_mdss_dptx3_link_clk_src", .parent_data =3D disp_cc_parent_data_3, .num_parents =3D ARRAY_SIZE(disp_cc_parent_data_3), .flags =3D CLK_SET_RATE_PARENT, - .ops =3D &clk_rcg2_ops, + .ops =3D &clk_byte2_ops, }, }; =20 --=20 2.39.2 From nobody Sun Feb 8 20:28:22 2026 Received: from mail-lf1-f47.google.com (mail-lf1-f47.google.com [209.85.167.47]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 0CEC8BE4F for ; Wed, 24 Apr 2024 01:39:33 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.167.47 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1713922776; 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Tue, 23 Apr 2024 18:39:32 -0700 (PDT) Received: from umbar.lan ([192.130.178.91]) by smtp.gmail.com with ESMTPSA id g12-20020a19ac0c000000b0051bb40c7ee7sm308220lfc.185.2024.04.23.18.39.31 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 23 Apr 2024 18:39:31 -0700 (PDT) From: Dmitry Baryshkov Date: Wed, 24 Apr 2024 04:39:30 +0300 Subject: [PATCH v2 2/4] clk: qcom: dispcc-sm6350: fix DisplayPort clocks Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20240424-dispcc-dp-clocks-v2-2-b44038f3fa96@linaro.org> References: <20240424-dispcc-dp-clocks-v2-0-b44038f3fa96@linaro.org> In-Reply-To: <20240424-dispcc-dp-clocks-v2-0-b44038f3fa96@linaro.org> To: Bjorn Andersson , Michael Turquette , Stephen Boyd , Konrad Dybcio , Konrad Dybcio , Neil Armstrong Cc: linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, Luca Weiss X-Mailer: b4 0.13.0 X-Developer-Signature: v=1; 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Drop frequency tables and use clk_byte2_ops for those clocks. This fixes frequency selection in the OPP core (which otherwise attempts to use invalid 810 KHz as DP link rate), also fixing the following message: msm-dp-display ae90000.displayport-controller: _opp_config_clk_single: fail= ed to set clock rate: -22 Fixes: 837519775f1d ("clk: qcom: Add display clock controller driver for SM= 6350") Reviewed-by: Neil Armstrong Tested-by: Luca Weiss Reviewed-by: Konrad Dybcio Signed-off-by: Dmitry Baryshkov --- drivers/clk/qcom/dispcc-sm6350.c | 11 +---------- 1 file changed, 1 insertion(+), 10 deletions(-) diff --git a/drivers/clk/qcom/dispcc-sm6350.c b/drivers/clk/qcom/dispcc-sm6= 350.c index 839435362010..e4b7464c4d0e 100644 --- a/drivers/clk/qcom/dispcc-sm6350.c +++ b/drivers/clk/qcom/dispcc-sm6350.c @@ -221,26 +221,17 @@ static struct clk_rcg2 disp_cc_mdss_dp_crypto_clk_src= =3D { }, }; =20 -static const struct freq_tbl ftbl_disp_cc_mdss_dp_link_clk_src[] =3D { - F(162000, P_DP_PHY_PLL_LINK_CLK, 1, 0, 0), - F(270000, P_DP_PHY_PLL_LINK_CLK, 1, 0, 0), - F(540000, P_DP_PHY_PLL_LINK_CLK, 1, 0, 0), - F(810000, P_DP_PHY_PLL_LINK_CLK, 1, 0, 0), - { } -}; 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Tue, 23 Apr 2024 18:39:32 -0700 (PDT) Received: from umbar.lan ([192.130.178.91]) by smtp.gmail.com with ESMTPSA id g12-20020a19ac0c000000b0051bb40c7ee7sm308220lfc.185.2024.04.23.18.39.32 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 23 Apr 2024 18:39:32 -0700 (PDT) From: Dmitry Baryshkov Date: Wed, 24 Apr 2024 04:39:31 +0300 Subject: [PATCH v2 3/4] clk: qcom: dispcc-sm8550: fix DisplayPort clocks Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20240424-dispcc-dp-clocks-v2-3-b44038f3fa96@linaro.org> References: <20240424-dispcc-dp-clocks-v2-0-b44038f3fa96@linaro.org> In-Reply-To: <20240424-dispcc-dp-clocks-v2-0-b44038f3fa96@linaro.org> To: Bjorn Andersson , Michael Turquette , Stephen Boyd , Konrad Dybcio , Konrad Dybcio , Neil Armstrong Cc: linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org X-Mailer: b4 0.13.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=3479; i=dmitry.baryshkov@linaro.org; h=from:subject:message-id; bh=+wcSE0jQUAsuubsPo5heuUnwmIQFYUlds9F5s8pvyXk=; b=owEBbQGS/pANAwAKAYs8ij4CKSjVAcsmYgBmKGLRAV1KakRYNoWd1kjF4UdOERvn9SJVGwnvq +D2bkvZkBaJATMEAAEKAB0WIQRMcISVXLJjVvC4lX+LPIo+Aiko1QUCZihi0QAKCRCLPIo+Aiko 1eDqB/9GiAaLEiNaC0CA0LKXCOKa0vb1gQFjUGjV0J7jQic7zzkC9qm2Kf14APNhbxr78ncwJTm /PLVVLaBoXvillojCGnbGovLWdAu39k2HAl4sreiOucjHLbSkd01eZXRcN6+QH72INXBSH6k0gT IFOiPYj1a38mNooF32jqZP6BzlEiM1HEufZGY+s+ZcMgRc2fFPWnpKqBFf9VzQegcHlktH1YR8Z +s5FpX3XoE5UyvHaZ6ebA0o5FJrXnWGtE0Zo/A1BPEKky67YpnRUL+z8GXx5ypiB5jJQMADMMqF PYfmDxvz1RX3xRnLvQ1G7K29TWuMftKQR1In5Mk3l543D6/d X-Developer-Key: i=dmitry.baryshkov@linaro.org; a=openpgp; fpr=8F88381DD5C873E4AE487DA5199BF1243632046A On SM8550 DisplayPort link clocks use frequency tables inherited from the vendor kernel, it is not applicable in the upstream kernel. Drop frequency tables and use clk_byte2_ops for those clocks. This fixes frequency selection in the OPP core (which otherwise attempts to use invalid 810 KHz as DP link rate), also fixing the following message: msm-dp-display ae90000.displayport-controller: _opp_config_clk_single: fail= ed to set clock rate: -22 Fixes: 90114ca11476 ("clk: qcom: add SM8550 DISPCC driver") Reviewed-by: Neil Armstrong Tested-by: Neil Armstrong # on SM8550-HDK Reviewed-by: Konrad Dybcio Signed-off-by: Dmitry Baryshkov --- drivers/clk/qcom/dispcc-sm8550.c | 20 ++++---------------- 1 file changed, 4 insertions(+), 16 deletions(-) diff --git a/drivers/clk/qcom/dispcc-sm8550.c b/drivers/clk/qcom/dispcc-sm8= 550.c index 3672c73ac11c..38ecea805503 100644 --- a/drivers/clk/qcom/dispcc-sm8550.c +++ b/drivers/clk/qcom/dispcc-sm8550.c @@ -345,26 +345,17 @@ static struct clk_rcg2 disp_cc_mdss_dptx0_aux_clk_src= =3D { }, }; =20 -static const struct freq_tbl ftbl_disp_cc_mdss_dptx0_link_clk_src[] =3D { - F(162000, P_DP0_PHY_PLL_LINK_CLK, 1, 0, 0), - F(270000, P_DP0_PHY_PLL_LINK_CLK, 1, 0, 0), - F(540000, P_DP0_PHY_PLL_LINK_CLK, 1, 0, 0), - F(810000, P_DP0_PHY_PLL_LINK_CLK, 1, 0, 0), - { } -}; - static struct clk_rcg2 disp_cc_mdss_dptx0_link_clk_src =3D { .cmd_rcgr =3D 0x8170, .mnd_width =3D 0, .hid_width =3D 5, .parent_map =3D disp_cc_parent_map_7, - .freq_tbl =3D ftbl_disp_cc_mdss_dptx0_link_clk_src, .clkr.hw.init =3D &(struct clk_init_data) { .name =3D "disp_cc_mdss_dptx0_link_clk_src", .parent_data =3D disp_cc_parent_data_7, .num_parents =3D ARRAY_SIZE(disp_cc_parent_data_7), .flags =3D CLK_SET_RATE_PARENT, - .ops =3D &clk_rcg2_ops, + .ops =3D &clk_byte2_ops, }, }; =20 @@ -418,13 +409,12 @@ static struct clk_rcg2 disp_cc_mdss_dptx1_link_clk_sr= c =3D { .mnd_width =3D 0, .hid_width =3D 5, .parent_map =3D disp_cc_parent_map_3, - .freq_tbl =3D ftbl_disp_cc_mdss_dptx0_link_clk_src, .clkr.hw.init =3D &(struct clk_init_data) { .name =3D "disp_cc_mdss_dptx1_link_clk_src", .parent_data =3D disp_cc_parent_data_3, .num_parents =3D ARRAY_SIZE(disp_cc_parent_data_3), .flags =3D CLK_SET_RATE_PARENT, - .ops =3D &clk_rcg2_ops, + .ops =3D &clk_byte2_ops, }, }; =20 @@ -478,13 +468,12 @@ static struct clk_rcg2 disp_cc_mdss_dptx2_link_clk_sr= c =3D { .mnd_width =3D 0, .hid_width =3D 5, .parent_map =3D disp_cc_parent_map_3, - .freq_tbl =3D ftbl_disp_cc_mdss_dptx0_link_clk_src, .clkr.hw.init =3D &(struct clk_init_data) { .name =3D "disp_cc_mdss_dptx2_link_clk_src", .parent_data =3D disp_cc_parent_data_3, .num_parents =3D ARRAY_SIZE(disp_cc_parent_data_3), .flags =3D CLK_SET_RATE_PARENT, - .ops =3D &clk_rcg2_ops, + .ops =3D &clk_byte2_ops, }, }; =20 @@ -538,13 +527,12 @@ static struct clk_rcg2 disp_cc_mdss_dptx3_link_clk_sr= c =3D { .mnd_width =3D 0, .hid_width =3D 5, .parent_map =3D disp_cc_parent_map_3, - .freq_tbl =3D ftbl_disp_cc_mdss_dptx0_link_clk_src, .clkr.hw.init =3D &(struct clk_init_data) { .name =3D "disp_cc_mdss_dptx3_link_clk_src", .parent_data =3D disp_cc_parent_data_3, .num_parents =3D ARRAY_SIZE(disp_cc_parent_data_3), .flags =3D CLK_SET_RATE_PARENT, - .ops =3D &clk_rcg2_ops, + .ops =3D &clk_byte2_ops, }, }; =20 --=20 2.39.2 From nobody Sun Feb 8 20:28:22 2026 Received: from mail-lf1-f51.google.com (mail-lf1-f51.google.com [209.85.167.51]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C539B10A1A for ; Wed, 24 Apr 2024 01:39:35 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.167.51 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1713922777; 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Tue, 23 Apr 2024 18:39:33 -0700 (PDT) Received: from umbar.lan ([192.130.178.91]) by smtp.gmail.com with ESMTPSA id g12-20020a19ac0c000000b0051bb40c7ee7sm308220lfc.185.2024.04.23.18.39.33 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 23 Apr 2024 18:39:33 -0700 (PDT) From: Dmitry Baryshkov Date: Wed, 24 Apr 2024 04:39:32 +0300 Subject: [PATCH v2 4/4] clk: qcom: dispcc-sm8650: fix DisplayPort clocks Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20240424-dispcc-dp-clocks-v2-4-b44038f3fa96@linaro.org> References: <20240424-dispcc-dp-clocks-v2-0-b44038f3fa96@linaro.org> In-Reply-To: <20240424-dispcc-dp-clocks-v2-0-b44038f3fa96@linaro.org> To: Bjorn Andersson , Michael Turquette , Stephen Boyd , Konrad Dybcio , Konrad Dybcio , Neil Armstrong Cc: linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org X-Mailer: b4 0.13.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=3525; i=dmitry.baryshkov@linaro.org; h=from:subject:message-id; bh=zB/5/SiVEaWqGONs3bHHf5u8om8piOX61Ct2vWQ8uzE=; b=owGbwMvMwMXYbdNlx6SpcZXxtFoSQ5pG0iVJnYX9C7JjFph8MF1o3mPiraS88YJd9gsVG52qk K62GMdORmMWBkYuBlkxRRafgpapMZuSwz7smFoPM4iVCWQKAxenAEwkZCX7/1otyTk3mlaF3JzJ fGxyx7VjP9XqLifanj69kOGU/7vWwvrOPwm+RsU2DN2aM19X8pms3Lj8rMKCs+92+OiHKO0wqej 6PtvuqJOQptDGd10HV+ctuNmvKT7xg8ayzPKrefdl20JLGDzF4n4VyhicT//M82nZ1/U/uZXZu8 2vRtmt95+z+w/DtBsJOq9VctZ6P30hPE3jQbzkrvzo1D2HP0dbV7dMVxNJXJz24dZtc0fvvnm1G /l77azOikVMbvlfobG95dnTx4LBq336rFfZzwy9yfAuwVZtU39GZt3c6keFOTt9/QXe7ZWfWxb7 6Z6btNKXeXXl3c5LLnnGc9daiYqtju+u+9Hx8YNRc1kqAA== X-Developer-Key: i=dmitry.baryshkov@linaro.org; a=openpgp; fpr=8F88381DD5C873E4AE487DA5199BF1243632046A On SM8650 DisplayPort link clocks use frequency tables inherited from the vendor kernel, it is not applicable in the upstream kernel. Drop frequency tables and use clk_byte2_ops for those clocks. This fixes frequency selection in the OPP core (which otherwise attempts to use invalid 810 KHz as DP link rate), also fixing the following message: msm-dp-display af54000.displayport-controller: _opp_config_clk_single: fail= ed to set clock rate: -22 Fixes: 9e939f008338 ("clk: qcom: add the SM8650 Display Clock Controller dr= iver") Reviewed-by: Neil Armstrong Tested-by: Neil Armstrong # on SM8650-HDK Reviewed-by: Konrad Dybcio Signed-off-by: Dmitry Baryshkov --- drivers/clk/qcom/dispcc-sm8650.c | 20 ++++---------------- 1 file changed, 4 insertions(+), 16 deletions(-) diff --git a/drivers/clk/qcom/dispcc-sm8650.c b/drivers/clk/qcom/dispcc-sm8= 650.c index 9539db0d9114..3eb64bcad487 100644 --- a/drivers/clk/qcom/dispcc-sm8650.c +++ b/drivers/clk/qcom/dispcc-sm8650.c @@ -343,26 +343,17 @@ static struct clk_rcg2 disp_cc_mdss_dptx0_aux_clk_src= =3D { }, }; =20 -static const struct freq_tbl ftbl_disp_cc_mdss_dptx0_link_clk_src[] =3D { - F(162000, P_DP0_PHY_PLL_LINK_CLK, 1, 0, 0), - F(270000, P_DP0_PHY_PLL_LINK_CLK, 1, 0, 0), - F(540000, P_DP0_PHY_PLL_LINK_CLK, 1, 0, 0), - F(810000, P_DP0_PHY_PLL_LINK_CLK, 1, 0, 0), - { } -}; - static struct clk_rcg2 disp_cc_mdss_dptx0_link_clk_src =3D { .cmd_rcgr =3D 0x8170, .mnd_width =3D 0, .hid_width =3D 5, .parent_map =3D disp_cc_parent_map_7, - .freq_tbl =3D ftbl_disp_cc_mdss_dptx0_link_clk_src, .clkr.hw.init =3D &(const struct clk_init_data) { .name =3D "disp_cc_mdss_dptx0_link_clk_src", .parent_data =3D disp_cc_parent_data_7, .num_parents =3D ARRAY_SIZE(disp_cc_parent_data_7), .flags =3D CLK_SET_RATE_PARENT, - .ops =3D &clk_rcg2_ops, + .ops =3D &clk_byte2_ops, }, }; =20 @@ -416,13 +407,12 @@ static struct clk_rcg2 disp_cc_mdss_dptx1_link_clk_sr= c =3D { .mnd_width =3D 0, .hid_width =3D 5, .parent_map =3D disp_cc_parent_map_3, - .freq_tbl =3D ftbl_disp_cc_mdss_dptx0_link_clk_src, .clkr.hw.init =3D &(const struct clk_init_data) { .name =3D "disp_cc_mdss_dptx1_link_clk_src", .parent_data =3D disp_cc_parent_data_3, .num_parents =3D ARRAY_SIZE(disp_cc_parent_data_3), .flags =3D CLK_SET_RATE_PARENT, - .ops =3D &clk_rcg2_ops, + .ops =3D &clk_byte2_ops, }, }; =20 @@ -476,13 +466,12 @@ static struct clk_rcg2 disp_cc_mdss_dptx2_link_clk_sr= c =3D { .mnd_width =3D 0, .hid_width =3D 5, .parent_map =3D disp_cc_parent_map_3, - .freq_tbl =3D ftbl_disp_cc_mdss_dptx0_link_clk_src, .clkr.hw.init =3D &(const struct clk_init_data) { .name =3D "disp_cc_mdss_dptx2_link_clk_src", .parent_data =3D disp_cc_parent_data_3, .num_parents =3D ARRAY_SIZE(disp_cc_parent_data_3), .flags =3D CLK_SET_RATE_PARENT, - .ops =3D &clk_rcg2_ops, + .ops =3D &clk_byte2_ops, }, }; =20 @@ -536,13 +525,12 @@ static struct clk_rcg2 disp_cc_mdss_dptx3_link_clk_sr= c =3D { .mnd_width =3D 0, .hid_width =3D 5, .parent_map =3D disp_cc_parent_map_3, - .freq_tbl =3D ftbl_disp_cc_mdss_dptx0_link_clk_src, .clkr.hw.init =3D &(const struct clk_init_data) { .name =3D "disp_cc_mdss_dptx3_link_clk_src", .parent_data =3D disp_cc_parent_data_3, .num_parents =3D ARRAY_SIZE(disp_cc_parent_data_3), .flags =3D CLK_SET_RATE_PARENT, - .ops =3D &clk_rcg2_ops, + .ops =3D &clk_byte2_ops, }, }; =20 --=20 2.39.2