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charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20240424-cpufeature_fixes-v1-1-585e73d2226b@rivosinc.com> References: <20240424-cpufeature_fixes-v1-0-585e73d2226b@rivosinc.com> In-Reply-To: <20240424-cpufeature_fixes-v1-0-585e73d2226b@rivosinc.com> To: Paul Walmsley , Palmer Dabbelt , Albert Ou , Guo Ren , Conor Dooley , Conor Dooley , =?utf-8?q?Cl=C3=A9ment_L=C3=A9ger?= , Evan Green Cc: Palmer Dabbelt , linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, Charlie Jenkins X-Mailer: b4 0.13.0 X-Developer-Signature: v=1; a=ed25519-sha256; t=1713975728; l=4740; i=charlie@rivosinc.com; s=20231120; h=from:subject:message-id; bh=PYZfCtA79Xr5VNJKr9n7fy84USLuN54khgYv4wgcjQo=; b=rlVl8T/xGO1/2xV6GwKE/PvkrwKe/pC57MOBlWz8JPpE33mWa2+YfUXu+QONVTmwtYaEmjPaJ 4/ZqnqEUBHKCCDC5PDpWOnN/B1tU8IeenzR0EJegRx6uMc6C9M5AhLm X-Developer-Key: i=charlie@rivosinc.com; a=ed25519; pk=t4RSWpMV1q5lf/NWIeR9z58bcje60/dbtxxmoSfBEcs= The riscv_cpuinfo struct that contains mvendorid and marchid is not populated until all harts are booted which happens after the DT parsing. Use the vendorid/archid values from the DT if available or assume all harts have the same values as the boot hart as a fallback. Fixes: d82f32202e0d ("RISC-V: Ignore V from the riscv,isa DT property on ol= der T-Head CPUs") Signed-off-by: Charlie Jenkins Reviewed-by: Conor Dooley --- arch/riscv/include/asm/sbi.h | 2 ++ arch/riscv/kernel/cpu.c | 40 ++++++++++++++++++++++++++++++++++++--= -- arch/riscv/kernel/cpufeature.c | 12 ++++++++++-- 3 files changed, 48 insertions(+), 6 deletions(-) diff --git a/arch/riscv/include/asm/sbi.h b/arch/riscv/include/asm/sbi.h index 6e68f8dff76b..0fab508a65b3 100644 --- a/arch/riscv/include/asm/sbi.h +++ b/arch/riscv/include/asm/sbi.h @@ -370,6 +370,8 @@ static inline int sbi_remote_fence_i(const struct cpuma= sk *cpu_mask) { return -1 static inline void sbi_init(void) {} #endif /* CONFIG_RISCV_SBI */ =20 +unsigned long riscv_get_mvendorid(void); +unsigned long riscv_get_marchid(void); unsigned long riscv_cached_mvendorid(unsigned int cpu_id); unsigned long riscv_cached_marchid(unsigned int cpu_id); unsigned long riscv_cached_mimpid(unsigned int cpu_id); diff --git a/arch/riscv/kernel/cpu.c b/arch/riscv/kernel/cpu.c index d11d6320fb0d..c1f3655238fd 100644 --- a/arch/riscv/kernel/cpu.c +++ b/arch/riscv/kernel/cpu.c @@ -139,6 +139,34 @@ int riscv_of_parent_hartid(struct device_node *node, u= nsigned long *hartid) return -1; } =20 +unsigned long __init riscv_get_marchid(void) +{ + struct riscv_cpuinfo *ci =3D this_cpu_ptr(&riscv_cpuinfo); + +#if IS_ENABLED(CONFIG_RISCV_SBI) + ci->marchid =3D sbi_spec_is_0_1() ? 0 : sbi_get_marchid(); +#elif IS_ENABLED(CONFIG_RISCV_M_MODE) + ci->marchid =3D csr_read(CSR_MARCHID); +#else + ci->marchid =3D 0; +#endif + return ci->marchid; +} + +unsigned long __init riscv_get_mvendorid(void) +{ + struct riscv_cpuinfo *ci =3D this_cpu_ptr(&riscv_cpuinfo); + +#if IS_ENABLED(CONFIG_RISCV_SBI) + ci->mvendorid =3D sbi_spec_is_0_1() ? 0 : sbi_get_mvendorid(); +#elif IS_ENABLED(CONFIG_RISCV_M_MODE) + ci->mvendorid =3D csr_read(CSR_MVENDORID); +#else + ci->mvendorid =3D 0; +#endif + return ci->mvendorid; +} + DEFINE_PER_CPU(struct riscv_cpuinfo, riscv_cpuinfo); =20 unsigned long riscv_cached_mvendorid(unsigned int cpu_id) @@ -170,12 +198,16 @@ static int riscv_cpuinfo_starting(unsigned int cpu) struct riscv_cpuinfo *ci =3D this_cpu_ptr(&riscv_cpuinfo); =20 #if IS_ENABLED(CONFIG_RISCV_SBI) - ci->mvendorid =3D sbi_spec_is_0_1() ? 0 : sbi_get_mvendorid(); - ci->marchid =3D sbi_spec_is_0_1() ? 0 : sbi_get_marchid(); + if (!ci->mvendorid) + ci->mvendorid =3D sbi_spec_is_0_1() ? 0 : sbi_get_mvendorid(); + if (!ci->marchid) + ci->marchid =3D sbi_spec_is_0_1() ? 0 : sbi_get_marchid(); ci->mimpid =3D sbi_spec_is_0_1() ? 0 : sbi_get_mimpid(); #elif IS_ENABLED(CONFIG_RISCV_M_MODE) - ci->mvendorid =3D csr_read(CSR_MVENDORID); - ci->marchid =3D csr_read(CSR_MARCHID); + if (!ci->mvendorid) + ci->mvendorid =3D csr_read(CSR_MVENDORID); + if (!ci->marchid) + ci->marchid =3D csr_read(CSR_MARCHID); ci->mimpid =3D csr_read(CSR_MIMPID); #else ci->mvendorid =3D 0; diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c index 3ed2359eae35..c6e27b45e192 100644 --- a/arch/riscv/kernel/cpufeature.c +++ b/arch/riscv/kernel/cpufeature.c @@ -490,6 +490,8 @@ static void __init riscv_fill_hwcap_from_isa_string(uns= igned long *isa2hwcap) struct acpi_table_header *rhct; acpi_status status; unsigned int cpu; + u64 boot_vendorid; + u64 boot_archid; =20 if (!acpi_disabled) { status =3D acpi_get_table(ACPI_SIG_RHCT, 0, &rhct); @@ -497,6 +499,13 @@ static void __init riscv_fill_hwcap_from_isa_string(un= signed long *isa2hwcap) return; } =20 + /* + * Naively assume that all harts have the same mvendorid/marchid as the + * boot hart. + */ + boot_vendorid =3D riscv_get_mvendorid(); + boot_archid =3D riscv_get_marchid(); + for_each_possible_cpu(cpu) { struct riscv_isainfo *isainfo =3D &hart_isa[cpu]; unsigned long this_hwcap =3D 0; @@ -544,8 +553,7 @@ static void __init riscv_fill_hwcap_from_isa_string(uns= igned long *isa2hwcap) * CPU cores with the ratified spec will contain non-zero * marchid. */ - if (acpi_disabled && riscv_cached_mvendorid(cpu) =3D=3D THEAD_VENDOR_ID = && - riscv_cached_marchid(cpu) =3D=3D 0x0) { + if (acpi_disabled && boot_vendorid =3D=3D THEAD_VENDOR_ID && boot_archid= =3D=3D 0x0) { this_hwcap &=3D ~isa2hwcap[RISCV_ISA_EXT_v]; clear_bit(RISCV_ISA_EXT_v, isainfo->isa); } --=20 2.44.0 From nobody Sat May 18 04:46:17 2024 Received: from mail-pg1-f169.google.com (mail-pg1-f169.google.com [209.85.215.169]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C6110161913 for ; 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Wed, 24 Apr 2024 09:22:13 -0700 (PDT) Received: from charlie.ba.rivosinc.com ([64.71.180.162]) by smtp.gmail.com with ESMTPSA id s8-20020a17090a1c0800b002a610ef880bsm14505760pjs.6.2024.04.24.09.22.11 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 24 Apr 2024 09:22:12 -0700 (PDT) From: Charlie Jenkins Date: Wed, 24 Apr 2024 09:19:55 -0700 Subject: [PATCH 2/2] riscv: cpufeature: Fix extension subset checking Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20240424-cpufeature_fixes-v1-2-585e73d2226b@rivosinc.com> References: <20240424-cpufeature_fixes-v1-0-585e73d2226b@rivosinc.com> In-Reply-To: <20240424-cpufeature_fixes-v1-0-585e73d2226b@rivosinc.com> To: Paul Walmsley , Palmer Dabbelt , Albert Ou , Guo Ren , Conor Dooley , Conor Dooley , =?utf-8?q?Cl=C3=A9ment_L=C3=A9ger?= , Evan Green Cc: Palmer Dabbelt , linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, Charlie Jenkins , Alexandre Ghiti X-Mailer: b4 0.13.0 X-Developer-Signature: v=1; a=ed25519-sha256; t=1713975728; l=1120; i=charlie@rivosinc.com; s=20231120; h=from:subject:message-id; bh=RrP4p1oOkU3DSs5epOmV4/BbqCtTpx1t2NayPBKRDTg=; b=fykBMmNYGQRbdKCnZBCBpAC7r/ZAcCVj+foxhpZYBt1r8uQQCIiAPcxCl/E79KO5e4NqinaiQ KxWiqVn4klhCdrNlU6ZGZ9F6O2RPTasya1RqwpiCLfDAjqIoRlwDu6r X-Developer-Key: i=charlie@rivosinc.com; a=ed25519; pk=t4RSWpMV1q5lf/NWIeR9z58bcje60/dbtxxmoSfBEcs= This loop is supposed to check if ext->subset_ext_ids[j] is valid, rather than if ext->subset_ext_ids[i] is valid, before setting the extension id ext->subset_ext_ids[j] in isainfo->isa. Signed-off-by: Charlie Jenkins Reviewed-by: Conor Dooley Reviewed-by: Alexandre Ghiti Fixes: 0d8295ed975b ("riscv: add ISA extension parsing for scalar crypto") Reviewed-by: Andrew Jones --- arch/riscv/kernel/cpufeature.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c index c6e27b45e192..6dff7bb1db3f 100644 --- a/arch/riscv/kernel/cpufeature.c +++ b/arch/riscv/kernel/cpufeature.c @@ -607,7 +607,7 @@ static int __init riscv_fill_hwcap_from_ext_list(unsign= ed long *isa2hwcap) =20 if (ext->subset_ext_size) { for (int j =3D 0; j < ext->subset_ext_size; j++) { - if (riscv_isa_extension_check(ext->subset_ext_ids[i])) + if (riscv_isa_extension_check(ext->subset_ext_ids[j])) set_bit(ext->subset_ext_ids[j], isainfo->isa); } } --=20 2.44.0