From nobody Sat May 18 06:04:13 2024 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 94F4815FA76; Wed, 24 Apr 2024 15:29:30 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1713972570; cv=none; b=NzGEqXw8qdS3xPTHOD8KXLGzZC4fQM3iau+FiQcXJZJRy+Rp1SiG1Jb+S+gUi7FeqL5hBIRXXRpSkBE3FCV2STFoSDcRlqigFw4zSIwFnqFovWairo7VnvRmLg49PwnCiVv1etbj4WmGRzw+BxDWaur1ko4vDJYheRV1wnDhO/w= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1713972570; c=relaxed/simple; bh=DiqvgTZBUY3PtNH3TfiCz4FuSNpD0GxOhifVBZkfCjM=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=WVoeQc7vFO4LNrSPrZ9ykbORHlitnOKr8PMi+5ZDcQxnlcUZGX7JuxukyMJqg5nbiqBtKOCuPHMzfAqDU0tBFYQfym/1WQZPvo5gq5+pN6KgbeohDyvGT6cBc4HiC045uIsu7mDwIMxpH3zgAHUxtHjfLiX6hWnDR+ZSU2ZURxY= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=uc1120O/; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="uc1120O/" Received: by smtp.kernel.org (Postfix) with ESMTPS id 2E011C113CE; Wed, 24 Apr 2024 15:29:30 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1713972570; bh=DiqvgTZBUY3PtNH3TfiCz4FuSNpD0GxOhifVBZkfCjM=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=uc1120O/6j0Xn8sL2lbfJOmtbl56+d8qwLFlslw9Q5Tjr2pa+OWYpecv3tS0eHks2 fM4VqDkwPF+N7orPmP5L3O5uLvvnPNcSzF2sCMjKiVN27yhC/brwENGTJqZzSiivEZ wcZhINN+ZPi6ZD8ok+zXp0cqC/NxAGAYvhYWHGMZZ/wMhw87oEAi/ziBBP7D5xtjgm cIeAQjdJqWTH9KzBOWu3Vqk9or4+LTD8MRgFWrFTfaO14dLMdvetPBGtSUBOuURwLj czG0U+W7s/VpW7Z+/IXOIwPwxDIdDLAoqYfH+D57j/Oa4uYLyVByfKDFpvUVTQIPj5 K8WvSWggFdZQw== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 15F60C07E8E; Wed, 24 Apr 2024 15:29:30 +0000 (UTC) From: Xilin Wu via B4 Relay Date: Wed, 24 Apr 2024 23:29:06 +0800 Subject: [PATCH 01/10] dt-bindings: pwm: Add SI-EN SN3112 PWM support Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20240424-ayn-odin2-initial-v1-1-e0aa05c991fd@gmail.com> References: <20240424-ayn-odin2-initial-v1-0-e0aa05c991fd@gmail.com> In-Reply-To: <20240424-ayn-odin2-initial-v1-0-e0aa05c991fd@gmail.com> To: =?utf-8?q?Uwe_Kleine-K=C3=B6nig?= , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Junhao Xie , Neil Armstrong , Jessica Zhang , Sam Ravnborg , David Airlie , Daniel Vetter , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , Bjorn Andersson , Konrad Dybcio , Tengfei Fan , Molly Sophia , Junhao Xie Cc: linux-pwm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, linux-arm-msm@vger.kernel.org, Xilin Wu X-Mailer: b4 0.13.0 X-Developer-Signature: v=1; a=ed25519-sha256; t=1713972563; l=1687; i=wuxilin123@gmail.com; s=20240424; h=from:subject:message-id; bh=Sd6Ecnq5OawH+103xxOmJ3nKkBaj9Y2Zw5nnRbO/UF4=; b=eUTowkOmB04wln4zX+/5k93CvZLX7lo0igr5S4Ch5podI8Hk35rew+sRl3bcVm14W1QrSqnT3 o1etBHkXd58C3DNUlIk2LarC5FzddpwfLuaYg8S82Fg6RCYkzg1QMsN X-Developer-Key: i=wuxilin123@gmail.com; a=ed25519; pk=vPnxeJnlD/PfEbyQPZzaay5ezxI/lMrke7qXy31lSM8= X-Endpoint-Received: by B4 Relay for wuxilin123@gmail.com/20240424 with auth_id=157 X-Original-From: Xilin Wu Reply-To: wuxilin123@gmail.com From: Junhao Xie Add a new driver for the SI-EN SN3112 12-channel 8-bit PWM LED controller. Signed-off-by: Junhao Xie --- .../devicetree/bindings/pwm/si-en,sn3112-pwm.yaml | 55 ++++++++++++++++++= ++++ 1 file changed, 55 insertions(+) diff --git a/Documentation/devicetree/bindings/pwm/si-en,sn3112-pwm.yaml b/= Documentation/devicetree/bindings/pwm/si-en,sn3112-pwm.yaml new file mode 100644 index 000000000000..2ab229ac40ce --- /dev/null +++ b/Documentation/devicetree/bindings/pwm/si-en,sn3112-pwm.yaml @@ -0,0 +1,55 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pwm/si-en,sn3112-pwm.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: SI-EN SN3112 12-channel 8-bit PWM LED controller + +maintainers: + - Junhao Xie + +allOf: + - $ref: pwm.yaml# + +properties: + compatible: + const: si-en,sn3112-pwm + + reg: + const: 0x54 + description: I2C slave address + + sdb-gpios: + maxItems: 1 + description: GPIO pin to hardware shutdown the device. + + vdd-supply: + description: Chip vdd supply + + "#pwm-cells": + const: 1 + +required: + - compatible + - reg + - "#pwm-cells" + +additionalProperties: false + +examples: + - | + #include + + i2c { + #address-cells =3D <1>; + #size-cells =3D <0>; + + pwm@54 { + compatible =3D "si-en,sn3112-pwm"; + reg =3D <0x54>; + sdb-gpios =3D <&pio 1 1 GPIO_ACTIVE_LOW>; /* PA1 */ + vdd-supply =3D <®_dcdc1>; + #pwm-cells =3D <1>; + }; + }; --=20 2.44.0 From nobody Sat May 18 06:04:13 2024 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 94F0615FA70; Wed, 24 Apr 2024 15:29:30 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1713972570; cv=none; b=TxZGzLM/VZ47mXHoo4V3Ii7ABAF18iqzpqOwLUQlsaXDzCy+Z9nIn57rhfrY5HQGRdu4qDfRglu+NOKYl9btD6KapOPceg2KD4trS3YFjcNij3qdOupRMM4QTEm77mjzm0D+a4FycSyAQBgKBOycEbvVR+FgLSNUZbJouBo4eJE= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1713972570; 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Wed, 24 Apr 2024 15:29:30 +0000 (UTC) From: Xilin Wu via B4 Relay Date: Wed, 24 Apr 2024 23:29:07 +0800 Subject: [PATCH 02/10] pwm: Add SI-EN SN3112 PWM support Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20240424-ayn-odin2-initial-v1-2-e0aa05c991fd@gmail.com> References: <20240424-ayn-odin2-initial-v1-0-e0aa05c991fd@gmail.com> In-Reply-To: <20240424-ayn-odin2-initial-v1-0-e0aa05c991fd@gmail.com> To: =?utf-8?q?Uwe_Kleine-K=C3=B6nig?= , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Junhao Xie , Neil Armstrong , Jessica Zhang , Sam Ravnborg , David Airlie , Daniel Vetter , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , Bjorn Andersson , Konrad Dybcio , Tengfei Fan , Molly Sophia , Junhao Xie Cc: linux-pwm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, linux-arm-msm@vger.kernel.org, Xilin Wu X-Mailer: b4 0.13.0 X-Developer-Signature: v=1; a=ed25519-sha256; t=1713972563; l=10699; i=wuxilin123@gmail.com; s=20240424; h=from:subject:message-id; bh=CRcoW1mNXLjSj7yu6IPFB73/snxRikqcgHYHMDdEkwo=; b=0N44s6Ip71stYnYGddQwOa5dxgVjSVSMTHPbo+EoTLvkpZuJ5W2a1wSB++1m/yk2CaszoRELD hLgbF8OcWabBPx72e2/K7O7YkUBDttDHnX0pvE8bX7JdKoZKdGN/wSt X-Developer-Key: i=wuxilin123@gmail.com; a=ed25519; pk=vPnxeJnlD/PfEbyQPZzaay5ezxI/lMrke7qXy31lSM8= X-Endpoint-Received: by B4 Relay for wuxilin123@gmail.com/20240424 with auth_id=157 X-Original-From: Xilin Wu Reply-To: wuxilin123@gmail.com From: Junhao Xie Add a new driver for the SI-EN SN3112 12-channel 8-bit PWM LED controller. Signed-off-by: Junhao Xie --- drivers/pwm/Kconfig | 10 ++ drivers/pwm/Makefile | 1 + drivers/pwm/pwm-sn3112.c | 336 +++++++++++++++++++++++++++++++++++++++++++= ++++ 3 files changed, 347 insertions(+) diff --git a/drivers/pwm/Kconfig b/drivers/pwm/Kconfig index 1dd7921194f5..e21c37c7991e 100644 --- a/drivers/pwm/Kconfig +++ b/drivers/pwm/Kconfig @@ -553,6 +553,16 @@ config PWM_SL28CPLD To compile this driver as a module, choose M here: the module will be called pwm-sl28cpld. =20 +config PWM_SN3112 + tristate "SI-EN SN3112 PWM driver" + depends on I2C + select REGMAP_I2C + help + Generic PWM framework driver for SI-EN SN3112 LED controller. + + To compile this driver as a module, choose M here: the module + will be called pwm-sn3112. + config PWM_SPEAR tristate "STMicroelectronics SPEAr PWM support" depends on PLAT_SPEAR || COMPILE_TEST diff --git a/drivers/pwm/Makefile b/drivers/pwm/Makefile index 90913519f11a..6aab2d113159 100644 --- a/drivers/pwm/Makefile +++ b/drivers/pwm/Makefile @@ -50,6 +50,7 @@ obj-$(CONFIG_PWM_RZ_MTU3) +=3D pwm-rz-mtu3.o obj-$(CONFIG_PWM_SAMSUNG) +=3D pwm-samsung.o obj-$(CONFIG_PWM_SIFIVE) +=3D pwm-sifive.o obj-$(CONFIG_PWM_SL28CPLD) +=3D pwm-sl28cpld.o +obj-$(CONFIG_PWM_SN3112) +=3D pwm-sn3112.o obj-$(CONFIG_PWM_SPEAR) +=3D pwm-spear.o obj-$(CONFIG_PWM_SPRD) +=3D pwm-sprd.o obj-$(CONFIG_PWM_STI) +=3D pwm-sti.o diff --git a/drivers/pwm/pwm-sn3112.c b/drivers/pwm/pwm-sn3112.c new file mode 100644 index 000000000000..38ef948602a3 --- /dev/null +++ b/drivers/pwm/pwm-sn3112.c @@ -0,0 +1,336 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Driver for SN3112 12-channel 8-bit PWM LED controller + * + * Copyright (c) 2024 Junhao Xie + * + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define SN3112_CHANNELS 12 +#define SN3112_REG_ENABLE 0x00 +#define SN3112_REG_PWM_VAL 0x04 +#define SN3112_REG_PWM_EN 0x13 +#define SN3112_REG_APPLY 0x16 +#define SN3112_REG_RESET 0x17 + +struct sn3112 { + struct device *pdev; + struct regmap *regmap; + struct mutex lock; + struct regulator *vdd; + uint8_t pwm_val[SN3112_CHANNELS]; + uint8_t pwm_en_reg[3]; + bool pwm_en[SN3112_CHANNELS]; +#if IS_ENABLED(CONFIG_GPIOLIB) + struct gpio_desc *sdb; +#endif +}; + +static int sn3112_write_reg(struct sn3112 *priv, unsigned int reg, + unsigned int val) +{ + int err; + + dev_dbg(priv->pdev, "request regmap_write 0x%x 0x%x\n", reg, val); + err =3D regmap_write(priv->regmap, reg, val); + if (err) + dev_warn_ratelimited( + priv->pdev, + "regmap_write to register 0x%x failed: %pe\n", reg, + ERR_PTR(err)); + + return err; +} + +static int sn3112_set_en_reg(struct sn3112 *priv, unsigned int channel, + bool enabled, bool write) +{ + unsigned int reg, bit; + + if (channel >=3D SN3112_CHANNELS) + return -EINVAL; + + /* LED_EN1: BIT5:BIT3 =3D OUT3:OUT1 */ + if (channel >=3D 0 && channel <=3D 2) + reg =3D 0, bit =3D channel + 3; + /* LED_EN2: BIT5:BIT0 =3D OUT9:OUT4 */ + else if (channel >=3D 3 && channel <=3D 8) + reg =3D 1, bit =3D channel - 3; + /* LED_EN3: BIT2:BIT0 =3D OUT12:OUT10 */ + else if (channel >=3D 9 && channel <=3D 11) + reg =3D 2, bit =3D channel - 9; + else + return -EINVAL; + + dev_dbg(priv->pdev, "channel %u enabled %u\n", channel, enabled); + dev_dbg(priv->pdev, "reg %u bit %u\n", reg, bit); + if (enabled) + set_bit(bit, (ulong *)&priv->pwm_en_reg[reg]); + else + clear_bit(bit, (ulong *)&priv->pwm_en_reg[reg]); + dev_dbg(priv->pdev, "set enable reg %u to %u\n", reg, + priv->pwm_en_reg[reg]); + + if (!write) + return 0; + return sn3112_write_reg(priv, SN3112_REG_PWM_EN + reg, + priv->pwm_en_reg[reg]); +} + +static int sn3112_set_val_reg(struct sn3112 *priv, unsigned int channel, + uint8_t val, bool write) +{ + if (channel >=3D SN3112_CHANNELS) + return -EINVAL; + priv->pwm_val[channel] =3D val; + dev_dbg(priv->pdev, "set value reg %u to %u\n", channel, + priv->pwm_val[channel]); + + if (!write) + return 0; + return sn3112_write_reg(priv, SN3112_REG_PWM_VAL + channel, + priv->pwm_val[channel]); +} + +static int sn3112_write_all(struct sn3112 *priv) +{ + int i, ret; + + /* regenerate enable register values */ + for (i =3D 0; i < SN3112_CHANNELS; i++) { + ret =3D sn3112_set_en_reg(priv, i, priv->pwm_en[i], false); + if (ret !=3D 0) + return ret; + } + + /* use random value to clear all registers */ + ret =3D sn3112_write_reg(priv, SN3112_REG_RESET, 0x66); + if (ret !=3D 0) + return ret; + + /* set software enable register */ + ret =3D sn3112_write_reg(priv, SN3112_REG_ENABLE, 1); + if (ret !=3D 0) + return ret; + + /* rewrite pwm value register */ + for (i =3D 0; i < SN3112_CHANNELS; i++) { + ret =3D sn3112_write_reg(priv, SN3112_REG_PWM_VAL + i, + priv->pwm_val[i]); + if (ret !=3D 0) + return ret; + } + + /* rewrite pwm enable register */ + for (i =3D 0; i < 3; i++) { + ret =3D sn3112_write_reg(priv, SN3112_REG_PWM_EN + i, + priv->pwm_en_reg[i]); + if (ret !=3D 0) + return ret; + } + + /* use random value to apply changes */ + ret =3D sn3112_write_reg(priv, SN3112_REG_APPLY, 0x66); + if (ret !=3D 0) + return ret; + + dev_dbg(priv->pdev, "reinitialized\n"); + return 0; +} + +static int sn3112_pwm_request(struct pwm_chip *chip, struct pwm_device *pw= m) +{ + struct sn3112 *priv =3D pwmchip_get_drvdata(chip); + + if (pwm->hwpwm >=3D SN3112_CHANNELS) + return -EINVAL; + + dev_dbg(priv->pdev, "sn3112 request channel %u\n", pwm->hwpwm); + pwm->args.period =3D 1000000; + return 0; +} + +static int sn3112_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm, + const struct pwm_state *state) +{ + u64 val =3D 0; + struct sn3112 *priv =3D pwmchip_get_drvdata(chip); + + if (pwm->hwpwm >=3D SN3112_CHANNELS) + return -EINVAL; + + if (state->polarity !=3D PWM_POLARITY_NORMAL) + return -EINVAL; + + if (state->period <=3D 0) + return -EINVAL; + + val =3D mul_u64_u64_div_u64(state->duty_cycle, 0xff, state->period); + dev_dbg(priv->pdev, "duty_cycle %llu period %llu\n", state->duty_cycle, + state->period); + dev_dbg(priv->pdev, "set channel %u value to %llu\n", pwm->hwpwm, val); + dev_dbg(priv->pdev, "set channel %u enabled to %u\n", pwm->hwpwm, + state->enabled); + + mutex_lock(&priv->lock); + sn3112_set_en_reg(priv, pwm->hwpwm, state->enabled, true); + sn3112_set_val_reg(priv, pwm->hwpwm, val, true); + sn3112_write_reg(priv, SN3112_REG_APPLY, 0x66); + mutex_unlock(&priv->lock); + + return 0; +} + +static const struct pwm_ops sn3112_pwm_ops =3D { + .apply =3D sn3112_pwm_apply, + .request =3D sn3112_pwm_request, +}; + +static const struct regmap_config sn3112_regmap_i2c_config =3D { + .reg_bits =3D 8, + .val_bits =3D 8, + .max_register =3D 24, + .cache_type =3D REGCACHE_NONE, +}; + +static int sn3112_pwm_probe(struct i2c_client *client) +{ + struct pwm_chip *chip; + struct sn3112 *priv; + int ret, i; + + dev_dbg(&client->dev, "probing\n"); + chip =3D devm_pwmchip_alloc(&client->dev, SN3112_CHANNELS, sizeof(*priv)); + if (IS_ERR(chip)) + return PTR_ERR(chip); + priv =3D pwmchip_get_drvdata(chip); + priv->pdev =3D &client->dev; + + /* initialize sn3112 (chip does not support read command) */ + for (i =3D 0; i < SN3112_CHANNELS; i++) + priv->pwm_en[i] =3D false; + for (i =3D 0; i < SN3112_CHANNELS; i++) + priv->pwm_val[i] =3D 0; + for (i =3D 0; i < 3; i++) + priv->pwm_en_reg[i] =3D 0; + + /* enable sn5112 power vdd */ + priv->vdd =3D devm_regulator_get(priv->pdev, "vdd"); + if (IS_ERR(priv->vdd)) { + ret =3D PTR_ERR(priv->vdd); + dev_err(priv->pdev, "Unable to get vdd regulator: %d\n", ret); + return ret; + } + +#if IS_ENABLED(CONFIG_GPIOLIB) + /* sn5112 hardware shutdown pin */ + priv->sdb =3D devm_gpiod_get_optional(priv->pdev, "sdb", GPIOD_OUT_LOW); + if (PTR_ERR(priv->sdb) =3D=3D -EPROBE_DEFER) + return -EPROBE_DEFER; +#endif + + /* enable sn5112 power vdd */ + ret =3D regulator_enable(priv->vdd); + if (ret < 0) { + dev_err(priv->pdev, "Unable to enable regulator: %d\n", ret); + return ret; + } + + priv->regmap =3D devm_regmap_init_i2c(client, &sn3112_regmap_i2c_config); + if (IS_ERR(priv->regmap)) { + ret =3D PTR_ERR(priv->regmap); + dev_err(priv->pdev, "Failed to initialize register map: %d\n", + ret); + return ret; + } + + i2c_set_clientdata(client, chip); + mutex_init(&priv->lock); + + chip->ops =3D &sn3112_pwm_ops; + ret =3D pwmchip_add(chip); + if (ret < 0) + return ret; + +#if IS_ENABLED(CONFIG_GPIOLIB) + /* disable hardware shutdown pin */ + if (priv->sdb) + gpiod_set_value(priv->sdb, 0); +#endif + + /* initialize registers */ + ret =3D sn3112_write_all(priv); + if (ret !=3D 0) { + dev_err(priv->pdev, "Failed to initialize sn3112: %d\n", ret); + return ret; + } + + dev_info(&client->dev, + "Found SI-EN SN3112 12-channel 8-bit PWM LED controller\n"); + return 0; +} + +static void sn3112_pwm_remove(struct i2c_client *client) +{ + struct pwm_chip *chip =3D i2c_get_clientdata(client); + struct sn3112 *priv =3D pwmchip_get_drvdata(chip); + + dev_dbg(priv->pdev, "remove\n"); + + /* set software enable register */ + sn3112_write_reg(priv, SN3112_REG_ENABLE, 0); + + /* use random value to apply changes */ + sn3112_write_reg(priv, SN3112_REG_APPLY, 0x66); + +#if IS_ENABLED(CONFIG_GPIOLIB) + /* enable hardware shutdown pin */ + if (priv->sdb) + gpiod_set_value(priv->sdb, 1); +#endif + + /* power-off sn5112 power vdd */ + regulator_disable(priv->vdd); + + pwmchip_remove(chip); +} + +static const struct i2c_device_id sn3112_id[] =3D { + { "sn3112", 0 }, + { /* sentinel */ }, +}; +MODULE_DEVICE_TABLE(i2c, sn3112_id); + +#ifdef CONFIG_OF +static const struct of_device_id sn3112_dt_ids[] =3D { + { .compatible =3D "si-en,sn3112-pwm", }, + { /* sentinel */ } +}; +MODULE_DEVICE_TABLE(of, sn3112_dt_ids); +#endif + +static struct i2c_driver sn3112_i2c_driver =3D { + .driver =3D { + .name =3D "sn3112-pwm", + .of_match_table =3D of_match_ptr(sn3112_dt_ids), + }, + .probe =3D sn3112_pwm_probe, + .remove =3D sn3112_pwm_remove, + .id_table =3D sn3112_id, +}; + +module_i2c_driver(sn3112_i2c_driver); + +MODULE_AUTHOR("BigfootACA "); +MODULE_DESCRIPTION("PWM driver for SI-EN SN3112"); +MODULE_LICENSE("GPL"); --=20 2.44.0 From nobody Sat May 18 06:04:13 2024 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 94EB415FA68; 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charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20240424-ayn-odin2-initial-v1-3-e0aa05c991fd@gmail.com> References: <20240424-ayn-odin2-initial-v1-0-e0aa05c991fd@gmail.com> In-Reply-To: <20240424-ayn-odin2-initial-v1-0-e0aa05c991fd@gmail.com> To: =?utf-8?q?Uwe_Kleine-K=C3=B6nig?= , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Junhao Xie , Neil Armstrong , Jessica Zhang , Sam Ravnborg , David Airlie , Daniel Vetter , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , Bjorn Andersson , Konrad Dybcio , Tengfei Fan , Molly Sophia , Junhao Xie Cc: linux-pwm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, linux-arm-msm@vger.kernel.org, Xilin Wu X-Mailer: b4 0.13.0 X-Developer-Signature: v=1; a=ed25519-sha256; t=1713972563; l=2025; i=wuxilin123@gmail.com; s=20240424; h=from:subject:message-id; bh=0VK+Kj9m0jq5c+1jyByVu388zTnbuAfKwi30ATqYDLI=; b=AweMBhEqEuTCc4enzY9h7GdeI8XUuiwF9MDWxLyD+4cgpmTUAoig7/9l8o0WgxW1VxR4gHORU cYNQ8NATvgzA6BG+EfLmVbx9tD6Qq3ybWio/Y940cWK+I6rFS9he+gk X-Developer-Key: i=wuxilin123@gmail.com; a=ed25519; pk=vPnxeJnlD/PfEbyQPZzaay5ezxI/lMrke7qXy31lSM8= X-Endpoint-Received: by B4 Relay for wuxilin123@gmail.com/20240424 with auth_id=157 X-Original-From: Xilin Wu Reply-To: wuxilin123@gmail.com From: Xilin Wu Synaptics TD4328 is a display driver IC used to drive LCD DSI panels. Signed-off-by: Xilin Wu --- .../bindings/display/panel/synaptics,td4328.yaml | 69 ++++++++++++++++++= ++++ 1 file changed, 69 insertions(+) diff --git a/Documentation/devicetree/bindings/display/panel/synaptics,td43= 28.yaml b/Documentation/devicetree/bindings/display/panel/synaptics,td4328.= yaml new file mode 100644 index 000000000000..216f2fb22b88 --- /dev/null +++ b/Documentation/devicetree/bindings/display/panel/synaptics,td4328.yaml @@ -0,0 +1,69 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/panel/synaptics,td4328.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Synaptics TD4328-based DSI display panels + +maintainers: + - Xilin Wu + +description: + The Synaptics TD4328 is a generic DSI Panel IC used to control + LCD panels. + +allOf: + - $ref: panel-common.yaml# + +properties: + compatible: + contains: + const: syna,td4328 + + vdd-supply: + description: Digital voltage rail + + vddio-supply: + description: Digital I/O voltage rail + + reg: true + port: true + +required: + - compatible + - reg + - reset-gpios + - vdd-supply + - vddio-supply + - port + +unevaluatedProperties: false + +examples: + - | + #include + + dsi { + #address-cells =3D <1>; + #size-cells =3D <0>; + + panel@0 { + compatible =3D "syna,td4328"; + reg =3D <0>; + + backlight =3D <&backlight>; + reset-gpios =3D <&tlmm 133 GPIO_ACTIVE_LOW>; + + vdd-supply =3D <&vdd_lcm_2p8>; + vddio-supply =3D <&vreg_l12b_1p8>; + + port { + panel_in_0: endpoint { + remote-endpoint =3D <&dsi0_out>; + }; + }; + }; + }; + +... --=20 2.44.0 From nobody Sat May 18 06:04:13 2024 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id AC5E815FA7D; Wed, 24 Apr 2024 15:29:30 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1713972570; cv=none; b=untkluHMZ2tllKwE+GiZH4bXrJDMO2bR5XoH8Yyb8Kb1YsDF7loLDOMHDKY6pi42hd27pbDFkWnFF5ujT43cblv/xTgycwQHdetJM/WPDb/6yaWmYrXmpjQVhw0qewx0yTU33Jb2P7aBKGtIo8U25R+tjb6JzwH6+SlNd7DFhWw= ARC-Message-Signature: i=1; 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b=C9BoxbgnJwNMbfUczAm5ya/8F+HAGmMFXtCXFYxNY/OV8ZyEZz76wcmLEULOqITi5 Laff9hjH72l5yTinwWclmNdPx2DIqs7UNY596NdpMfrjAqyvcUXFN+ZiOpToVPvF2D AtOq8Qvny6wli/OL9QQrnraSxSgdyMBo5LJQL2EPapnYCRTNXvSO6nLUGbtJz843tx HBYnzdgi8/Yk8bbTGeGjtP7zDq4Os3KFnORLvUVX6Yy4lboT4yJydnh8mmmLXOaRqg DH/7iBEBfztqtGN5P/7F9eekVxEnmiRvYR8yKMzyEln2owlYuo8vDWWQ4/c3If6bGY A24ghkEUnHFSA== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 4F2D0C4345F; Wed, 24 Apr 2024 15:29:30 +0000 (UTC) From: Xilin Wu via B4 Relay Date: Wed, 24 Apr 2024 23:29:09 +0800 Subject: [PATCH 04/10] drm/panel: Add driver for Synaptics TD4328 LCD panel Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20240424-ayn-odin2-initial-v1-4-e0aa05c991fd@gmail.com> References: <20240424-ayn-odin2-initial-v1-0-e0aa05c991fd@gmail.com> In-Reply-To: <20240424-ayn-odin2-initial-v1-0-e0aa05c991fd@gmail.com> To: =?utf-8?q?Uwe_Kleine-K=C3=B6nig?= , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Junhao Xie , Neil Armstrong , Jessica Zhang , Sam Ravnborg , David Airlie , Daniel Vetter , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , Bjorn Andersson , Konrad Dybcio , Tengfei Fan , Molly Sophia , Junhao Xie Cc: linux-pwm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, linux-arm-msm@vger.kernel.org, Xilin Wu X-Mailer: b4 0.13.0 X-Developer-Signature: v=1; a=ed25519-sha256; t=1713972563; l=8690; i=wuxilin123@gmail.com; s=20240424; h=from:subject:message-id; bh=vBXmgfQvNHQkw/pZY8cGKOKpfT0S0Vam5IlRm/dfwZ8=; b=KevvcObJWYXSjlHkLwa5nIIOnFi5HxPCK+S8y/IACiIfJ1U+0qtSKMS+8MN3mQrJU47+bOxRf YvVNIvdfH96BbExx/xTSjScjjPDj+wxFIoxPaWnCeOy0LhE6rGnRm85 X-Developer-Key: i=wuxilin123@gmail.com; a=ed25519; pk=vPnxeJnlD/PfEbyQPZzaay5ezxI/lMrke7qXy31lSM8= X-Endpoint-Received: by B4 Relay for wuxilin123@gmail.com/20240424 with auth_id=157 X-Original-From: Xilin Wu Reply-To: wuxilin123@gmail.com From: Xilin Wu Add support for the 1920x1080 LCD panel driven by the Synaptics TD4328 IC, as found on AYN Odin 2. Co-developed-by: Junhao Xie Signed-off-by: Junhao Xie Signed-off-by: Xilin Wu --- drivers/gpu/drm/panel/Kconfig | 10 + drivers/gpu/drm/panel/Makefile | 1 + drivers/gpu/drm/panel/panel-synaptics-td4328.c | 246 +++++++++++++++++++++= ++++ 3 files changed, 257 insertions(+) diff --git a/drivers/gpu/drm/panel/Kconfig b/drivers/gpu/drm/panel/Kconfig index ab67789e59a2..69852a35eccd 100644 --- a/drivers/gpu/drm/panel/Kconfig +++ b/drivers/gpu/drm/panel/Kconfig @@ -845,6 +845,16 @@ config DRM_PANEL_SYNAPTICS_R63353 Say Y if you want to enable support for panels based on the Synaptics R63353 controller. =20 +config DRM_PANEL_SYNAPTICS_TD4328 + tristate "Synaptics TD4328-based panels" + depends on OF + depends on DRM_MIPI_DSI + depends on BACKLIGHT_CLASS_DEVICE + select DRM_KMS_HELPER + help + Say Y if you want to enable support for panels based on the + Synaptics TD4328 controller. + config DRM_PANEL_TDO_TL070WSH30 tristate "TDO TL070WSH30 DSI panel" depends on OF diff --git a/drivers/gpu/drm/panel/Makefile b/drivers/gpu/drm/panel/Makefile index 0b40b010e8e7..927013e3eb11 100644 --- a/drivers/gpu/drm/panel/Makefile +++ b/drivers/gpu/drm/panel/Makefile @@ -81,6 +81,7 @@ obj-$(CONFIG_DRM_PANEL_SITRONIX_ST7701) +=3D panel-sitron= ix-st7701.o obj-$(CONFIG_DRM_PANEL_SITRONIX_ST7703) +=3D panel-sitronix-st7703.o obj-$(CONFIG_DRM_PANEL_SITRONIX_ST7789V) +=3D panel-sitronix-st7789v.o obj-$(CONFIG_DRM_PANEL_SYNAPTICS_R63353) +=3D panel-synaptics-r63353.o +obj-$(CONFIG_DRM_PANEL_SYNAPTICS_TD4328) +=3D panel-synaptics-td4328.o obj-$(CONFIG_DRM_PANEL_SONY_ACX565AKM) +=3D panel-sony-acx565akm.o obj-$(CONFIG_DRM_PANEL_SONY_TD4353_JDI) +=3D panel-sony-td4353-jdi.o obj-$(CONFIG_DRM_PANEL_SONY_TULIP_TRULY_NT35521) +=3D panel-sony-tulip-tru= ly-nt35521.o diff --git a/drivers/gpu/drm/panel/panel-synaptics-td4328.c b/drivers/gpu/d= rm/panel/panel-synaptics-td4328.c new file mode 100644 index 000000000000..0fb0ddd9373d --- /dev/null +++ b/drivers/gpu/drm/panel/panel-synaptics-td4328.c @@ -0,0 +1,246 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Generated with linux-mdss-dsi-panel-driver-generator from vendor device= tree. + * Copyright (c) 2024 Xilin Wu + * Copyright (c) 2024 Junhao Xie + */ + +#include +#include +#include +#include +#include + +#include +#include +#include +#include + +struct td4328 { + struct drm_panel panel; + struct mipi_dsi_device *dsi; + struct regulator_bulk_data supplies[2]; + struct gpio_desc *reset_gpio; +}; + +static inline struct td4328 *to_td4328(struct drm_panel *panel) +{ + return container_of(panel, struct td4328, panel); +} + +static void td4328_reset(struct td4328 *ctx) +{ + gpiod_set_value_cansleep(ctx->reset_gpio, 0); + usleep_range(10000, 11000); + gpiod_set_value_cansleep(ctx->reset_gpio, 1); + usleep_range(10000, 11000); + gpiod_set_value_cansleep(ctx->reset_gpio, 0); + usleep_range(10000, 11000); +} + +static int td4328_on(struct td4328 *ctx) +{ + struct mipi_dsi_device *dsi =3D ctx->dsi; + struct device *dev =3D &dsi->dev; + int ret; + + dsi->mode_flags |=3D MIPI_DSI_MODE_LPM; + + mipi_dsi_dcs_write_seq(dsi, 0xb0, 0x00); + mipi_dsi_dcs_write_seq(dsi, 0xb3, 0x31); + mipi_dsi_dcs_write_seq(dsi, 0xd6, 0x00); + + ret =3D mipi_dsi_dcs_exit_sleep_mode(dsi); + if (ret < 0) { + dev_err(dev, "Failed to exit sleep mode: %d\n", ret); + return ret; + } + msleep(70); + + ret =3D mipi_dsi_dcs_set_display_on(dsi); + if (ret < 0) { + dev_err(dev, "Failed to set display on: %d\n", ret); + return ret; + } + + return 0; +} + +static int td4328_off(struct td4328 *ctx) +{ + struct mipi_dsi_device *dsi =3D ctx->dsi; + struct device *dev =3D &dsi->dev; + int ret; + + dsi->mode_flags &=3D ~MIPI_DSI_MODE_LPM; + + ret =3D mipi_dsi_dcs_set_display_off(dsi); + if (ret < 0) { + dev_err(dev, "Failed to set display off: %d\n", ret); + return ret; + } + msleep(50); + + ret =3D mipi_dsi_dcs_enter_sleep_mode(dsi); + if (ret < 0) { + dev_err(dev, "Failed to enter sleep mode: %d\n", ret); + return ret; + } + msleep(120); + + return 0; +} + +static int td4328_prepare(struct drm_panel *panel) +{ + struct td4328 *ctx =3D to_td4328(panel); + struct device *dev =3D &ctx->dsi->dev; + int ret; + + ret =3D regulator_bulk_enable(ARRAY_SIZE(ctx->supplies), ctx->supplies); + if (ret < 0) { + dev_err(dev, "Failed to enable regulators: %d\n", ret); + return ret; + } + + td4328_reset(ctx); + + ret =3D td4328_on(ctx); + if (ret < 0) { + dev_err(dev, "Failed to initialize panel: %d\n", ret); + gpiod_set_value_cansleep(ctx->reset_gpio, 1); + regulator_bulk_disable(ARRAY_SIZE(ctx->supplies), ctx->supplies); + return ret; + } + + return 0; +} + +static int td4328_unprepare(struct drm_panel *panel) +{ + struct td4328 *ctx =3D to_td4328(panel); + struct device *dev =3D &ctx->dsi->dev; + int ret; + + ret =3D td4328_off(ctx); + if (ret < 0) + dev_err(dev, "Failed to un-initialize panel: %d\n", ret); + + regulator_bulk_disable(ARRAY_SIZE(ctx->supplies), ctx->supplies); + + return 0; +} + +static const struct drm_display_mode td4328_mode =3D { + .clock =3D (1080 + 93 + 1 + 47) * (1920 + 40 + 2 + 60) * 60 / 1000, + .hdisplay =3D 1080, + .hsync_start =3D 1080 + 93, + .hsync_end =3D 1080 + 93 + 1, + .htotal =3D 1080 + 93 + 1 + 47, + .vdisplay =3D 1920, + .vsync_start =3D 1920 + 40, + .vsync_end =3D 1920 + 40 + 2, + .vtotal =3D 1920 + 40 + 2 + 60, + .width_mm =3D 75, + .height_mm =3D 133, + .type =3D DRM_MODE_TYPE_DRIVER, +}; + +static int td4328_get_modes(struct drm_panel *panel, + struct drm_connector *connector) +{ + return drm_connector_helper_get_modes_fixed(connector, &td4328_mode); +} + +static enum drm_panel_orientation td4328_get_orientation(struct drm_panel = *panel) +{ + return DRM_MODE_PANEL_ORIENTATION_RIGHT_UP; +} + +static const struct drm_panel_funcs td4328_panel_funcs =3D { + .prepare =3D td4328_prepare, + .disable =3D td4328_unprepare, + .get_modes =3D td4328_get_modes, + .get_orientation =3D td4328_get_orientation, +}; + +static int td4328_probe(struct mipi_dsi_device *dsi) +{ + struct device *dev =3D &dsi->dev; + struct td4328 *ctx; + int ret; + + ctx =3D devm_kzalloc(dev, sizeof(*ctx), GFP_KERNEL); + if (!ctx) + return -ENOMEM; + + ctx->supplies[0].supply =3D "vddio"; + ctx->supplies[1].supply =3D "vdd"; + ret =3D devm_regulator_bulk_get(dev, ARRAY_SIZE(ctx->supplies), + ctx->supplies); + if (ret < 0) + return dev_err_probe(dev, ret, "Failed to get regulators\n"); + + ctx->reset_gpio =3D devm_gpiod_get(dev, "reset", GPIOD_OUT_LOW); + if (IS_ERR(ctx->reset_gpio)) + return dev_err_probe(dev, PTR_ERR(ctx->reset_gpio), + "Failed to get reset-gpios\n"); + + ctx->dsi =3D dsi; + mipi_dsi_set_drvdata(dsi, ctx); + + dsi->lanes =3D 4; + dsi->format =3D MIPI_DSI_FMT_RGB888; + dsi->mode_flags =3D MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_BURST | + MIPI_DSI_CLOCK_NON_CONTINUOUS; + + drm_panel_init(&ctx->panel, dev, &td4328_panel_funcs, + DRM_MODE_CONNECTOR_DSI); + ctx->panel.prepare_prev_first =3D true; + + ret =3D drm_panel_of_backlight(&ctx->panel); + if (ret) + return dev_err_probe(dev, ret, "Failed to get backlight\n"); + + drm_panel_add(&ctx->panel); + + ret =3D mipi_dsi_attach(dsi); + if (ret < 0) { + dev_err_probe(dev, ret, "Failed to attach to DSI host\n"); + drm_panel_remove(&ctx->panel); + return ret; + } + + return 0; +} + +static void td4328_remove(struct mipi_dsi_device *dsi) +{ + struct td4328 *ctx =3D mipi_dsi_get_drvdata(dsi); + int ret; + + ret =3D mipi_dsi_detach(dsi); + if (ret < 0) + dev_err(&dsi->dev, "Failed to detach from DSI host: %d\n", ret); + + drm_panel_remove(&ctx->panel); +} + +static const struct of_device_id td4328_of_match[] =3D { + { .compatible =3D "syna,td4328" }, + { /* sentinel */ } +}; +MODULE_DEVICE_TABLE(of, td4328_of_match); + +static struct mipi_dsi_driver td4328_driver =3D { + .probe =3D td4328_probe, + .remove =3D td4328_remove, + .driver =3D { + .name =3D "panel-td4328", + .of_match_table =3D td4328_of_match, + }, +}; +module_mipi_dsi_driver(td4328_driver); + +MODULE_DESCRIPTION("DRM driver for td4328-equipped DSI panels"); +MODULE_LICENSE("GPL"); --=20 2.44.0 From nobody Sat May 18 06:04:13 2024 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E5C9416079C; Wed, 24 Apr 2024 15:29:30 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1713972571; cv=none; b=cn6g6fFTwh0sBwqlVRouKWQod4kg1MkbhrSpSqr78tONXf9lSOwv7wP/hhzZ1UxYrFE8GDr99l2dp1pZ2I6IJzEgRc4kZHfda0kygC8eM7hggduwreLg/2AumhVlx35TWQxaUDXvbFuXf+jiKGIEMWYVzKVcllPTy7/KmqNW23g= ARC-Message-Signature: i=1; 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b=GYPoWxwfjWjBIZqzfXah+R1y39jKPnpmgHVSmpHgQifk+qjwnYgCpBFPlPGt2nvTZ yOP8czmAe6Ekh9WqewODZb1M6L4f+kw5gmp0iyzj2H1AXA51HXvZEGiLGLPN2xtj4p h30KMOmlSSPNj9+OGxCkneF0aVrSbrCax2cuHfMlwbidwwoifu6NZeg9hUAP7eZhnA u8DHvPSf2/ahiIkwK+avKByRKRa+3sQwBiF9EaIrX+eqOfavFVtZ50VnIgHs3L9QM6 2lqXRQCjM1YFG822lBgQ/IOoavFcEhLNNCTXp1HtMwPH65235fe1ExwnsCCQX5RqHU al3ziHloshvWg== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 5E454C19F4F; Wed, 24 Apr 2024 15:29:30 +0000 (UTC) From: Xilin Wu via B4 Relay Date: Wed, 24 Apr 2024 23:29:10 +0800 Subject: [PATCH 05/10] arm64: dts: qcom: pmk8550: Add PWM controller Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20240424-ayn-odin2-initial-v1-5-e0aa05c991fd@gmail.com> References: <20240424-ayn-odin2-initial-v1-0-e0aa05c991fd@gmail.com> In-Reply-To: <20240424-ayn-odin2-initial-v1-0-e0aa05c991fd@gmail.com> To: =?utf-8?q?Uwe_Kleine-K=C3=B6nig?= , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Junhao Xie , Neil Armstrong , Jessica Zhang , Sam Ravnborg , David Airlie , Daniel Vetter , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , Bjorn Andersson , Konrad Dybcio , Tengfei Fan , Molly Sophia , Junhao Xie Cc: linux-pwm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, linux-arm-msm@vger.kernel.org, Xilin Wu X-Mailer: b4 0.13.0 X-Developer-Signature: v=1; a=ed25519-sha256; t=1713972563; l=805; i=wuxilin123@gmail.com; s=20240424; h=from:subject:message-id; bh=UJJkbMFALeVJntjJ0F6Zy3BxeVdQ8NMCNMFJYC7Boyk=; b=CxOiSooLXVMHGp39j8/B3jelCeqziYdEj46802PdgC+psrDtPoDZNIW6D7J2ub0wVyd5OYEUV APrmVMQwclPD0ASCtCxD40Y4LrcBZeQAkA1iUSRraJ92DVQL/c3QGGk X-Developer-Key: i=wuxilin123@gmail.com; a=ed25519; pk=vPnxeJnlD/PfEbyQPZzaay5ezxI/lMrke7qXy31lSM8= X-Endpoint-Received: by B4 Relay for wuxilin123@gmail.com/20240424 with auth_id=157 X-Original-From: Xilin Wu Reply-To: wuxilin123@gmail.com From: Xilin Wu Add the PWM function to the pmk8550 dtsi, which is usually used to control PWM backlight on platforms using this PMIC. Signed-off-by: Xilin Wu Reviewed-by: Konrad Dybcio --- arch/arm64/boot/dts/qcom/pmk8550.dtsi | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/pmk8550.dtsi b/arch/arm64/boot/dts/qc= om/pmk8550.dtsi index c7ac9b2eaacf..8d43fbb85263 100644 --- a/arch/arm64/boot/dts/qcom/pmk8550.dtsi +++ b/arch/arm64/boot/dts/qcom/pmk8550.dtsi @@ -73,5 +73,15 @@ pmk8550_gpios: gpio@8800 { interrupt-controller; #interrupt-cells =3D <2>; }; + + pmk8550_pwm: pwm { + compatible =3D "qcom,pmk8550-pwm"; + + #address-cells =3D <1>; + #size-cells =3D <0>; + #pwm-cells =3D <2>; + + status =3D "disabled"; + }; }; }; --=20 2.44.0 From nobody Sat May 18 06:04:13 2024 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E7AE61607A1; Wed, 24 Apr 2024 15:29:30 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1713972571; cv=none; b=maWpylZp96o6y7fXvt+Q9Et11/nBsysNf/QQsVGN5QnqfseVj4HKK4GsYlF0Npka4EHblr3z+SWWwL+bxzQeOZ2RLXswO2LauV/CMWNZDnO4Fw4o1s7JwrLS3kaJEvD4687CPjf3QJcIdh/Klh0MpWk+iTEJbch24hf8uhjuLuQ= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1713972571; c=relaxed/simple; bh=ps8qVqZjeKNfojZTva19k/8ll2iZtLvnZM7p9hTjE38=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=goAnt9R5DnYqc0Pl0gmxdMdgs51TmL+SoTaUS3yOBdyNBJbGr6PDXYyAHLoYWSQjrR1alz7pwDR2RkWZJWETHDd6n89z3PpnKpt5BhKNwMY2CmuEAQNQc4Bp7IYwOrGoUV9sN+bbdcF9GdemmDyKY2npg8HBjsoDgMO5CZUblgM= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=WWO/ztVX; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="WWO/ztVX" Received: by smtp.kernel.org (Postfix) with ESMTPS id 7DED5C4AF49; Wed, 24 Apr 2024 15:29:30 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1713972570; bh=ps8qVqZjeKNfojZTva19k/8ll2iZtLvnZM7p9hTjE38=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=WWO/ztVXyClqShOKi1gpwGT2p+HM0JnU+aIW/o7CD9iTjQ5nLwHxknnGD9Apf9ki8 QTUIX1WWg9xWsknVmcZpt9hVcXBca4965XHycOD1pyaWwGVU7+qL9EMacLLE/iDntd QaHveJ7NveVPci8KaoslloczCJphpQrWOB9Bx+e4j8l9hzrN39U/i5Ij3YPyX6/Wkv CMd+wQk9ERJl81V3SzHhGy291jZn0+ibOFE1+SUzAHNPp2L0GUBmaF+nYXG2k+X+qT ibhtfN6hQ+UPfgkOxTuO0IbChSBTqcGpVv9Wf9c6v6tPHHpEGFa4RDAY/zoP4oEHvM 2Ppw5uMEEi0uw== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 72CDEC4345F; Wed, 24 Apr 2024 15:29:30 +0000 (UTC) From: Xilin Wu via B4 Relay Date: Wed, 24 Apr 2024 23:29:11 +0800 Subject: [PATCH 06/10] arm64: dts: qcom: sm8550: Add UART15 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20240424-ayn-odin2-initial-v1-6-e0aa05c991fd@gmail.com> References: <20240424-ayn-odin2-initial-v1-0-e0aa05c991fd@gmail.com> In-Reply-To: <20240424-ayn-odin2-initial-v1-0-e0aa05c991fd@gmail.com> To: =?utf-8?q?Uwe_Kleine-K=C3=B6nig?= , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Junhao Xie , Neil Armstrong , Jessica Zhang , Sam Ravnborg , David Airlie , Daniel Vetter , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , Bjorn Andersson , Konrad Dybcio , Tengfei Fan , Molly Sophia , Junhao Xie Cc: linux-pwm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, linux-arm-msm@vger.kernel.org, Xilin Wu X-Mailer: b4 0.13.0 X-Developer-Signature: v=1; a=ed25519-sha256; t=1713972563; l=1572; i=wuxilin123@gmail.com; s=20240424; h=from:subject:message-id; bh=OFzbypiVPytW4zM7r7H6VNiMNFxsnAj0i8lBbxZUWk8=; b=tQq4dufCVktTutlbsclvej4fOdX/xDLlbF43Jmj8yh8O2UYPrLVmE/j5VMRLoF9xN9P9u7ToH 8xN5wY7sFBaCOU/0mIlgdQJD5X1zB0GGgNJcIwMJgMmy2rfyknDtryu X-Developer-Key: i=wuxilin123@gmail.com; a=ed25519; pk=vPnxeJnlD/PfEbyQPZzaay5ezxI/lMrke7qXy31lSM8= X-Endpoint-Received: by B4 Relay for wuxilin123@gmail.com/20240424 with auth_id=157 X-Original-From: Xilin Wu Reply-To: wuxilin123@gmail.com From: Xilin Wu Add uart15 node for UART bus present on sm8550 SoC. Signed-off-by: Molly Sophia Signed-off-by: Xilin Wu Reviewed-by: Dmitry Baryshkov --- arch/arm64/boot/dts/qcom/sm8550.dtsi | 22 ++++++++++++++++++++++ 1 file changed, 22 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm8550.dtsi b/arch/arm64/boot/dts/qco= m/sm8550.dtsi index bc5aeb05ffc3..b8bbe88e770f 100644 --- a/arch/arm64/boot/dts/qcom/sm8550.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8550.dtsi @@ -1122,6 +1122,20 @@ spi15: spi@89c000 { #size-cells =3D <0>; status =3D "disabled"; }; + + uart15: serial@89c000 { + compatible =3D "qcom,geni-uart"; + reg =3D <0 0x89c000 0 0x4000>; + clock-names =3D "se"; + clocks =3D <&gcc GCC_QUPV3_WRAP2_S7_CLK>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&qup_uart15_default>; + interrupts =3D ; + interconnects =3D <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_C= ORE_2 0>, + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>; + interconnect-names =3D "qup-core", "qup-config"; + status =3D "disabled"; + }; }; =20 i2c_master_hub_0: geniqup@9c0000 { @@ -3856,6 +3870,14 @@ qup_uart14_cts_rts: qup-uart14-cts-rts-state { bias-pull-down; }; =20 + qup_uart15_default: qup-uart15-default-state { + /* TX, RX */ + pins =3D "gpio74", "gpio75"; + function =3D "qup2_se7"; + drive-strength =3D <2>; + bias-pull-up; + }; + sdc2_sleep: sdc2-sleep-state { clk-pins { pins =3D "sdc2_clk"; --=20 2.44.0 From nobody Sat May 18 06:04:13 2024 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E9A371607A2; Wed, 24 Apr 2024 15:29:30 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1713972571; cv=none; b=LG6uAx9NOgdolO09XDEVrE3SRDtyA64eJUw0wclu3zyeLPtoczy3tTIgkqRiyk4PiicoPwkHMOeBG+deIgS7jrTkoqV4SDxEHH2uY7jB2p3lW4ygQx3vWs62jRWPUP/AoAIIV4FO8TgmoRjbAWgPxCaL/Vq4w5rFVY7xuvtqF6Y= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; 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Wed, 24 Apr 2024 15:29:30 +0000 (UTC) From: Xilin Wu via B4 Relay Date: Wed, 24 Apr 2024 23:29:12 +0800 Subject: [PATCH 07/10] arm64: dts: qcom: sm8550: Update EAS properties Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20240424-ayn-odin2-initial-v1-7-e0aa05c991fd@gmail.com> References: <20240424-ayn-odin2-initial-v1-0-e0aa05c991fd@gmail.com> In-Reply-To: <20240424-ayn-odin2-initial-v1-0-e0aa05c991fd@gmail.com> To: =?utf-8?q?Uwe_Kleine-K=C3=B6nig?= , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Junhao Xie , Neil Armstrong , Jessica Zhang , Sam Ravnborg , David Airlie , Daniel Vetter , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , Bjorn Andersson , Konrad Dybcio , Tengfei Fan , Molly Sophia , Junhao Xie Cc: linux-pwm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, linux-arm-msm@vger.kernel.org, Xilin Wu X-Mailer: b4 0.13.0 X-Developer-Signature: v=1; a=ed25519-sha256; t=1713972563; l=6912; i=wuxilin123@gmail.com; s=20240424; h=from:subject:message-id; bh=eJdsjG3Ujl+JaIzyIaW0tLBoLUPuJTGlhV/s1VJPzzY=; b=fxx1evrD1+3dEvUHC+b13Y34IhR9IOYveFQsTNidPvGjFTP/Fj5LEY/SVF6xGs8oj4PFvfm4v 6jDAU9Scfb1BNIvSc81K9KQbtGlJxRF1cAWELGmF4/SEyvjh8P/cE/s X-Developer-Key: i=wuxilin123@gmail.com; a=ed25519; pk=vPnxeJnlD/PfEbyQPZzaay5ezxI/lMrke7qXy31lSM8= X-Endpoint-Received: by B4 Relay for wuxilin123@gmail.com/20240424 with auth_id=157 X-Original-From: Xilin Wu Reply-To: wuxilin123@gmail.com From: Xilin Wu The original values provided by Qualcomm appear to be quite inaccurate. Specifically, some heavy gaming tasks could be improperly assigned to the A510 cores by the scheduler, resulting in a CPU bottleneck. This update to the EAS properties aims to enhance the user experience across various scenarios. The power numbers were obtained using a Type-C power meter, which was directly connected to the battery connector on the AYN Odin 2 motherboard, acting as a fake battery. It should be noted that the A715 cores seem less efficient than the A710 cores. Therefore, an average value has been assigned to them, considering that the A715 and A710 cores share a single cpufreq domain. Cortex-A510 cores: 441 kHz, 564 mV, 43 mW, 350 Cx 556 kHz, 580 mV, 59 mW, 346 Cx 672 kHz, 592 mV, 71 mW, 312 Cx 787 kHz, 604 mV, 83 mW, 290 Cx 902 kHz, 608 mV, 96 mW, 288 Cx 1017 kHz, 624 mV, 107 mW, 264 Cx 1113 kHz, 636 mV, 117 mW, 252 Cx 1228 kHz, 652 mV, 130 mW, 240 Cx 1344 kHz, 668 mV, 146 mW, 235 Cx 1459 kHz, 688 mV, 155 mW, 214 Cx 1555 kHz, 704 mV, 166 mW, 205 Cx 1670 kHz, 724 mV, 178 mW, 192 Cx 1785 kHz, 744 mV, 197 mW, 189 Cx 1900 kHz, 764 mV, 221 mW, 190 Cx 2016 kHz, 784 mV, 243 mW, 188 Cx Your dynamic-power-coefficient for cpu 1: 251 Cortex-A715 cores: 614 kHz, 572 mV, 97 mW, 470 Cx 729 kHz, 592 mV, 123 mW, 473 Cx 844 kHz, 608 mV, 152 mW, 486 Cx 940 kHz, 624 mV, 178 mW, 485 Cx 1056 kHz, 644 mV, 207 mW, 465 Cx 1171 kHz, 656 mV, 243 mW, 480 Cx 1286 kHz, 672 mV, 271 mW, 459 Cx 1401 kHz, 692 mV, 310 mW, 454 Cx 1536 kHz, 716 mV, 368 mW, 462 Cx 1651 kHz, 740 mV, 416 mW, 454 Cx 1785 kHz, 760 mV, 492 mW, 475 Cx 1920 kHz, 784 mV, 544 mW, 457 Cx 2054 kHz, 804 mV, 613 mW, 458 Cx 2188 kHz, 828 mV, 702 mW, 465 Cx 2323 kHz, 852 mV, 782 mW, 461 Cx 2457 kHz, 876 mV, 895 mW, 473 Cx 2592 kHz, 896 mV, 1020 mW, 490 Cx 2707 kHz, 920 mV, 1140 mW, 498 Cx 2803 kHz, 940 mV, 1215 mW, 490 Cx Your dynamic-power-coefficient for cpu 3: 472 Cortex-A710 cores: 614 kHz, 572 mV, 91 mW, 388 Cx 729 kHz, 592 mV, 116 mW, 424 Cx 844 kHz, 608 mV, 143 mW, 443 Cx 940 kHz, 624 mV, 165 mW, 434 Cx 1056 kHz, 644 mV, 195 mW, 430 Cx 1171 kHz, 656 mV, 218 mW, 414 Cx 1286 kHz, 672 mV, 250 mW, 415 Cx 1401 kHz, 692 mV, 286 mW, 412 Cx 1536 kHz, 716 mV, 331 mW, 407 Cx 1651 kHz, 740 mV, 374 mW, 401 Cx 1785 kHz, 760 mV, 439 mW, 417 Cx 1920 kHz, 784 mV, 495 mW, 411 Cx 2054 kHz, 804 mV, 557 mW, 412 Cx 2188 kHz, 828 mV, 632 mW, 415 Cx 2323 kHz, 852 mV, 721 mW, 422 Cx 2457 kHz, 876 mV, 813 mW, 427 Cx 2592 kHz, 896 mV, 912 mW, 435 Cx 2707 kHz, 920 mV, 1019 mW, 442 Cx 2803 kHz, 940 mV, 1087 mW, 436 Cx Your dynamic-power-coefficient for cpu 5: 421 Cortex-X3 core: 729 kHz, 568 mV, 252 mW, 1110 Cx 864 kHz, 580 mV, 312 mW, 1097 Cx 998 kHz, 592 mV, 379 mW, 1109 Cx 1132 kHz, 608 mV, 453 mW, 1099 Cx 1248 kHz, 624 mV, 517 mW, 1067 Cx 1363 kHz, 636 mV, 587 mW, 1067 Cx 1478 kHz, 648 mV, 657 mW, 1058 Cx 1593 kHz, 664 mV, 739 mW, 1049 Cx 1708 kHz, 680 mV, 813 mW, 1020 Cx 1843 kHz, 704 mV, 940 mW, 1021 Cx 1977 kHz, 724 mV, 1054 mW, 1007 Cx 2092 kHz, 740 mV, 1201 mW, 1045 Cx 2227 kHz, 768 mV, 1358 mW, 1029 Cx 2342 kHz, 788 mV, 1486 mW, 1016 Cx 2476 kHz, 812 mV, 1711 mW, 1046 Cx 2592 kHz, 836 mV, 1846 mW, 1014 Cx 2726 kHz, 856 mV, 2046 mW, 1020 Cx 2841 kHz, 880 mV, 2266 mW, 1027 Cx 2956 kHz, 908 mV, 2616 mW, 1074 Cx 3187 kHz, 956 mV, 3326 mW, 1147 Cx Your dynamic-power-coefficient for cpu 7: 1057 7-zip benchmark single-core MIPS: 2128 4416 4632 6686 Signed-off-by: Xilin Wu --- arch/arm64/boot/dts/qcom/sm8550.dtsi | 32 ++++++++++++++++---------------- 1 file changed, 16 insertions(+), 16 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sm8550.dtsi b/arch/arm64/boot/dts/qco= m/sm8550.dtsi index b8bbe88e770f..a84dd7f6ebc1 100644 --- a/arch/arm64/boot/dts/qcom/sm8550.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8550.dtsi @@ -79,8 +79,8 @@ CPU0: cpu@0 { power-domains =3D <&CPU_PD0>; power-domain-names =3D "psci"; qcom,freq-domain =3D <&cpufreq_hw 0>; - capacity-dmips-mhz =3D <1024>; - dynamic-power-coefficient =3D <100>; + capacity-dmips-mhz =3D <326>; + dynamic-power-coefficient =3D <251>; #cooling-cells =3D <2>; L2_0: l2-cache { compatible =3D "cache"; @@ -105,8 +105,8 @@ CPU1: cpu@100 { power-domains =3D <&CPU_PD1>; power-domain-names =3D "psci"; qcom,freq-domain =3D <&cpufreq_hw 0>; - capacity-dmips-mhz =3D <1024>; - dynamic-power-coefficient =3D <100>; + capacity-dmips-mhz =3D <326>; + dynamic-power-coefficient =3D <251>; #cooling-cells =3D <2>; L2_100: l2-cache { compatible =3D "cache"; @@ -126,8 +126,8 @@ CPU2: cpu@200 { power-domains =3D <&CPU_PD2>; power-domain-names =3D "psci"; qcom,freq-domain =3D <&cpufreq_hw 0>; - capacity-dmips-mhz =3D <1024>; - dynamic-power-coefficient =3D <100>; + capacity-dmips-mhz =3D <326>; + dynamic-power-coefficient =3D <251>; #cooling-cells =3D <2>; L2_200: l2-cache { compatible =3D "cache"; @@ -147,8 +147,8 @@ CPU3: cpu@300 { power-domains =3D <&CPU_PD3>; power-domain-names =3D "psci"; qcom,freq-domain =3D <&cpufreq_hw 1>; - capacity-dmips-mhz =3D <1792>; - dynamic-power-coefficient =3D <270>; + capacity-dmips-mhz =3D <693>; + dynamic-power-coefficient =3D <447>; #cooling-cells =3D <2>; L2_300: l2-cache { compatible =3D "cache"; @@ -168,8 +168,8 @@ CPU4: cpu@400 { power-domains =3D <&CPU_PD4>; power-domain-names =3D "psci"; qcom,freq-domain =3D <&cpufreq_hw 1>; - capacity-dmips-mhz =3D <1792>; - dynamic-power-coefficient =3D <270>; + capacity-dmips-mhz =3D <693>; + dynamic-power-coefficient =3D <447>; #cooling-cells =3D <2>; L2_400: l2-cache { compatible =3D "cache"; @@ -189,8 +189,8 @@ CPU5: cpu@500 { power-domains =3D <&CPU_PD5>; power-domain-names =3D "psci"; qcom,freq-domain =3D <&cpufreq_hw 1>; - capacity-dmips-mhz =3D <1792>; - dynamic-power-coefficient =3D <270>; + capacity-dmips-mhz =3D <693>; + dynamic-power-coefficient =3D <447>; #cooling-cells =3D <2>; L2_500: l2-cache { compatible =3D "cache"; @@ -210,8 +210,8 @@ CPU6: cpu@600 { power-domains =3D <&CPU_PD6>; power-domain-names =3D "psci"; qcom,freq-domain =3D <&cpufreq_hw 1>; - capacity-dmips-mhz =3D <1792>; - dynamic-power-coefficient =3D <270>; + capacity-dmips-mhz =3D <693>; + dynamic-power-coefficient =3D <447>; #cooling-cells =3D <2>; L2_600: l2-cache { compatible =3D "cache"; @@ -231,8 +231,8 @@ CPU7: cpu@700 { power-domains =3D <&CPU_PD7>; power-domain-names =3D "psci"; qcom,freq-domain =3D <&cpufreq_hw 2>; - capacity-dmips-mhz =3D <1894>; - dynamic-power-coefficient =3D <588>; + capacity-dmips-mhz =3D <1024>; + dynamic-power-coefficient =3D <1057>; #cooling-cells =3D <2>; L2_700: l2-cache { compatible =3D "cache"; --=20 2.44.0 From nobody Sat May 18 06:04:13 2024 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E3FB6160794; Wed, 24 Apr 2024 15:29:30 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; 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charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20240424-ayn-odin2-initial-v1-8-e0aa05c991fd@gmail.com> References: <20240424-ayn-odin2-initial-v1-0-e0aa05c991fd@gmail.com> In-Reply-To: <20240424-ayn-odin2-initial-v1-0-e0aa05c991fd@gmail.com> To: =?utf-8?q?Uwe_Kleine-K=C3=B6nig?= , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Junhao Xie , Neil Armstrong , Jessica Zhang , Sam Ravnborg , David Airlie , Daniel Vetter , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , Bjorn Andersson , Konrad Dybcio , Tengfei Fan , Molly Sophia , Junhao Xie Cc: linux-pwm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, linux-arm-msm@vger.kernel.org, Xilin Wu X-Mailer: b4 0.13.0 X-Developer-Signature: v=1; a=ed25519-sha256; t=1713972563; l=793; i=wuxilin123@gmail.com; s=20240424; h=from:subject:message-id; bh=Cm/VLCSCBA/wJ9+LOf+qf8btflRrlxYoe2807MqhRCQ=; b=yUgbXGvI3Ipr+IOpp0cr2Plxv3RuqFD9A60qsyDt6n2ukUILRwQAZjBJPAaIjhv4eJPpAoMyc W9vvOzXzZq6AVyqP9CiftwtVCfjavCdVlkMpLK+HR5iJ1T3VaEDyns3 X-Developer-Key: i=wuxilin123@gmail.com; a=ed25519; pk=vPnxeJnlD/PfEbyQPZzaay5ezxI/lMrke7qXy31lSM8= X-Endpoint-Received: by B4 Relay for wuxilin123@gmail.com/20240424 with auth_id=157 X-Original-From: Xilin Wu Reply-To: wuxilin123@gmail.com From: Xilin Wu Add an entry for AYN Technologies (https://www.ayntec.com/) Signed-off-by: Xilin Wu --- Documentation/devicetree/bindings/vendor-prefixes.yaml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/vendor-prefixes.yaml b/Docum= entation/devicetree/bindings/vendor-prefixes.yaml index e4aeeb5fe4d1..c2365b0f4184 100644 --- a/Documentation/devicetree/bindings/vendor-prefixes.yaml +++ b/Documentation/devicetree/bindings/vendor-prefixes.yaml @@ -194,6 +194,8 @@ patternProperties: description: Axentia Technologies AB "^axis,.*": description: Axis Communications AB + "^ayn,.*": + description: AYN Technologies Co., Ltd. "^azoteq,.*": description: Azoteq (Pty) Ltd "^azw,.*": --=20 2.44.0 From nobody Sat May 18 06:04:13 2024 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 0464A160873; Wed, 24 Apr 2024 15:29:30 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1713972571; cv=none; b=ZISuj3HeD3e3zX3Ji9rOBtlG96SgK37RoHI/1S8OvyDO/U5SmWwRZNyOuXLCBTvhDsPj5iSGGGJvSYYBwi9jHi3mtVATCLWFw4L9yDD39Dgztgeu/dgCkPwUlwU9ZrULp/AUkzImxlQ6Rgx1A2s0F8G6OlFKYqZdJPiPAs4/G2k= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1713972571; c=relaxed/simple; bh=GHuQ1HT+FCoEdjc3sTAOaE6jN4Sii4ShQFjHbxCz/4g=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=Vbi96qvTNOeFELpXNWQW0Vqph9HMP8aLoHaKVz5B7cFebO8UETO8uWmJdbS8qR9FwCJPkmHAAGk3b5JQEBlYHdl32Tjzc7aYJhPzZphm1/74AqJugOBI125qZeMEF2Fx/TWhYT0KE/0UoYiwhx34JjABRasOcO+yRG8FiAKPYnw= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=FQZYzapv; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="FQZYzapv" Received: by smtp.kernel.org (Postfix) with ESMTPS id AB173C4AF67; Wed, 24 Apr 2024 15:29:30 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1713972570; bh=GHuQ1HT+FCoEdjc3sTAOaE6jN4Sii4ShQFjHbxCz/4g=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=FQZYzapvKPsStieqUCu1gfkOJ3Hl63RXAFnRMHTtB3ebc+OmeGPVe7Y/CngvMGqal M49hFPk5N/CPqn+dzlnHP8aZWz3OcYqcvoee7gRWkk4idwNM55Do6xS9TTv9DaiCyT IoumS4hPT5gXpKOgdP1TjLHyXYVyFf29CsKmDZWfVLiEb7CFCZ70sHSjzGUhY+23Ic Ew97MMdfmAiTJe3GFumxmZ4oWCGa2637ImEGul2TspgxEub2InP8lPtKrLCgOLGcUb JShv/xwCtCZfCrpWYhdpXMkiBUf1cviouDhU9VW2Vglis+fkx62TaHqe9SXO5kCbW9 ZdfDIjV6d34Mg== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id A2681C4345F; Wed, 24 Apr 2024 15:29:30 +0000 (UTC) From: Xilin Wu via B4 Relay Date: Wed, 24 Apr 2024 23:29:14 +0800 Subject: [PATCH 09/10] dt-bindings: arm: qcom: Add AYN Odin 2 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20240424-ayn-odin2-initial-v1-9-e0aa05c991fd@gmail.com> References: <20240424-ayn-odin2-initial-v1-0-e0aa05c991fd@gmail.com> In-Reply-To: <20240424-ayn-odin2-initial-v1-0-e0aa05c991fd@gmail.com> To: =?utf-8?q?Uwe_Kleine-K=C3=B6nig?= , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Junhao Xie , Neil Armstrong , Jessica Zhang , Sam Ravnborg , David Airlie , Daniel Vetter , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , Bjorn Andersson , Konrad Dybcio , Tengfei Fan , Molly Sophia , Junhao Xie Cc: linux-pwm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, linux-arm-msm@vger.kernel.org, Xilin Wu X-Mailer: b4 0.13.0 X-Developer-Signature: v=1; a=ed25519-sha256; t=1713972563; l=733; i=wuxilin123@gmail.com; s=20240424; h=from:subject:message-id; bh=IWMEwTxqsDx0Pa+feRUvwg8F4G6cj6QTAKgbPe9K9dg=; b=iD8DU0abmJ2QjedN04FauD4gidVpA+VEmLsIeXWjq4WakuoBBDP8fgdmXR8tOuuCLrz2NnT7r 64ShVrCrXD7BVvnsjrEyKIz1oDbYkgB17nJGRA3pr/Nbocbh+33xUJm X-Developer-Key: i=wuxilin123@gmail.com; a=ed25519; pk=vPnxeJnlD/PfEbyQPZzaay5ezxI/lMrke7qXy31lSM8= X-Endpoint-Received: by B4 Relay for wuxilin123@gmail.com/20240424 with auth_id=157 X-Original-From: Xilin Wu Reply-To: wuxilin123@gmail.com From: Xilin Wu This documents AYN Odin 2 which is a gaming handheld by AYN based on the QCS8550 SoC. Signed-off-by: Xilin Wu --- Documentation/devicetree/bindings/arm/qcom.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/arm/qcom.yaml b/Documentatio= n/devicetree/bindings/arm/qcom.yaml index 090fc5fda9b0..8e991f2bd9d8 100644 --- a/Documentation/devicetree/bindings/arm/qcom.yaml +++ b/Documentation/devicetree/bindings/arm/qcom.yaml @@ -1003,6 +1003,7 @@ properties: =20 - items: - enum: + - ayn,odin2 - qcom,qcs8550-aim300-aiot - const: qcom,qcs8550-aim300 - const: qcom,qcs8550 --=20 2.44.0 From nobody Sat May 18 06:04:13 2024 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 2E39116133F; Wed, 24 Apr 2024 15:29:30 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1713972571; cv=none; b=NmxnKLr4UVG5SUPWv+MrfwNjLSOYBEdV6mAtSfZGnVGI/bk2AecCcYW9THMWXLjJlHZkc9Ftmo1pyy5B3RoWvN6lvSyKSSiNYRtzp9czaOnUWkp9svHS0Ad0sCvhkbx4ji6B7UbfkfNUzSPR1suq18XuW/10yZbG8yyK2k7rSDc= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1713972571; c=relaxed/simple; bh=wO1mlouIkGphlwZEnYXnwsuEldgA+TbsXDjNHC3vXbc=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=k8V+QDsKvPMM3oRVfjDypcA+TiRMdGWpOqRBMX+UDiZ6daG1FKVlk+4iEIHK1IRF3fxRPs5W1Me0DFe/dKmeqhPbUHYa5LXvuCRDuePTDFeWokzMm5EbK599eWYJbUzG+8pVhnAW8kJe3BOFswyzUKk6IZ8ReqL2/9WfSpZQQOw= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=IZrH0XCb; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="IZrH0XCb" Received: by smtp.kernel.org (Postfix) with ESMTPS id C0729C4AF64; Wed, 24 Apr 2024 15:29:30 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1713972570; bh=wO1mlouIkGphlwZEnYXnwsuEldgA+TbsXDjNHC3vXbc=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=IZrH0XCbpYhHiUQqnaB/pmznMUu3mDyUBF/iIVh9m/I/sCVSeO14wRSLa8xJf2VBC ObKNShjtBOvQvxAgA/G7esfXc0zWItW+anrRyndwqbDAFpZFjq1a+jC3lOGg+qC1Cc 1cYWsSsrVpTJwO51LTOrN9fQYd04gX9Zej8rUl5Ud81y6vtTXxB3Rvl40TcxttWu7u 5yj+SpteBgO/aLI5mEHaZFc7lRJhsgEFf+jKlxgss4Sxa+BXX1lDtAGa45RrfHPQiK zmNBhE+Fe0Kv5DoE+wj6SRLa+fULfWXK/xHG23Xlsq7e1rmDKCQSKD5SaeC3tLtlM3 DSEOoVEUkJ4/g== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id B88CEC07E8E; Wed, 24 Apr 2024 15:29:30 +0000 (UTC) From: Xilin Wu via B4 Relay Date: Wed, 24 Apr 2024 23:29:15 +0800 Subject: [PATCH 10/10] arm64: dts: qcom: Add AYN Odin 2 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20240424-ayn-odin2-initial-v1-10-e0aa05c991fd@gmail.com> References: <20240424-ayn-odin2-initial-v1-0-e0aa05c991fd@gmail.com> In-Reply-To: <20240424-ayn-odin2-initial-v1-0-e0aa05c991fd@gmail.com> To: =?utf-8?q?Uwe_Kleine-K=C3=B6nig?= , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Junhao Xie , Neil Armstrong , Jessica Zhang , Sam Ravnborg , David Airlie , Daniel Vetter , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , Bjorn Andersson , Konrad Dybcio , Tengfei Fan , Molly Sophia , Junhao Xie Cc: linux-pwm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, linux-arm-msm@vger.kernel.org, Xilin Wu X-Mailer: b4 0.13.0 X-Developer-Signature: v=1; a=ed25519-sha256; t=1713972563; l=34888; i=wuxilin123@gmail.com; s=20240424; h=from:subject:message-id; bh=5jhsQku4cVI7cM86CfiA0phdO7isJxAGMe4tWG1ivmw=; b=ub7i4HAtTGxx4iWn9joPzgCUOnOL7MkU4T653B1J6/armSE3Ti5qEXuw2Cjzt/sTOyJU4pXy1 MX28jRaTYwgDD2OkY3UJlMwR93MugtcQIYbWnzcS1iuS7G+6zF0F24G X-Developer-Key: i=wuxilin123@gmail.com; a=ed25519; pk=vPnxeJnlD/PfEbyQPZzaay5ezxI/lMrke7qXy31lSM8= X-Endpoint-Received: by B4 Relay for wuxilin123@gmail.com/20240424 with auth_id=157 X-Original-From: Xilin Wu Reply-To: wuxilin123@gmail.com From: Xilin Wu AYN Odin 2 is a gaming handheld based on QCS8550, which is derived from SM8550 but without modem RF system. This commit brings support for: * Remoteprocs * UFS storage * SD Card * Type-C with USB3 10Gbps and DisplayPort (4-lane requires a pending patch) * PCIe0 (Wi-Fi requires the pending pwrseq series) * Bluetooth * Regulators * Integrated fan with automatic speed control based on CPU temperature * Power and volume keys * M1, M2 buttons * HDMI output up to 1080p 60hz * four groups of RGB lights * GPU * Internal DSI display with touchscreen Signed-off-by: Xilin Wu --- arch/arm64/boot/dts/qcom/Makefile | 1 + arch/arm64/boot/dts/qcom/qcs8550-ayn-odin2.dts | 1410 ++++++++++++++++++++= ++++ 2 files changed, 1411 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/M= akefile index c46c10d85697..070c0d996059 100644 --- a/arch/arm64/boot/dts/qcom/Makefile +++ b/arch/arm64/boot/dts/qcom/Makefile @@ -97,6 +97,7 @@ dtb-$(CONFIG_ARCH_QCOM) +=3D qcs404-evb-1000.dtb dtb-$(CONFIG_ARCH_QCOM) +=3D qcs404-evb-4000.dtb dtb-$(CONFIG_ARCH_QCOM) +=3D qcs6490-rb3gen2.dtb dtb-$(CONFIG_ARCH_QCOM) +=3D qcs8550-aim300-aiot.dtb +dtb-$(CONFIG_ARCH_QCOM) +=3D qcs8550-ayn-odin2.dtb dtb-$(CONFIG_ARCH_QCOM) +=3D qdu1000-idp.dtb dtb-$(CONFIG_ARCH_QCOM) +=3D qrb2210-rb1.dtb dtb-$(CONFIG_ARCH_QCOM) +=3D qrb4210-rb2.dtb diff --git a/arch/arm64/boot/dts/qcom/qcs8550-ayn-odin2.dts b/arch/arm64/bo= ot/dts/qcom/qcs8550-ayn-odin2.dts new file mode 100644 index 000000000000..bfe353d3c53e --- /dev/null +++ b/arch/arm64/boot/dts/qcom/qcs8550-ayn-odin2.dts @@ -0,0 +1,1410 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024, Xilin Wu + */ + +/dts-v1/; + +#include +#include +#include +#include "qcs8550.dtsi" +#include "pm8550.dtsi" +#include "pm8550b.dtsi" +#define PMK8550VE_SID 5 +#include "pm8550ve.dtsi" +#include "pm8550vs.dtsi" +#include "pmk8550.dtsi" + +/* + * The SoC being used on this product doesn't feature modem + * and camera subsystem. + * Variant: 202-AB + * FEATURE_ID: 0x8 + */ + +/delete-node/ &mpss_mem; +/delete-node/ &q6_mpss_dtb_mem; +/delete-node/ &ipa_fw_mem; +/delete-node/ &ipa_gsi_mem; +/delete-node/ &camera_mem; +/delete-node/ &mpss_dsm_mem; +/delete-node/ &camcc; +/delete-node/ &remoteproc_mpss; + +/ { + model =3D "AYN Odin 2"; + compatible =3D "ayn,odin2", "qcom,qcs8550", "qcom,sm8550"; + chassis-type =3D "handset"; + + qcom,msm-id =3D ; + qcom,board-id =3D <0x1001f 0>; + + aliases { + serial0 =3D &uart7; + serial1 =3D &uart14; + serial2 =3D &uart15; + }; + + backlight: backlight { + compatible =3D "pwm-backlight"; + pwms =3D <&pmk8550_pwm 0 860000>; + brightness-levels =3D <1023 0>; + num-interpolated-steps =3D <1023>; + default-brightness-level =3D <600>; + power-supply =3D <&vph_pwr>; + enable-gpios =3D <&pmk8550_gpios 5 GPIO_ACTIVE_HIGH>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pwm_backlight_default>; + status =3D "okay"; + }; + + fan_pwr: fan-pwr-regulator { + compatible =3D "regulator-fixed"; + regulator-name =3D "fan_pwr"; + + regulator-min-microvolt =3D <5000000>; + regulator-max-microvolt =3D <5000000>; + + gpio =3D <&tlmm 109 GPIO_ACTIVE_HIGH>; + enable-active-high; + + pinctrl-names =3D "default"; + pinctrl-0 =3D <&fan_pwr_en>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + gpio-keys { + compatible =3D "gpio-keys"; + + pinctrl-0 =3D <&volume_up_n>, <&m1_m2_keys_default>; + pinctrl-names =3D "default"; + + key-volume-up { + label =3D "Volume Up"; + linux,code =3D ; + gpios =3D <&pm8550_gpios 6 GPIO_ACTIVE_LOW>; + debounce-interval =3D <15>; + linux,can-disable; + wakeup-source; + }; + + m1-button { + label =3D "M1"; + linux,code =3D ; + gpios =3D <&tlmm 57 GPIO_ACTIVE_LOW>; + }; + + m2-button { + label =3D "M2"; + linux,code =3D ; + gpios =3D <&tlmm 58 GPIO_ACTIVE_LOW>; + }; + }; + + hdmi-out { + compatible =3D "hdmi-connector"; + type =3D "d"; + hpd-gpios =3D <&tlmm 9 GPIO_ACTIVE_HIGH>; + + port { + hdmi_con: endpoint { + remote-endpoint =3D <<8912_out>; + }; + }; + }; + + hdmi_pwr: hdmi-pwr-regulator { + compatible =3D "regulator-fixed"; + regulator-name =3D "hdmi_pwr"; + + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + + gpio =3D <&tlmm 10 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + vdd_lcm_2p8: vdd-lcm-2p8-regulator { + compatible =3D "regulator-fixed"; + regulator-name =3D "vdd_lcm_2p8"; + + regulator-min-microvolt =3D <2800000>; + regulator-max-microvolt =3D <2800000>; + + gpio =3D <&tlmm 142 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + led_left_side: led-controller-1 { + compatible =3D "pwm-leds-multicolor"; + + multi-led { + label =3D "left-side"; + color =3D ; + max-brightness =3D <255>; + + led-red { + color =3D ; + pwms =3D <&pwm_rgb_left 0>; + }; + + led-green { + color =3D ; + pwms =3D <&pwm_rgb_left 1>; + }; + + led-blue { + color =3D ; + pwms =3D <&pwm_rgb_left 2>; + }; + }; + }; + + led_left_joystick: led-controller-2 { + compatible =3D "pwm-leds-multicolor"; + + multi-led { + label =3D "left-joystick"; + color =3D ; + max-brightness =3D <255>; + + led-red { + color =3D ; + pwms =3D <&pwm_rgb_left 6>; + }; + + led-green { + color =3D ; + pwms =3D <&pwm_rgb_left 7>; + }; + + led-blue { + color =3D ; + pwms =3D <&pwm_rgb_left 8>; + }; + }; + }; + + led_right_side: led-controller-3 { + compatible =3D "pwm-leds-multicolor"; + + multi-led { + label =3D "right-side"; + color =3D ; + max-brightness =3D <255>; + + led-red { + color =3D ; + pwms =3D <&pwm_rgb_right 0>; + }; + + led-green { + color =3D ; + pwms =3D <&pwm_rgb_right 1>; + }; + + led-blue { + color =3D ; + pwms =3D <&pwm_rgb_right 2>; + }; + }; + }; + + led_right_joystick: led-controller-4 { + compatible =3D "pwm-leds-multicolor"; + + multi-led { + label =3D "right-joystick"; + color =3D ; + max-brightness =3D <255>; + + led-red { + color =3D ; + pwms =3D <&pwm_rgb_right 6>; + }; + + led-green { + color =3D ; + pwms =3D <&pwm_rgb_right 7>; + }; + + led-blue { + color =3D ; + pwms =3D <&pwm_rgb_right 8>; + }; + }; + }; + + mcu_3v3: mcu-3v3-regulator { + compatible =3D "regulator-fixed"; + regulator-name =3D "mcu_3v3"; + + regulator-min-microvolt =3D <3300000>; + regulator-max-microvolt =3D <3300000>; + + gpio =3D <&tlmm 99 GPIO_ACTIVE_HIGH>; + regulator-always-on; + regulator-boot-on; + enable-active-high; + }; + + pmic-glink { + compatible =3D "qcom,sm8550-pmic-glink", "qcom,pmic-glink"; + #address-cells =3D <1>; + #size-cells =3D <0>; + orientation-gpios =3D <&tlmm 11 GPIO_ACTIVE_HIGH>; + + connector@0 { + compatible =3D "usb-c-connector"; + reg =3D <0>; + power-role =3D "dual"; + data-role =3D "dual"; + + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@0 { + reg =3D <0>; + + pmic_glink_hs_in: endpoint { + remote-endpoint =3D <&usb_1_dwc3_hs>; + }; + }; + + port@1 { + reg =3D <1>; + + pmic_glink_ss_in: endpoint { + remote-endpoint =3D <&usb_dp_qmpphy_out>; + }; + }; + + port@2 { + reg =3D <2>; + + pmic_glink_sbu: endpoint { + remote-endpoint =3D <&usb0_sbu_mux>; + }; + }; + }; + }; + }; + + fan: pwm-fan { + compatible =3D "pwm-fan"; + cooling-levels =3D <0 40 65 75 90 100 120 150>; + #cooling-cells =3D <2>; + fan-supply =3D <&fan_pwr>; + pwms =3D <&pm8550_pwm 3 100000>; + + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pwm_out_default &fan_int>; + + pulses-per-revolution =3D <4>; + interrupt-parent =3D <&tlmm>; + interrupts =3D <13 IRQ_TYPE_EDGE_FALLING>; + }; + + thermal-zones { + cpuss0-thermal { + trips { + cpuss0_active0: trip-point2 { + temperature =3D <50000>; + hysteresis =3D <4000>; + type =3D "active"; + }; + + cpuss0_active1: trip-point3 { + temperature =3D <55000>; + hysteresis =3D <4000>; + type =3D "active"; + }; + + cpuss0_active2: trip-point4 { + temperature =3D <60000>; + hysteresis =3D <4000>; + type =3D "active"; + }; + + cpuss0_active3: trip-point5 { + temperature =3D <65000>; + hysteresis =3D <4000>; + type =3D "active"; + }; + + cpuss0_active4: trip-point6 { + temperature =3D <70000>; + hysteresis =3D <4000>; + type =3D "active"; + }; + + cpuss0_active5: trip-point7 { + temperature =3D <75000>; + hysteresis =3D <4000>; + type =3D "active"; + }; + + cpuss0_active6: trip-point8 { + temperature =3D <80000>; + hysteresis =3D <4000>; + type =3D "active"; + }; + }; + + cooling-maps { + map0 { + trip =3D <&cpuss0_active0>; + cooling-device =3D <&fan 0 1>; + }; + map1 { + trip =3D <&cpuss0_active1>; + cooling-device =3D <&fan 1 2>; + }; + map2 { + trip =3D <&cpuss0_active2>; + cooling-device =3D <&fan 2 3>; + }; + map3 { + trip =3D <&cpuss0_active3>; + cooling-device =3D <&fan 3 4>; + }; + map4 { + trip =3D <&cpuss0_active4>; + cooling-device =3D <&fan 4 5>; + }; + map5 { + trip =3D <&cpuss0_active5>; + cooling-device =3D <&fan 5 6>; + }; + map6 { + trip =3D <&cpuss0_active6>; + cooling-device =3D <&fan 6 7>; + }; + }; + }; + }; + + usb0-sbu-mux { + compatible =3D "pericom,pi3usb102", "gpio-sbu-mux"; + + enable-gpios =3D <&tlmm 140 GPIO_ACTIVE_LOW>; + select-gpios =3D <&tlmm 141 GPIO_ACTIVE_HIGH>; + + pinctrl-names =3D "default"; + pinctrl-0 =3D <&usb0_sbu_default>; + + mode-switch; + orientation-switch; + + port { + usb0_sbu_mux: endpoint { + remote-endpoint =3D <&pmic_glink_sbu>; + }; + }; + }; + + vph_pwr: vph-pwr-regulator { + compatible =3D "regulator-fixed"; + regulator-name =3D "vph_pwr"; + regulator-min-microvolt =3D <3700000>; + regulator-max-microvolt =3D <3700000>; + + regulator-always-on; + regulator-boot-on; + }; +}; + +&apps_rsc { + regulators-0 { + compatible =3D "qcom,pm8550-rpmh-regulators"; + qcom,pmic-id =3D "b"; + + vdd-bob1-supply =3D <&vph_pwr>; + vdd-bob2-supply =3D <&vph_pwr>; + vdd-l1-l4-l10-supply =3D <&vreg_s6g_1p86>; + vdd-l2-l13-l14-supply =3D <&vreg_bob1>; + vdd-l3-supply =3D <&vreg_s4g_1p25>; + vdd-l5-l16-supply =3D <&vreg_bob1>; + vdd-l6-l7-supply =3D <&vreg_bob1>; + vdd-l8-l9-supply =3D <&vreg_bob1>; + vdd-l11-supply =3D <&vreg_s4g_1p25>; + vdd-l12-supply =3D <&vreg_s6g_1p86>; + vdd-l15-supply =3D <&vreg_s6g_1p86>; + vdd-l17-supply =3D <&vreg_bob2>; + + vreg_bob1: bob1 { + regulator-name =3D "vreg_bob1"; + regulator-min-microvolt =3D <3296000>; + regulator-max-microvolt =3D <3960000>; + regulator-initial-mode =3D ; + }; + + vreg_bob2: bob2 { + regulator-name =3D "vreg_bob2"; + regulator-min-microvolt =3D <2720000>; + regulator-max-microvolt =3D <3960000>; + regulator-initial-mode =3D ; + }; + + vreg_l1b_1p8: ldo1 { + regulator-name =3D "vreg_l1b_1p8"; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + regulator-initial-mode =3D ; + regulator-allow-set-load; + regulator-allowed-modes =3D ; + }; + + vreg_l2b_3p0: ldo2 { + regulator-name =3D "vreg_l2b_3p0"; + regulator-min-microvolt =3D <3008000>; + regulator-max-microvolt =3D <3008000>; + regulator-initial-mode =3D ; + regulator-allow-set-load; + regulator-allowed-modes =3D ; + }; + + vreg_l5b_3p1: ldo5 { + regulator-name =3D "vreg_l5b_3p1"; + regulator-min-microvolt =3D <3104000>; + regulator-max-microvolt =3D <3104000>; + regulator-initial-mode =3D ; + regulator-allow-set-load; + regulator-allowed-modes =3D ; + }; + + vreg_l6b_1p8: ldo6 { + regulator-name =3D "vreg_l6b_1p8"; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <3008000>; + regulator-initial-mode =3D ; + regulator-allow-set-load; + regulator-allowed-modes =3D ; + }; + + vreg_l7b_1p8: ldo7 { + regulator-name =3D "vreg_l7b_1p8"; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <3008000>; + regulator-initial-mode =3D ; + regulator-allow-set-load; + regulator-allowed-modes =3D ; + }; + + vreg_l8b_1p8: ldo8 { + regulator-name =3D "vreg_l8b_1p8"; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <3008000>; + regulator-initial-mode =3D ; + regulator-allow-set-load; + regulator-allowed-modes =3D ; + }; + + vreg_l9b_2p9: ldo9 { + regulator-name =3D "vreg_l9b_2p9"; + regulator-min-microvolt =3D <2960000>; + regulator-max-microvolt =3D <3008000>; + regulator-initial-mode =3D ; + regulator-allow-set-load; + regulator-allowed-modes =3D ; + }; + + vreg_l10b_1p8: ldo10 { + regulator-name =3D "vreg_l10b_1p8"; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + regulator-initial-mode =3D ; + regulator-allow-set-load; + regulator-allowed-modes =3D ; + }; + + vreg_l11b_1p2: ldo11 { + regulator-name =3D "vreg_l11b_1p2"; + regulator-min-microvolt =3D <1200000>; + regulator-max-microvolt =3D <1504000>; + regulator-initial-mode =3D ; + regulator-allow-set-load; + regulator-allowed-modes =3D ; + }; + + vreg_l12b_1p8: ldo12 { + regulator-name =3D "vreg_l12b_1p8"; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + regulator-initial-mode =3D ; + regulator-allow-set-load; + regulator-allowed-modes =3D ; + }; + + vreg_l13b_3p0: ldo13 { + regulator-name =3D "vreg_l13b_3p0"; + regulator-min-microvolt =3D <3000000>; + regulator-max-microvolt =3D <3000000>; + regulator-initial-mode =3D ; + regulator-allow-set-load; + regulator-allowed-modes =3D ; + }; + + vreg_l14b_3p2: ldo14 { + regulator-name =3D "vreg_l14b_3p2"; + regulator-min-microvolt =3D <3200000>; + regulator-max-microvolt =3D <3200000>; + regulator-initial-mode =3D ; + regulator-allow-set-load; + regulator-allowed-modes =3D ; + }; + + vreg_l15b_1p8: ldo15 { + regulator-name =3D "vreg_l15b_1p8"; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + regulator-initial-mode =3D ; + regulator-allow-set-load; + regulator-allowed-modes =3D ; + }; + + vreg_l16b_2p8: ldo16 { + regulator-name =3D "vreg_l16b_2p8"; + regulator-min-microvolt =3D <2800000>; + regulator-max-microvolt =3D <2800000>; + regulator-initial-mode =3D ; + regulator-allow-set-load; + regulator-allowed-modes =3D ; + }; + + /* Setting regulator-allow-set-load here will crash the device */ + vreg_l17b_2p5: ldo17 { + regulator-name =3D "vreg_l17b_2p5"; + regulator-min-microvolt =3D <2504000>; + regulator-max-microvolt =3D <2504000>; + regulator-initial-mode =3D ; + }; + }; + + regulators-1 { + compatible =3D "qcom,pm8550vs-rpmh-regulators"; + qcom,pmic-id =3D "c"; + + vdd-l1-supply =3D <&vreg_s4g_1p25>; + vdd-l2-supply =3D <&vreg_s4e_0p95>; + vdd-l3-supply =3D <&vreg_s4e_0p95>; + + vreg_l1c_1p2: ldo1 { + regulator-name =3D "vreg_l1c_1p2"; + regulator-min-microvolt =3D <1200000>; + regulator-max-microvolt =3D <1200000>; + regulator-initial-mode =3D ; + regulator-allow-set-load; + regulator-allowed-modes =3D ; + }; + + vreg_l3c_0p9: ldo3 { + regulator-name =3D "vreg_l3c_0p9"; + regulator-min-microvolt =3D <880000>; + regulator-max-microvolt =3D <912000>; + regulator-initial-mode =3D ; + regulator-allow-set-load; + regulator-allowed-modes =3D ; + }; + }; + + regulators-2 { + compatible =3D "qcom,pm8550vs-rpmh-regulators"; + qcom,pmic-id =3D "d"; + + vdd-l1-supply =3D <&vreg_s4e_0p95>; + vdd-l2-supply =3D <&vreg_s4e_0p95>; + vdd-l3-supply =3D <&vreg_s4e_0p95>; + + vreg_l1d_0p88: ldo1 { + regulator-name =3D "vreg_l1d_0p88"; + regulator-min-microvolt =3D <880000>; + regulator-max-microvolt =3D <920000>; + regulator-initial-mode =3D ; + regulator-allow-set-load; + regulator-allowed-modes =3D ; + }; + + /* ldo2 supplies SM8550 VDD_LPI_MX */ + }; + + regulators-3 { + compatible =3D "qcom,pm8550vs-rpmh-regulators"; + qcom,pmic-id =3D "e"; + + vdd-l1-supply =3D <&vreg_s4e_0p95>; + vdd-l2-supply =3D <&vreg_s4e_0p95>; + vdd-l3-supply =3D <&vreg_s4g_1p25>; + vdd-s4-supply =3D <&vph_pwr>; + vdd-s5-supply =3D <&vph_pwr>; + + vreg_s4e_0p95: smps4 { + regulator-name =3D "vreg_s4e_0p95"; + regulator-min-microvolt =3D <904000>; + regulator-max-microvolt =3D <984000>; + regulator-initial-mode =3D ; + }; + + vreg_s5e_1p08: smps5 { + regulator-name =3D "vreg_s5e_1p08"; + regulator-min-microvolt =3D <1010000>; + regulator-max-microvolt =3D <1120000>; + regulator-initial-mode =3D ; + }; + + vreg_l1e_0p88: ldo1 { + regulator-name =3D "vreg_l1e_0p88"; + regulator-min-microvolt =3D <880000>; + regulator-max-microvolt =3D <912000>; + regulator-initial-mode =3D ; + regulator-allow-set-load; + regulator-allowed-modes =3D ; + }; + + vreg_l2e_0p9: ldo2 { + regulator-name =3D "vreg_l2e_0p9"; + regulator-min-microvolt =3D <870000>; + regulator-max-microvolt =3D <970000>; + regulator-initial-mode =3D ; + regulator-allow-set-load; + regulator-allowed-modes =3D ; + }; + + vreg_l3e_1p2: ldo3 { + regulator-name =3D "vreg_l3e_1p2"; + regulator-min-microvolt =3D <1200000>; + regulator-max-microvolt =3D <1200000>; + regulator-initial-mode =3D ; + regulator-allow-set-load; + regulator-allowed-modes =3D ; + }; + }; + + regulators-4 { + compatible =3D "qcom,pm8550ve-rpmh-regulators"; + qcom,pmic-id =3D "f"; + + vdd-l1-supply =3D <&vreg_s4e_0p95>; + vdd-l2-supply =3D <&vreg_s4e_0p95>; + vdd-l3-supply =3D <&vreg_s4e_0p95>; + vdd-s4-supply =3D <&vph_pwr>; + + vreg_s4f_0p5: smps4 { + regulator-name =3D "vreg_s4f_0p5"; + regulator-min-microvolt =3D <300000>; + regulator-max-microvolt =3D <700000>; + regulator-initial-mode =3D ; + }; + + vreg_l1f_0p9: ldo1 { + regulator-name =3D "vreg_l1f_0p9"; + regulator-min-microvolt =3D <880000>; + regulator-max-microvolt =3D <912000>; + regulator-initial-mode =3D ; + regulator-allow-set-load; + regulator-allowed-modes =3D ; + }; + + vreg_l2f_0p88: ldo2 { + regulator-name =3D "vreg_l2f_0p88"; + regulator-min-microvolt =3D <880000>; + regulator-max-microvolt =3D <912000>; + regulator-initial-mode =3D ; + regulator-allow-set-load; + regulator-allowed-modes =3D ; + }; + + vreg_l3f_0p88: ldo3 { + regulator-name =3D "vreg_l3f_0p88"; + regulator-min-microvolt =3D <880000>; + regulator-max-microvolt =3D <912000>; + regulator-initial-mode =3D ; + regulator-allow-set-load; + regulator-allowed-modes =3D ; + }; + }; + + regulators-5 { + compatible =3D "qcom,pm8550vs-rpmh-regulators"; + qcom,pmic-id =3D "g"; + + vdd-l1-supply =3D <&vreg_s4g_1p25>; + vdd-l2-supply =3D <&vreg_s4g_1p25>; + vdd-l3-supply =3D <&vreg_s4g_1p25>; + vdd-s1-supply =3D <&vph_pwr>; + vdd-s2-supply =3D <&vph_pwr>; + vdd-s3-supply =3D <&vph_pwr>; + vdd-s4-supply =3D <&vph_pwr>; + vdd-s5-supply =3D <&vph_pwr>; + vdd-s6-supply =3D <&vph_pwr>; + + vreg_s1g_1p25: smps1 { + regulator-name =3D "vreg_s1g_1p25"; + regulator-min-microvolt =3D <1200000>; + regulator-max-microvolt =3D <1300000>; + regulator-initial-mode =3D ; + }; + + vreg_s2g_0p85: smps2 { + regulator-name =3D "vreg_s2g_0p85"; + regulator-min-microvolt =3D <500000>; + regulator-max-microvolt =3D <1036000>; + regulator-initial-mode =3D ; + }; + + vreg_s3g_0p8: smps3 { + regulator-name =3D "vreg_s3g_0p8"; + regulator-min-microvolt =3D <300000>; + regulator-max-microvolt =3D <1004000>; + regulator-initial-mode =3D ; + }; + + vreg_s4g_1p25: smps4 { + regulator-name =3D "vreg_s4g_1p25"; + regulator-min-microvolt =3D <1200000>; + regulator-max-microvolt =3D <1352000>; + regulator-initial-mode =3D ; + }; + + vreg_s5g_0p85: smps5 { + regulator-name =3D "vreg_s5g_0p85"; + regulator-min-microvolt =3D <500000>; + regulator-max-microvolt =3D <1004000>; + regulator-initial-mode =3D ; + }; + + vreg_s6g_1p86: smps6 { + regulator-name =3D "vreg_s6g_1p86"; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <2000000>; + regulator-initial-mode =3D ; + }; + + vreg_l1g_1p2: ldo1 { + regulator-name =3D "vreg_l1g_1p2"; + regulator-min-microvolt =3D <1144000>; + regulator-max-microvolt =3D <1256000>; + regulator-initial-mode =3D ; + regulator-allow-set-load; + regulator-allowed-modes =3D ; + }; + + vreg_l2g_1p1: ldo2 { + regulator-name =3D "vreg_l2g_1p1"; + regulator-min-microvolt =3D <1100000>; + regulator-max-microvolt =3D <1200000>; + regulator-initial-mode =3D ; + regulator-allow-set-load; + regulator-allowed-modes =3D ; + }; + + vreg_l3g_1p2: ldo3 { + regulator-name =3D "vreg_l3g_1p2"; + regulator-min-microvolt =3D <1200000>; + regulator-max-microvolt =3D <1200000>; + regulator-initial-mode =3D ; + regulator-allow-set-load; + regulator-allowed-modes =3D ; + }; + }; +}; + +&gpi_dma1 { + status =3D "okay"; +}; + +&gpi_dma2 { + status =3D "okay"; +}; + +&gpu { + status =3D "okay"; + + zap-shader { + firmware-name =3D "qcom/sm8550/ayn/odin2/a740_zap.mbn"; + }; +}; + +&hub_i2c0_data_clk { + /delete-property/ bias-pull-up; + bias-disable; +}; + +&i2c0 { + clock-frequency =3D <400000>; + status =3D "okay"; + + pwm_rgb_left: pwm@54 { + compatible =3D "si-en,sn3112-pwm"; + reg =3D <0x54>; + sdb-gpios =3D <&tlmm 55 GPIO_ACTIVE_LOW>; + vdd-supply =3D <&mcu_3v3>; + #pwm-cells =3D <1>; + }; +}; + +&i2c4 { + clock-frequency =3D <400000>; + status =3D "okay"; + + touchscreen@20 { + compatible =3D "syna,rmi4-i2c"; + reg =3D <0x20>; + #address-cells =3D <1>; + #size-cells =3D <0>; + interrupts-extended =3D <&tlmm 25 0x2008>; + + pinctrl-names =3D "default", "sleep"; + pinctrl-0 =3D <&ts_int_default>; + pinctrl-1 =3D <&ts_int_sleep>; + + vio-supply =3D <&vreg_l12b_1p8>; + + syna,startup-delay-ms =3D <200>; + syna,reset-delay-ms =3D <200>; + + rmi4-f01@1 { + syna,nosleep-mode =3D <0x1>; + reg =3D <0x1>; + }; + + rmi4-f12@12 { + reg =3D <0x12>; + syna,rezero-wait-ms =3D <20>; + syna,clip-x-low =3D <0>; + syna,clip-y-low =3D <0>; + syna,clip-x-high =3D <1080>; + syna,clip-y-high =3D <1920>; + syna,sensor-type =3D <1>; + touchscreen-inverted-x; + }; + }; +}; + +&i2c12 { + clock-frequency =3D <400000>; + status =3D "okay"; + + pwm_rgb_right: pwm@54 { + compatible =3D "si-en,sn3112-pwm"; + reg =3D <0x54>; + sdb-gpios =3D <&tlmm 56 GPIO_ACTIVE_LOW>; + vdd-supply =3D <&mcu_3v3>; + #pwm-cells =3D <1>; + }; +}; + +&i2c_master_hub_0 { + status =3D "okay"; +}; + +&i2c_hub_0 { + clock-frequency =3D <100000>; + status =3D "okay"; + + hdmi-bridge@48 { + compatible =3D "lontium,lt8912b"; + reg =3D <0x48> ; + reset-gpios =3D <&tlmm 7 GPIO_ACTIVE_LOW>; + + vdd-supply =3D <&hdmi_pwr>; + vccmipirx-supply =3D <&hdmi_pwr>; + vccsysclk-supply =3D <&hdmi_pwr>; + vcclvdstx-supply =3D <&hdmi_pwr>; + vcchdmitx-supply =3D <&hdmi_pwr>; + vcclvdspll-supply =3D <&hdmi_pwr>; + vcchdmipll-supply =3D <&hdmi_pwr>; + + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@0 { + reg =3D <0>; + + hdmi_out_in: endpoint { + data-lanes =3D <1 2 3 4>; + remote-endpoint =3D <&mdss_dsi0_out>; + }; + }; + + port@1 { + reg =3D <1>; + + lt8912_out: endpoint { + remote-endpoint =3D <&hdmi_con>; + }; + }; + }; + }; +}; + +&i2c_hub_2 { + status =3D "okay"; + + /* Awinic AW88166 audio amplifier @ 34, 35 */ +}; + +&mdss { + status =3D "okay"; +}; + +&mdss_dp0 { + status =3D "okay"; +}; + +&mdss_dp0_out { + remote-endpoint =3D <&usb_dp_qmpphy_dp_in>; + link-frequencies =3D /bits/ 64 <1620000000 2700000000 5400000000 81000000= 00>; +}; + +&mdss_dsi0 { + vdda-supply =3D <&vreg_l3e_1p2>; + status =3D "okay"; +}; + +&mdss_dsi0_out { + remote-endpoint =3D <&hdmi_out_in>; + data-lanes =3D <0 1 2 3>; +}; + +&mdss_dsi0_phy { + vdds-supply =3D <&vreg_l1e_0p88>; + status =3D "okay"; +}; + +&mdss_dsi1 { + vdda-supply =3D <&vreg_l3e_1p2>; + status =3D "okay"; + + panel: panel@0 { + compatible =3D "syna,td4328"; + reg =3D <0>; + + pinctrl-0 =3D <&sde_dsi_active>, <&sde_te_active>; + pinctrl-1 =3D <&sde_dsi_suspend>, <&sde_te_suspend>; + pinctrl-names =3D "default", "sleep"; + + vdd-supply =3D <&vdd_lcm_2p8>; + vddio-supply =3D <&vreg_l12b_1p8>; + + backlight =3D <&backlight>; + /* touchscreen and display panel share the same reset gpio! */ + reset-gpios =3D <&tlmm 133 GPIO_ACTIVE_LOW>; + + port { + panel0_in: endpoint { + remote-endpoint =3D <&mdss_dsi1_out>; + }; + }; + }; +}; + +&mdss_dsi1_out { + remote-endpoint =3D <&panel0_in>; + data-lanes =3D <0 1 2 3>; +}; + +&mdss_dsi1_phy { + vdds-supply =3D <&vreg_l1e_0p88>; + status =3D "okay"; +}; + +&pcie0 { + wake-gpios =3D <&tlmm 96 GPIO_ACTIVE_HIGH>; + perst-gpios =3D <&tlmm 94 GPIO_ACTIVE_LOW>; + + max-link-speed =3D <2>; + + pinctrl-0 =3D <&pcie0_default_state>; + pinctrl-names =3D "default"; + + status =3D "okay"; +}; + +&pcie0_phy { + vdda-phy-supply =3D <&vreg_l1e_0p88>; + vdda-pll-supply =3D <&vreg_l3e_1p2>; + + status =3D "okay"; +}; + +&pm8550_gpios { + pwm_out_default: pwm-out-default-state { + pins =3D "gpio8"; + function =3D "func1"; + input-disable; + output-enable; + output-low; + bias-disable; + power-source =3D <1>; + }; + + sdc2_card_det_n: sdc2-card-det-state { + pins =3D "gpio12"; + function =3D "normal"; + input-enable; + output-disable; + bias-pull-up; + power-source =3D <1>; /* 1.8 V */ + }; + + volume_up_n: volume-up-n-state { + pins =3D "gpio6"; + function =3D "normal"; + power-source =3D <1>; + bias-pull-up; + input-enable; + }; +}; + +&pm8550_pwm { + status =3D "okay"; + + multi-led { + color =3D ; + function =3D LED_FUNCTION_CHARGING; + + #address-cells =3D <1>; + #size-cells =3D <0>; + + led@1 { + reg =3D <1>; + color =3D ; + }; + + led@2 { + reg =3D <2>; + color =3D ; + }; + + led@3 { + reg =3D <3>; + color =3D ; + }; + }; +}; + +&pm8550b_eusb2_repeater { + qcom,tune-usb2-disc-thres =3D /bits/ 8 <0x6>; + qcom,tune-usb2-amplitude =3D /bits/ 8 <0xb>; + qcom,tune-usb2-preem =3D /bits/ 8 <0x3>; + vdd18-supply =3D <&vreg_l15b_1p8>; + vdd3-supply =3D <&vreg_l5b_3p1>; +}; + +&pmk8550_gpios { + pwm_backlight_default: pwm-backlight-default-state { + pins =3D "gpio5"; + function =3D "func3"; + input-disable; + output-enable; + output-low; + bias-disable; + power-source =3D <0>; + qcom,drive-strength =3D <2>; + }; +}; + +&pmk8550_pwm { + status =3D "okay"; +}; + +&pmk8550_rtc { + nvmem-cells =3D <&rtc_offset>; + nvmem-cell-names =3D "offset"; + + status =3D "okay"; +}; + +&pmk8550_sdam_2 { + status =3D "okay"; + + rtc_offset: rtc-offset@bc { + reg =3D <0xbc 0x4>; + }; +}; + +&pon_pwrkey { + status =3D "okay"; +}; + +&pon_resin { + linux,code =3D ; + status =3D "okay"; +}; + +&qupv3_id_0 { + status =3D "okay"; +}; + +&qupv3_id_1 { + status =3D "okay"; +}; + +&remoteproc_adsp { + firmware-name =3D "qcom/sm8550/ayn/odin2/adsp.mbn", + "qcom/sm8550/ayn/odin2/adsp_dtb.mbn"; + status =3D "okay"; +}; + +&remoteproc_cdsp { + firmware-name =3D "qcom/sm8550/ayn/odin2/cdsp.mbn", + "qcom/sm8550/ayn/odin2/cdsp_dtb.mbn"; + status =3D "okay"; +}; + +&sdhc_2 { + cd-gpios =3D <&pm8550_gpios 12 GPIO_ACTIVE_LOW>; + pinctrl-names =3D "default", "sleep"; + pinctrl-0 =3D <&sdc2_default &sdc2_card_det_n>; + pinctrl-1 =3D <&sdc2_sleep &sdc2_card_det_n>; + vmmc-supply =3D <&vreg_l9b_2p9>; + vqmmc-supply =3D <&vreg_l8b_1p8>; + bus-width =3D <4>; + no-sdio; + no-mmc; + + /* SDR104 does seem to be working on this device*/ + /delete-property/ sdhci-caps-mask; + qcom,dll-config =3D <0x0007442c>; + + status =3D "okay"; +}; + +&sleep_clk { + clock-frequency =3D <32000>; +}; + +&tlmm { + gpio-reserved-ranges =3D <32 8>; + + fan_int: fan-int-state { + pins =3D "gpio13"; + function =3D "gpio"; + drive-strength =3D <2>; + bias-disable; + }; + + fan_pwr_en: fan-pwr-en-state { + pins =3D "gpio109"; + function =3D "gpio"; + drive-strength =3D <2>; + bias-disable; + output-low; + }; + + m1_m2_keys_default: m1-m2-keys-default-state { + pins =3D "gpio57", "gpio58"; + function =3D "gpio"; + bias-pull-up; + }; + + ts_int_default: ts-int-default-state { + pins =3D "gpio25"; + function =3D "gpio"; + bias-pull-up; + drive-strength =3D <8>; + }; + + ts_int_sleep: ts-int-sleep-state { + pins =3D "gpio25"; + function =3D "gpio"; + bias-pull-down; + drive-strength =3D <2>; + }; + + bt_default: bt-default-state { + bt-en-pins { + pins =3D "gpio81"; + function =3D "gpio"; + drive-strength =3D <16>; + bias-disable; + }; + + sw-ctrl-pins { + pins =3D "gpio82"; + function =3D "gpio"; + bias-pull-down; + }; + }; + + usb0_sbu_default: usb0-sbu-state { + oe-n-pins { + pins =3D "gpio140"; + function =3D "gpio"; + bias-disable; + drive-strength =3D <16>; + output-high; + }; + + sel-pins { + pins =3D "gpio141"; + function =3D "gpio"; + bias-disable; + drive-strength =3D <16>; + }; + }; + + sde_dsi_active: sde-dsi-active-state { + pins =3D "gpio133"; + function =3D "gpio"; + drive-strength =3D <8>; + bias-disable; + }; + + sde_dsi_suspend: sde-dsi-suspend-state { + pins =3D "gpio133"; + function =3D "gpio"; + drive-strength =3D <2>; + bias-pull-down; + }; + + sde_te_active: sde-te-active-state { + pins =3D "gpio86"; + function =3D "mdp_vsync"; + drive-strength =3D <2>; + bias-pull-down; + }; + + sde_te_suspend: sde-te-suspend-state { + pins =3D "gpio86"; + function =3D "mdp_vsync"; + drive-strength =3D <2>; + bias-pull-down; + }; +}; + +&uart7 { + status =3D "okay"; +}; + +&uart14 { + status =3D "okay"; + + bluetooth { + compatible =3D "qcom,wcn7850-bt"; + + vddio-supply =3D <&vreg_l15b_1p8>; + vddaon-supply =3D <&vreg_s4e_0p95>; + vdddig-supply =3D <&vreg_s4e_0p95>; + vddrfa0p8-supply =3D <&vreg_s4e_0p95>; + vddrfa1p2-supply =3D <&vreg_s4g_1p25>; + vddrfa1p9-supply =3D <&vreg_s6g_1p86>; + + max-speed =3D <3200000>; + + enable-gpios =3D <&tlmm 81 GPIO_ACTIVE_HIGH>; + swctrl-gpios =3D <&tlmm 82 GPIO_ACTIVE_HIGH>; + + pinctrl-0 =3D <&bt_default>; + pinctrl-names =3D "default"; + }; +}; + +&uart15 { + status =3D "okay"; + + /* Gamepad controlled by onboard MCU */ +}; + +&ufs_mem_hc { + reset-gpios =3D <&tlmm 210 GPIO_ACTIVE_LOW>; + vcc-supply =3D <&vreg_l17b_2p5>; + vcc-max-microamp =3D <1300000>; + vccq-supply =3D <&vreg_l1g_1p2>; + vccq-max-microamp =3D <1200000>; + vdd-hba-supply =3D <&vreg_l3g_1p2>; + + status =3D "okay"; +}; + +&ufs_mem_phy { + vdda-phy-supply =3D <&vreg_l1d_0p88>; + vdda-pll-supply =3D <&vreg_l3e_1p2>; + + status =3D "okay"; +}; + +&usb_1 { + status =3D "okay"; +}; + +&usb_1_dwc3 { + dr_mode =3D "otg"; + usb-role-switch; + maximum-speed =3D "super-speed-plus-gen2x1"; +}; + +&usb_1_dwc3_hs { + remote-endpoint =3D <&pmic_glink_hs_in>; +}; + +&usb_1_dwc3_ss { + remote-endpoint =3D <&usb_dp_qmpphy_usb_ss_in>; +}; + +&usb_1_hsphy { + vdd-supply =3D <&vreg_l1e_0p88>; + vdda12-supply =3D <&vreg_l3e_1p2>; + + phys =3D <&pm8550b_eusb2_repeater>; + + status =3D "okay"; +}; + +&usb_dp_qmpphy { + vdda-phy-supply =3D <&vreg_l3e_1p2>; + vdda-pll-supply =3D <&vreg_l3f_0p88>; + + orientation-switch; + + status =3D "okay"; +}; + +&usb_dp_qmpphy_dp_in { + remote-endpoint =3D <&mdss_dp0_out>; +}; + +&usb_dp_qmpphy_out { + remote-endpoint =3D <&pmic_glink_ss_in>; +}; + +&usb_dp_qmpphy_usb_ss_in { + remote-endpoint =3D <&usb_1_dwc3_ss>; +}; + +&xo_board { + clock-frequency =3D <76800000>; +}; --=20 2.44.0