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charset="utf-8" Enable the cmu_hsi2 clock management unit. It feeds some of the high speed interfaces such as PCIe and UFS. Signed-off-by: Peter Griffin Reviewed-by: Andr=C3=A9 Draszik --- arch/arm64/boot/dts/exynos/google/gs101.dtsi | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/arch/arm64/boot/dts/exynos/google/gs101.dtsi b/arch/arm64/boot= /dts/exynos/google/gs101.dtsi index eddb6b326fde..38ac4fb1397e 100644 --- a/arch/arm64/boot/dts/exynos/google/gs101.dtsi +++ b/arch/arm64/boot/dts/exynos/google/gs101.dtsi @@ -1253,6 +1253,18 @@ pinctrl_hsi1: pinctrl@11840000 { interrupts =3D ; }; =20 + cmu_hsi2: clock-controller@14400000 { + compatible =3D "google,gs101-cmu-hsi2"; + reg =3D <0x14400000 0x4000>; + #clock-cells =3D <1>; + clocks =3D <&ext_24_5m>, + <&cmu_top CLK_DOUT_CMU_HSI2_BUS>, + <&cmu_top CLK_DOUT_CMU_HSI2_PCIE>, + <&cmu_top CLK_DOUT_CMU_HSI2_UFS_EMBD>, + <&cmu_top CLK_DOUT_CMU_HSI2_MMC_CARD>; + clock-names =3D "oscclk", "bus", "pcie", "ufs_embd", "mmc_card"; + }; + pinctrl_hsi2: pinctrl@14440000 { compatible =3D "google,gs101-pinctrl"; reg =3D <0x14440000 0x00001000>; --=20 2.44.0.769.g3c40516874-goog