From nobody Sun May 19 08:30:46 2024 Received: from fllv0015.ext.ti.com (fllv0015.ext.ti.com [198.47.19.141]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C3B5C5820E; Tue, 23 Apr 2024 15:17:42 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.47.19.141 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1713885464; cv=none; b=nnUR2nvrk2zqMVuwCP35eTIMxdykrCZEwfv720doC2SgK6r7XbIlUO1OIBGgTukVNeji/gsi4Wel+nmW1fFFR4lTnso9eBFSucRshLK4lMhDkyimmJTT3KbSQ06Xb/xrUuOxy4Kb42MSWsn8zvDF4SXGZ0MBOtIenlGNcLeDH5M= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1713885464; c=relaxed/simple; bh=11X1XUAxVaW4b16EfFWhWg9RCuLlRPTWcapG2V7xXTU=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=q4fIsXAJtxEi2qf02x6rpQyudaBo8DlPhlVmhBKDoBEy1bBg4EI2OvILPLpHp00rwsWimQ9B2XVLFIpg7947y0Ke7eAXVKxaYMPChhCML6rTsbJTMz7SSQhpS4dBZoJoJZFbKSlZTKURsNEclHYykZ1PVlicQ8TmCrsuxVKaKMM= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com; spf=pass smtp.mailfrom=ti.com; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b=kcbifMMN; arc=none smtp.client-ip=198.47.19.141 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=ti.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b="kcbifMMN" Received: from lelv0266.itg.ti.com ([10.180.67.225]) by fllv0015.ext.ti.com (8.15.2/8.15.2) with ESMTP id 43NFHWKF060829; Tue, 23 Apr 2024 10:17:32 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1713885452; bh=h22C2hujtGXlxvbATtGe/0Gh3kVEv7O7ltevjWhcaB0=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=kcbifMMNCst26oyhQIIGZNdbOTeeL1ct7iNR4WU5Q/+0RijalhgWTY1Z6CsTx7CJA XUdsc+NbZrk5/8g1MEMlMAqF7/mHEnw1Gvi7o668PWzzbCrN+DE6Z3+vWk9KUVPFjz TZMO1jTLxZaKEmALhsxpa7uJVTsKoZvl5qPO+EUk= Received: from DFLE103.ent.ti.com (dfle103.ent.ti.com [10.64.6.24]) by lelv0266.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 43NFHWNA098205 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Tue, 23 Apr 2024 10:17:32 -0500 Received: from DFLE103.ent.ti.com (10.64.6.24) by DFLE103.ent.ti.com (10.64.6.24) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23; Tue, 23 Apr 2024 10:17:32 -0500 Received: from lelvsmtp6.itg.ti.com (10.180.75.249) by DFLE103.ent.ti.com (10.64.6.24) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23 via Frontend Transport; Tue, 23 Apr 2024 10:17:32 -0500 Received: from judy-hp.dhcp.ti.com (judy-hp.dhcp.ti.com [128.247.81.105]) by lelvsmtp6.itg.ti.com (8.15.2/8.15.2) with ESMTP id 43NFHWYH080176; Tue, 23 Apr 2024 10:17:32 -0500 From: Judith Mendez To: Rob Herring , Krzysztof Kozlowski CC: Conor Dooley , , , , Bhavya Kapoor , Dasnavis Sabiya , Vignesh Raghavendra Subject: [PATCH v3 1/5] arm64: dts: ti: k3-am65-main: Fix sdhci node properties Date: Tue, 23 Apr 2024 10:17:28 -0500 Message-ID: <20240423151732.3541894-2-jm@ti.com> X-Mailer: git-send-email 2.43.2 In-Reply-To: <20240423151732.3541894-1-jm@ti.com> References: <20240423151732.3541894-1-jm@ti.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Content-Type: text/plain; charset="utf-8" Update otap-del-sel properties as per datasheet [0]. Add missing clkbuf-sel and itap-del-sel values also as per datasheet [0]. Move clkbuf-sel and ti,trm-icp above the otap-del-sel properties so the sdhci nodes could be more uniform across platforms. [0] https://www.ti.com/lit/ds/symlink/am6548.pdf Fixes: eac99d38f861 ("arm64: dts: ti: k3-am654-main: Update otap-del-sel va= lues") Fixes: d7600d070fb0 ("arm64: dts: ti: k3-am65-main: Add support for sdhci1") Signed-off-by: Judith Mendez --- Changes since v2: - no change --- arch/arm64/boot/dts/ti/k3-am65-main.dtsi | 17 +++++++++++------ 1 file changed, 11 insertions(+), 6 deletions(-) diff --git a/arch/arm64/boot/dts/ti/k3-am65-main.dtsi b/arch/arm64/boot/dts= /ti/k3-am65-main.dtsi index 670557c89f756..0803a8b9bfe84 100644 --- a/arch/arm64/boot/dts/ti/k3-am65-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am65-main.dtsi @@ -435,6 +435,8 @@ sdhci0: mmc@4f80000 { interrupts =3D ; mmc-ddr-1_8v; mmc-hs200-1_8v; + ti,clkbuf-sel =3D <0x7>; + ti,trm-icp =3D <0x8>; ti,otap-del-sel-legacy =3D <0x0>; ti,otap-del-sel-mmc-hs =3D <0x0>; ti,otap-del-sel-sd-hs =3D <0x0>; @@ -445,8 +447,7 @@ sdhci0: mmc@4f80000 { ti,otap-del-sel-ddr50 =3D <0x5>; ti,otap-del-sel-ddr52 =3D <0x5>; ti,otap-del-sel-hs200 =3D <0x5>; - ti,otap-del-sel-hs400 =3D <0x0>; - ti,trm-icp =3D <0x8>; + ti,itap-del-sel-ddr52 =3D <0x0>; dma-coherent; status =3D "disabled"; }; @@ -458,18 +459,22 @@ sdhci1: mmc@4fa0000 { clocks =3D <&k3_clks 48 0>, <&k3_clks 48 1>; clock-names =3D "clk_ahb", "clk_xin"; interrupts =3D ; + ti,clkbuf-sel =3D <0x7>; + ti,trm-icp =3D <0x8>; ti,otap-del-sel-legacy =3D <0x0>; ti,otap-del-sel-mmc-hs =3D <0x0>; ti,otap-del-sel-sd-hs =3D <0x0>; - ti,otap-del-sel-sdr12 =3D <0x0>; - ti,otap-del-sel-sdr25 =3D <0x0>; + ti,otap-del-sel-sdr12 =3D <0xf>; + ti,otap-del-sel-sdr25 =3D <0xf>; ti,otap-del-sel-sdr50 =3D <0x8>; ti,otap-del-sel-sdr104 =3D <0x7>; ti,otap-del-sel-ddr50 =3D <0x4>; ti,otap-del-sel-ddr52 =3D <0x4>; ti,otap-del-sel-hs200 =3D <0x7>; - ti,clkbuf-sel =3D <0x7>; - ti,trm-icp =3D <0x8>; + ti,itap-del-sel-legacy =3D <0xa>; + ti,itap-del-sel-sd-hs =3D <0x1>; + ti,itap-del-sel-sdr12 =3D <0xa>; + ti,itap-del-sel-sdr25 =3D <0x1>; dma-coherent; status =3D "disabled"; }; --=20 2.43.2 From nobody Sun May 19 08:30:46 2024 Received: from lelv0143.ext.ti.com (lelv0143.ext.ti.com [198.47.23.248]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B858813D29E; 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Tue, 23 Apr 2024 10:17:32 -0500 Received: from DFLE101.ent.ti.com (10.64.6.22) by DFLE104.ent.ti.com (10.64.6.25) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23; Tue, 23 Apr 2024 10:17:32 -0500 Received: from lelvsmtp6.itg.ti.com (10.180.75.249) by DFLE101.ent.ti.com (10.64.6.22) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23 via Frontend Transport; Tue, 23 Apr 2024 10:17:32 -0500 Received: from judy-hp.dhcp.ti.com (judy-hp.dhcp.ti.com [128.247.81.105]) by lelvsmtp6.itg.ti.com (8.15.2/8.15.2) with ESMTP id 43NFHWYI080176; Tue, 23 Apr 2024 10:17:32 -0500 From: Judith Mendez To: Rob Herring , Krzysztof Kozlowski CC: Conor Dooley , , , , Bhavya Kapoor , Dasnavis Sabiya , Vignesh Raghavendra Subject: [PATCH v3 2/5] arm64: dts: ti: k3-am65-main: Remove unused properties in sdhci nodes Date: Tue, 23 Apr 2024 10:17:29 -0500 Message-ID: <20240423151732.3541894-3-jm@ti.com> X-Mailer: git-send-email 2.43.2 In-Reply-To: <20240423151732.3541894-1-jm@ti.com> References: <20240423151732.3541894-1-jm@ti.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Content-Type: text/plain; charset="utf-8" On AM65x platform, sdhci0 is for eMMC and sdhci1 is for SD. Remove the properties that are not applicable for each device. Fixes: eac99d38f861 ("arm64: dts: ti: k3-am654-main: Update otap-del-sel va= lues") Fixes: d7600d070fb0 ("arm64: dts: ti: k3-am65-main: Add support for sdhci1") Signed-off-by: Judith Mendez --- Changes since v2: - no change --- arch/arm64/boot/dts/ti/k3-am65-main.dtsi | 9 --------- 1 file changed, 9 deletions(-) diff --git a/arch/arm64/boot/dts/ti/k3-am65-main.dtsi b/arch/arm64/boot/dts= /ti/k3-am65-main.dtsi index 0803a8b9bfe84..127f581a56bc6 100644 --- a/arch/arm64/boot/dts/ti/k3-am65-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am65-main.dtsi @@ -439,12 +439,6 @@ sdhci0: mmc@4f80000 { ti,trm-icp =3D <0x8>; ti,otap-del-sel-legacy =3D <0x0>; ti,otap-del-sel-mmc-hs =3D <0x0>; - ti,otap-del-sel-sd-hs =3D <0x0>; - ti,otap-del-sel-sdr12 =3D <0x0>; - ti,otap-del-sel-sdr25 =3D <0x0>; - ti,otap-del-sel-sdr50 =3D <0x8>; - ti,otap-del-sel-sdr104 =3D <0x7>; - ti,otap-del-sel-ddr50 =3D <0x5>; ti,otap-del-sel-ddr52 =3D <0x5>; ti,otap-del-sel-hs200 =3D <0x5>; ti,itap-del-sel-ddr52 =3D <0x0>; @@ -462,15 +456,12 @@ sdhci1: mmc@4fa0000 { ti,clkbuf-sel =3D <0x7>; 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Tue, 23 Apr 2024 10:17:32 -0500 Received: from judy-hp.dhcp.ti.com (judy-hp.dhcp.ti.com [128.247.81.105]) by lelvsmtp6.itg.ti.com (8.15.2/8.15.2) with ESMTP id 43NFHWYJ080176; Tue, 23 Apr 2024 10:17:32 -0500 From: Judith Mendez To: Rob Herring , Krzysztof Kozlowski CC: Conor Dooley , , , , Bhavya Kapoor , Dasnavis Sabiya , Vignesh Raghavendra Subject: [PATCH v3 3/5] arm64: dts: ti: k3-am62a: Enable UHS mode support for SD cards Date: Tue, 23 Apr 2024 10:17:30 -0500 Message-ID: <20240423151732.3541894-4-jm@ti.com> X-Mailer: git-send-email 2.43.2 In-Reply-To: <20240423151732.3541894-1-jm@ti.com> References: <20240423151732.3541894-1-jm@ti.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Content-Type: text/plain; charset="utf-8" From: Vignesh Raghavendra Hook up required IO voltage regulators and drop no-1-8-v to support UHS modes on SD cards. Fixes: 5fc6b1b62639 ("arm64: dts: ti: Introduce AM62A7 family of SoCs") Signed-off-by: Vignesh Raghavendra [Judith: Remove no-1-8-v for sdhci2, keep otap-del-sel-legacy=3D0, add fixes tag, reword commit] Signed-off-by: Judith Mendez --- Changes since v2: - no change --- arch/arm64/boot/dts/ti/k3-am62a-main.dtsi | 2 -- arch/arm64/boot/dts/ti/k3-am62a7-sk.dts | 21 +++++++++++++++++++++ 2 files changed, 21 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/ti/k3-am62a-main.dtsi b/arch/arm64/boot/dt= s/ti/k3-am62a-main.dtsi index aa1e057082f08..6652701d3e3b8 100644 --- a/arch/arm64/boot/dts/ti/k3-am62a-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am62a-main.dtsi @@ -573,7 +573,6 @@ sdhci1: mmc@fa00000 { ti,itap-del-sel-sd-hs =3D <0x0>; ti,itap-del-sel-sdr12 =3D <0x0>; ti,itap-del-sel-sdr25 =3D <0x0>; - no-1-8-v; status =3D "disabled"; }; =20 @@ -597,7 +596,6 @@ sdhci2: mmc@fa20000 { ti,itap-del-sel-sd-hs =3D <0x0>; ti,itap-del-sel-sdr12 =3D <0x0>; ti,itap-del-sel-sdr25 =3D <0x0>; - no-1-8-v; status =3D "disabled"; }; =20 diff --git a/arch/arm64/boot/dts/ti/k3-am62a7-sk.dts b/arch/arm64/boot/dts/= ti/k3-am62a7-sk.dts index f241637a5642a..fa43cd0b631e6 100644 --- a/arch/arm64/boot/dts/ti/k3-am62a7-sk.dts +++ b/arch/arm64/boot/dts/ti/k3-am62a7-sk.dts @@ -113,6 +113,20 @@ vcc_3v3_sys: regulator-4 { regulator-boot-on; }; =20 + vddshv_sdio: regulator-5 { + compatible =3D "regulator-gpio"; + regulator-name =3D "vddshv_sdio"; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&vddshv_sdio_pins_default>; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <3300000>; + regulator-boot-on; + vin-supply =3D <&ldo1>; + gpios =3D <&main_gpio0 31 GPIO_ACTIVE_HIGH>; + states =3D <1800000 0x0>, + <3300000 0x1>; + }; + leds { compatible =3D "gpio-leds"; pinctrl-names =3D "default"; @@ -342,6 +356,12 @@ main_gpio1_ioexp_intr_pins_default: main-gpio1-ioexp-i= ntr-default-pins { AM62AX_IOPAD(0x01d4, PIN_INPUT, 7) /* (C15) UART0_RTSn.GPIO1_23 */ >; }; + + vddshv_sdio_pins_default: vddshv-sdio-default-pins { + pinctrl-single,pins =3D < + AM62AX_IOPAD(0x07c, PIN_OUTPUT, 7) /* (M19) GPMC0_CLK.GPIO0_31 */ + >; + }; }; =20 &mcu_pmx0 { @@ -580,6 +600,7 @@ &sdhci1 { /* SD/MMC */ status =3D "okay"; vmmc-supply =3D <&vdd_mmc1>; + vqmmc-supply =3D <&vddshv_sdio>; pinctrl-names =3D "default"; pinctrl-0 =3D <&main_mmc1_pins_default>; disable-wp; --=20 2.43.2 From nobody Sun May 19 08:30:46 2024 Received: from lelv0142.ext.ti.com (lelv0142.ext.ti.com [198.47.23.249]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 0A27513D283; Tue, 23 Apr 2024 15:17:50 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.47.23.249 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1713885472; cv=none; b=NKQnkz0SglcSI01IMrkmZ5r102xD7w7zlZxmUfbfUusjkFAup4Et69GQmWFRYuIHzQxSPB2XTxMai5Oc1N+sd0mjlr5WdlKjb50DNdkdQS1Fl+2QAoGcHaU+BMCxYzfB9x61lOCG5+5xipsZrdJ0ohNMdgx46S1SzP929TZABBY= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1713885472; 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Tue, 23 Apr 2024 10:17:32 -0500 Received: from judy-hp.dhcp.ti.com (judy-hp.dhcp.ti.com [128.247.81.105]) by lelvsmtp6.itg.ti.com (8.15.2/8.15.2) with ESMTP id 43NFHWYK080176; Tue, 23 Apr 2024 10:17:32 -0500 From: Judith Mendez To: Rob Herring , Krzysztof Kozlowski CC: Conor Dooley , , , , Bhavya Kapoor , Dasnavis Sabiya , Vignesh Raghavendra Subject: [PATCH v3 4/5] arm64: dts: ti: k3-j721s2-main: Enable support for SDR104 speed mode Date: Tue, 23 Apr 2024 10:17:31 -0500 Message-ID: <20240423151732.3541894-5-jm@ti.com> X-Mailer: git-send-email 2.43.2 In-Reply-To: <20240423151732.3541894-1-jm@ti.com> References: <20240423151732.3541894-1-jm@ti.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Content-Type: text/plain; charset="utf-8" From: Bhavya Kapoor According to TRM for J721S2, SDR104 speed mode is supported by the SoC but its capabilities were masked in device tree. Remove sdhci-caps-mask to enable support for SDR104 speed mode for SD card in J721S2 SoC. [+] Refer to : section 12.3.6.1.1 MMCSD Features, in J721S2 TRM - https://www.ti.com/lit/zip/spruj28 Fixes: b8545f9d3a54 ("arm64: dts: ti: Add initial support for J721S2 SoC") Signed-off-by: Bhavya Kapoor Signed-off-by: Vignesh Raghavendra --- Changes since v2: - no change --- arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi | 2 -- 1 file changed, 2 deletions(-) diff --git a/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi b/arch/arm64/boot/d= ts/ti/k3-j721s2-main.dtsi index 3cb06a7e4117f..9ed6949b40e9d 100644 --- a/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi @@ -768,8 +768,6 @@ main_sdhci1: mmc@4fb0000 { ti,clkbuf-sel =3D <0x7>; ti,trm-icp =3D <0x8>; dma-coherent; - /* Masking support for SDR104 capability */ - sdhci-caps-mask =3D <0x00000003 0x00000000>; status =3D "disabled"; }; =20 --=20 2.43.2 From nobody Sun May 19 08:30:46 2024 Received: from lelv0142.ext.ti.com (lelv0142.ext.ti.com [198.47.23.249]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C95CD13C67E; Tue, 23 Apr 2024 15:17:50 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.47.23.249 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1713885472; cv=none; b=TZ8xcwiVdVaBsBYwjMLx3TaUaLmKpJHs3fuPmKhGyMV1syjEJWM4Yclwe++uNUf4qYydbwLIQE0YjMvPIjE5en6VG5TPRRWsTjt2G4LgA14GT0VfJo/HjNmzf3f9mzpatYH6b/bbzdcMGBG3UtFm09YE2EvyjIFgbPNw1vhNDHg= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1713885472; c=relaxed/simple; bh=bvgv9aLUJ3EMk1jeY5CIgMbaDSjxNRI7pgf5rK8d4Wo=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=ckox7BwONBOLv8HXVyAMS37MGigWQ0aLNg/PuglRcqpn8jtldrtSm9jNIIUHDje1oPMBdHDs4sL4kl316qkGpsrLsjuhLX+jhz4RgHTnX4F6zI3B/+qx0tBH96qqMC/RncPACuQuAm6mjzDeYcCimqKrWAdAZfI3q1xdZJ3os5Y= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com; spf=pass smtp.mailfrom=ti.com; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b=ChPSXrCm; arc=none smtp.client-ip=198.47.23.249 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=ti.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b="ChPSXrCm" Received: from fllv0034.itg.ti.com ([10.64.40.246]) by lelv0142.ext.ti.com (8.15.2/8.15.2) with ESMTP id 43NFHXIV078995; Tue, 23 Apr 2024 10:17:33 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1713885453; bh=lvfJKgIkkEKUauOE6w6qO3n0tQqMfPCnxJ2Toh2ImOo=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=ChPSXrCmw4Uan0ilpxHCww+JQG7wUpj/H1+Gy/oFr1y0/n3TtXwZyJkcgyIo0ldj2 klj2eDeumoVT1e6ahMjGdyHWGY3GKgbpzGfQVylHXSWpcwHrp3EM3U1r0/iHUR6tSh ybKgeC5RcI8qzjiDtTEMgA4bvbGylszd6/+LUs40= Received: from DLEE105.ent.ti.com (dlee105.ent.ti.com [157.170.170.35]) by fllv0034.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 43NFHWZm130282 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Tue, 23 Apr 2024 10:17:32 -0500 Received: from DLEE112.ent.ti.com (157.170.170.23) by DLEE105.ent.ti.com (157.170.170.35) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23; Tue, 23 Apr 2024 10:17:32 -0500 Received: from lelvsmtp6.itg.ti.com (10.180.75.249) by DLEE112.ent.ti.com (157.170.170.23) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23 via Frontend Transport; Tue, 23 Apr 2024 10:17:32 -0500 Received: from judy-hp.dhcp.ti.com (judy-hp.dhcp.ti.com [128.247.81.105]) by lelvsmtp6.itg.ti.com (8.15.2/8.15.2) with ESMTP id 43NFHWYL080176; Tue, 23 Apr 2024 10:17:32 -0500 From: Judith Mendez To: Rob Herring , Krzysztof Kozlowski CC: Conor Dooley , , , , Bhavya Kapoor , Dasnavis Sabiya , Vignesh Raghavendra Subject: [PATCH v3 5/5] arm64: dts: ti: k3-j784s4-main: Enable support for UHS mode Date: Tue, 23 Apr 2024 10:17:32 -0500 Message-ID: <20240423151732.3541894-6-jm@ti.com> X-Mailer: git-send-email 2.43.2 In-Reply-To: <20240423151732.3541894-1-jm@ti.com> References: <20240423151732.3541894-1-jm@ti.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Content-Type: text/plain; charset="utf-8" From: Dasnavis Sabiya Remove sdhci-caps-mask to enable support for SDR104 speed mode for SD card and remove no-1-8-v property so that SD card can work in any UHS-1 high speed mode it can support. Fixes: 4664ebd8346a ("arm64: dts: ti: Add initial support for J784S4 SoC") Signed-off-by: Bhavya Kapoor Signed-off-by: Dasnavis Sabiya Signed-off-by: Vignesh Raghavendra [Judith: Add fixes tag] Signed-off-by: Judith Mendez --- Changes since v2: - no change --- arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi | 2 -- 1 file changed, 2 deletions(-) diff --git a/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi b/arch/arm64/boot/d= ts/ti/k3-j784s4-main.dtsi index d42f25cacf23d..6a4554c6c9c13 100644 --- a/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi @@ -904,8 +904,6 @@ main_sdhci1: mmc@4fb0000 { ti,clkbuf-sel =3D <0x7>; ti,trm-icp =3D <0x8>; dma-coherent; - sdhci-caps-mask =3D <0x00000003 0x00000000>; - no-1-8-v; status =3D "disabled"; }; =20 --=20 2.43.2