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Tue, 23 Apr 2024 05:00:13 -0700 From: Prathamesh Shete To: , , , , , , , CC: , , , , Subject: [PATCH v2] gpio: tegra186: Fix tegra186_gpio_is_accessible() check Date: Tue, 23 Apr 2024 17:30:11 +0530 Message-ID: <20240423120011.21554-1-pshete@nvidia.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BN2PEPF000044A1:EE_|MN0PR12MB6128:EE_ X-MS-Office365-Filtering-Correlation-Id: af34eac1-e130-4103-07b0-08dc638cfd6c X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: =?us-ascii?Q?Eod41ayva1XH61sm9jrzphH113eBQYGqREQ3Clf9iPWE0QNrKPHxn6PdEwvj?= =?us-ascii?Q?F2V6VXO+FfvHj2B9KAn1wWTjlH6nxqujrIv6Bqm3whKyTc90qYJvy9p0OvtQ?= =?us-ascii?Q?JgijEyVR4A9Ylrw14oe3URE50L50xf0XVZNUTdhTOtmN0n+D8nBIlMXs36Lc?= =?us-ascii?Q?iFk/taylIdJeyk9jGEGQXMeqlAwWPiOWDVB/H4xY7Wh5QJNeZ+izZjRzanST?= =?us-ascii?Q?NGatCaPyM0SV/5wB/lNczNNasEzJOfDg4AHNbsODLRoto+gXfS2Tap6qX9NG?= =?us-ascii?Q?U+6E24NpcxfmPT9AxFi7Q/HJCGefyaoXwCwhqPs7x5bfLDg9VcAdgzFkobjD?= =?us-ascii?Q?hO7JfnBDLpWusERn2jTLP5y5ii+LNvysaWa8sTp4ZDnc2W+lCZ6T/iF5eipt?= =?us-ascii?Q?j0KeesX92t9TahHC57tCoGOjYHehPxJk6VJhPqkjUF6LPrRS8VscLUkzPV6C?= =?us-ascii?Q?Wsmld/199zrmP4WOVLSPxm+4Nii6EP2yB4hK885KFgR7Q3uiH5IlXihjv3Y9?= =?us-ascii?Q?CrhbBOMeKmDdKGQ00/IKnXpg2bsma7bvrH+YgDZ+e0Sz23mJ1pPiSIQgM0wS?= =?us-ascii?Q?DZuMIKLBEbT/hayOH/aaU/VnbA8kM/Db1Jfo3TxiTTENX0b8E+Rc6q/KWHgS?= =?us-ascii?Q?eUyTpKtkLSRRPbgOJ4NdTkQp2glX1rBkrREMC+Ku2n5OFVtQ/usjJIL9+bgM?= =?us-ascii?Q?ga4nQ4qSB7uCYk4KzR+se+v6B8c5Dp4RVyKKFbpAp9SZryAmLDD8G/2QLVzF?= =?us-ascii?Q?Z744IWdFp6IosozR72bHeHnG0jVbOPj83iW8GZ/r7ZrJ1qFaXyp17U35F/lb?= =?us-ascii?Q?LMrLRegj3LF7ogR8XNVFfbKuVJVKT1w2nT62zZbEyJGvMmAtAg7d03yGjo4y?= =?us-ascii?Q?WppgUZYXz8x6tDmGaTEfGz7ymjIk1akl0fgrpEz/OmPr6dTxgfo+Tx7d9goi?= =?us-ascii?Q?wIueN6XxaTOFEZKzpHlC5oTutUCv6LMnihsIqMS5TY/MDWI9gFpr2JTQPQHn?= =?us-ascii?Q?3YRxDK03/7vbBhMEsB1zk2YaY/4gcuFopxPisuTkjM8RpIxwLFhQMReFTaNO?= =?us-ascii?Q?us3nQk2XhRSltnFxTfiXqW5J3JF18DPh0dPGhpsnmXj6wY8nGR2M9fkZ57cZ?= =?us-ascii?Q?/WJOS1wFJsrDr02v1GEe6mpMKbaPYVwHulcMxnUhVp7k5C4iqWF9cvoDLhRg?= =?us-ascii?Q?YWHXcRmrf9lQ96lnL73a6RbcfxnSzQ89DeYaQMLH65liOopPE/GlNfSrJbPD?= =?us-ascii?Q?kpQutieIoxyG8fAz99Ehx48jMQtE5o1zqSXF3JiQwbUHiH8MjKN+j6vKfM5e?= =?us-ascii?Q?XFEtplUoCdQJmGSQDpS3mwEt47XRrGZX1eJNxbiOObOZwoh9VgmIDD38eobE?= =?us-ascii?Q?h0CdH2R02S7hh+WpFWxdOaSrz83H?= X-Forefront-Antispam-Report: CIP:216.228.117.160;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge1.nvidia.com;CAT:NONE;SFS:(13230031)(376005)(1800799015)(82310400014)(36860700004);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 23 Apr 2024 12:00:37.5867 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: af34eac1-e130-4103-07b0-08dc638cfd6c X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.160];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BN2PEPF000044A1.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MN0PR12MB6128 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The controller has several register bits describing access control information for a given GPIO pin. When SCR_SEC_[R|W]EN is unset, it means we have full read/write access to all the registers for given GPIO pin. When SCR_SEC[R|W]EN is set, it means we need to further check the accompanying SCR_SEC_G1[R|W] bit to determine read/write access to all the registers for given GPIO pin. This check was previously declaring that a GPIO pin was accessible only if either of the following conditions were met: - SCR_SEC_REN + SCR_SEC_WEN both set or - SCR_SEC_REN + SCR_SEC_WEN both set and SCR_SEC_G1R + SCR_SEC_G1W both set Update the check to properly handle cases where only one of SCR_SEC_REN or SCR_SEC_WEN is set. Fixes: b2b56a163230 ("gpio: tegra186: Check GPIO pin permission before acce= ss.") Signed-off-by: Prathamesh Shete --- drivers/gpio/gpio-tegra186.c | 20 +++++++++++--------- 1 file changed, 11 insertions(+), 9 deletions(-) diff --git a/drivers/gpio/gpio-tegra186.c b/drivers/gpio/gpio-tegra186.c index d87dd06db40d..9130c691a2dd 100644 --- a/drivers/gpio/gpio-tegra186.c +++ b/drivers/gpio/gpio-tegra186.c @@ -36,12 +36,6 @@ #define TEGRA186_GPIO_SCR_SEC_REN BIT(27) #define TEGRA186_GPIO_SCR_SEC_G1W BIT(9) #define TEGRA186_GPIO_SCR_SEC_G1R BIT(1) -#define TEGRA186_GPIO_FULL_ACCESS (TEGRA186_GPIO_SCR_SEC_WEN | \ - TEGRA186_GPIO_SCR_SEC_REN | \ - TEGRA186_GPIO_SCR_SEC_G1R | \ - TEGRA186_GPIO_SCR_SEC_G1W) -#define TEGRA186_GPIO_SCR_SEC_ENABLE (TEGRA186_GPIO_SCR_SEC_WEN | \ - TEGRA186_GPIO_SCR_SEC_REN) =20 /* control registers */ #define TEGRA186_GPIO_ENABLE_CONFIG 0x00 @@ -177,10 +171,18 @@ static inline bool tegra186_gpio_is_accessible(struct= tegra_gpio *gpio, unsigned =20 value =3D __raw_readl(secure + TEGRA186_GPIO_SCR); =20 - if ((value & TEGRA186_GPIO_SCR_SEC_ENABLE) =3D=3D 0) - return true; + /* + * When SCR_SEC_[R|W]EN is unset, then we have full read/write access to = all the + * registers for given GPIO pin. + * When SCR_SEC[R|W]EN is set, then there is need to further check the ac= companying + * SCR_SEC_G1[R|W] bit to determine read/write access to all the register= s for given + * GPIO pin. + */ =20 - if ((value & TEGRA186_GPIO_FULL_ACCESS) =3D=3D TEGRA186_GPIO_FULL_ACCESS) + if (((value & TEGRA186_GPIO_SCR_SEC_REN) =3D=3D 0 || + ((value & TEGRA186_GPIO_SCR_SEC_REN) && (value & TEGRA186_GPIO_SCR_S= EC_G1R))) && + ((value & TEGRA186_GPIO_SCR_SEC_WEN) =3D=3D 0 || + ((value & TEGRA186_GPIO_SCR_SEC_WEN) && (value & TEGRA186_GPIO_SCR_S= EC_G1W)))) return true; =20 return false; --=20 2.17.1