From nobody Mon Feb 9 17:35:27 2026 Received: from mx0b-0016f401.pphosted.com (mx0a-0016f401.pphosted.com [67.231.148.174]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C46F447A5D; Tue, 23 Apr 2024 07:46:34 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=67.231.148.174 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1713858396; cv=none; b=ncRg806JzTkzv2e4fHCa1xdsoVD26PzR9xdHKdLe96gntC6KATCWjFtf9BbGb/CFjmjCGDzc+kPQBg+yisiCQ777aVrjqnyvjFkBqLF01+gSvmsfaw4pIGi2DpHTGLZ3i+a1zNr838ZwxRc5WYuy+XR9nxFTbYG1DV53kk/rIRA= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1713858396; c=relaxed/simple; bh=O4I7PnUrQ4yKzKJJoqB42JrYaglC3t0N7VGuEuP7EvM=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=egsV/Zhe4N3n/wPGVEw53vS0WWIwIrCeGjwfDBDsE71eScFv8wEF2Hg0gZJ1YFL8gZW3rYi0OQ4CQXpbiZJ80BbryeBUlxkx0llmo4ffMyCdRpiDyRWgKBNw8HkxhGxxQJdtvCePJlShCODVWUCuHJWQTjwiCKmPEP755zx9xUc= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=marvell.com; spf=pass smtp.mailfrom=marvell.com; dkim=pass (2048-bit key) header.d=marvell.com header.i=@marvell.com header.b=GlAkExta; arc=none smtp.client-ip=67.231.148.174 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=marvell.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=marvell.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=marvell.com header.i=@marvell.com header.b="GlAkExta" Received: from pps.filterd (m0045849.ppops.net [127.0.0.1]) by mx0a-0016f401.pphosted.com (8.18.1.2/8.18.1.2) with ESMTP id 43MJQqSY013946; Tue, 23 Apr 2024 00:46:32 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h= from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding:content-type; s= pfpt0220; bh=tg85wy9gKnkj+wZNeONRKHtdHs+hZhP285GqdLuMH7Y=; b=GlA kExtai/qMcZ40BBsbx6VdAkMELMIs387Q67ZtDewUnqaN3JSW1RSXpFAmJsb0lX0 UVCiy09NNkYCVPtKDbV9+xfdT0CV12RZXOq6li5egYGGBC0yrw7IBT54+Hv8XeeG oKh+Elppg5rUG1Ah8jBs9/ffzGxbOeLStwTQdS/9GvZj5ZTfegltkcZ0PyMggAi5 guTDWnKzL0+qf4XDPxQa8N7kKrUbVXw61sEni7DIEe4ir/cEcl/YehpvvP5ZFGWj udfZFnRqqjuuwTvnymisW7cPbvcMLh15ysUcepVe3dIoJuzuBpFQfPXMz2MIv1KN JhLsw495B9A3qSl35Eg== Received: from dc6wp-exch02.marvell.com ([4.21.29.225]) by mx0a-0016f401.pphosted.com (PPS) with ESMTPS id 3xnngcv9jx-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Tue, 23 Apr 2024 00:46:32 -0700 (PDT) Received: from DC6WP-EXCH02.marvell.com (10.76.176.209) by DC6WP-EXCH02.marvell.com (10.76.176.209) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.4; Tue, 23 Apr 2024 00:46:30 -0700 Received: from maili.marvell.com (10.69.176.80) by DC6WP-EXCH02.marvell.com (10.76.176.209) with Microsoft SMTP Server id 15.2.1544.4 via Frontend Transport; Tue, 23 Apr 2024 00:46:30 -0700 Received: from Dell2s-9.sclab.marvell.com (unknown [10.110.150.250]) by maili.marvell.com (Postfix) with ESMTP id 846FB3F7051; Tue, 23 Apr 2024 00:46:30 -0700 (PDT) From: Piyush Malgujar To: , , CC: , , , Piyush Malgujar Subject: [PATCH v7 1/5] i2c: thunderx: Clock divisor logic changes Date: Tue, 23 Apr 2024 00:46:04 -0700 Message-ID: <20240423074618.3278609-2-pmalgujar@marvell.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240423074618.3278609-1-pmalgujar@marvell.com> References: <20240423074618.3278609-1-pmalgujar@marvell.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Proofpoint-GUID: M0-YPlDiUY1SBUnqjzrVUKxIszLTRQEA X-Proofpoint-ORIG-GUID: M0-YPlDiUY1SBUnqjzrVUKxIszLTRQEA X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1011,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2024-04-23_04,2024-04-22_01,2023-05-22_02 Content-Type: text/plain; charset="utf-8" From: Suneel Garapati Handle changes to clock divisor logic for OcteonTX2 SoC family using subsystem ID and using default reference clock source as 100MHz. Signed-off-by: Suneel Garapati Signed-off-by: Piyush Malgujar Acked-by: Andi Shyti --- drivers/i2c/busses/i2c-octeon-core.c | 39 +++++++++++++++++++++--- drivers/i2c/busses/i2c-octeon-core.h | 17 +++++++++++ drivers/i2c/busses/i2c-thunderx-pcidrv.c | 7 +++++ 3 files changed, 59 insertions(+), 4 deletions(-) diff --git a/drivers/i2c/busses/i2c-octeon-core.c b/drivers/i2c/busses/i2c-= octeon-core.c index 845eda70b8cab52a0453c9f4cb545010fba4305d..75efb375d8e49479267e214772d= 4df48352be358 100644 --- a/drivers/i2c/busses/i2c-octeon-core.c +++ b/drivers/i2c/busses/i2c-octeon-core.c @@ -17,9 +17,14 @@ #include #include #include +#include =20 #include "i2c-octeon-core.h" =20 +#define INITIAL_DELTA_HZ 1000000 +#define TWSI_MASTER_CLK_REG_DEF_VAL 0x18 +#define TWSI_MASTER_CLK_REG_OTX2_VAL 0x3 + /* interrupt service routine */ irqreturn_t octeon_i2c_isr(int irq, void *dev_id) { @@ -658,31 +663,57 @@ int octeon_i2c_xfer(struct i2c_adapter *adap, struct = i2c_msg *msgs, int num) void octeon_i2c_set_clock(struct octeon_i2c *i2c) { int tclk, thp_base, inc, thp_idx, mdiv_idx, ndiv_idx, foscl, diff; - int thp =3D 0x18, mdiv =3D 2, ndiv =3D 0, delta_hz =3D 1000000; + bool is_plat_otx2; + unsigned int mdiv_min =3D 2; + /* + * Find divisors to produce target frequency, start with large delta + * to cover wider range of divisors, note thp =3D TCLK half period. + */ + unsigned int thp =3D TWSI_MASTER_CLK_REG_DEF_VAL, mdiv =3D 2, ndiv =3D 0; + unsigned int delta_hz =3D INITIAL_DELTA_HZ; + + is_plat_otx2 =3D octeon_i2c_is_otx2(to_pci_dev(i2c->dev)); + + if (is_plat_otx2) { + thp =3D TWSI_MASTER_CLK_REG_OTX2_VAL; + mdiv_min =3D 0; + } =20 for (ndiv_idx =3D 0; ndiv_idx < 8 && delta_hz !=3D 0; ndiv_idx++) { /* * An mdiv value of less than 2 seems to not work well * with ds1337 RTCs, so we constrain it to larger values. */ - for (mdiv_idx =3D 15; mdiv_idx >=3D 2 && delta_hz !=3D 0; mdiv_idx--) { + for (mdiv_idx =3D 15; mdiv_idx >=3D mdiv_min && delta_hz !=3D 0; mdiv_id= x--) { /* * For given ndiv and mdiv values check the * two closest thp values. */ tclk =3D i2c->twsi_freq * (mdiv_idx + 1) * 10; tclk *=3D (1 << ndiv_idx); - thp_base =3D (i2c->sys_freq / (tclk * 2)) - 1; + if (is_plat_otx2) + thp_base =3D (i2c->sys_freq / tclk) - 2; + else + thp_base =3D (i2c->sys_freq / (tclk * 2)) - 1; =20 for (inc =3D 0; inc <=3D 1; inc++) { thp_idx =3D thp_base + inc; if (thp_idx < 5 || thp_idx > 0xff) continue; =20 - foscl =3D i2c->sys_freq / (2 * (thp_idx + 1)); + if (is_plat_otx2) + foscl =3D i2c->sys_freq / (thp_idx + 2); + else + foscl =3D i2c->sys_freq / + (2 * (thp_idx + 1)); foscl =3D foscl / (1 << ndiv_idx); foscl =3D foscl / (mdiv_idx + 1) / 10; diff =3D abs(foscl - i2c->twsi_freq); + /* + * Diff holds difference between calculated frequency + * value vs desired frequency. + * Delta_hz is updated with last minimum diff. + */ if (diff < delta_hz) { delta_hz =3D diff; thp =3D thp_idx; diff --git a/drivers/i2c/busses/i2c-octeon-core.h b/drivers/i2c/busses/i2c-= octeon-core.h index 9bb9f64fdda0392364638ecbaafe3fab5612baf6..69bd62940f99eb786877026380c= d1d02a4eaadb9 100644 --- a/drivers/i2c/busses/i2c-octeon-core.h +++ b/drivers/i2c/busses/i2c-octeon-core.h @@ -1,5 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0 */ #include +#include #include #include #include @@ -7,6 +8,7 @@ #include #include #include +#include =20 /* Controller command patterns */ #define SW_TWSI_V BIT_ULL(63) /* Valid bit */ @@ -211,6 +213,21 @@ static inline void octeon_i2c_write_int(struct octeon_= i2c *i2c, u64 data) octeon_i2c_writeq_flush(data, i2c->twsi_base + TWSI_INT(i2c)); } =20 +#define PCI_SUBSYS_DEVID_9XXX 0xB +#define PCI_SUBSYS_MASK GENMASK(15, 12) +/** + * octeon_i2c_is_otx2 - check for chip ID + * @pdev: PCI dev structure + * + * Returns true if the device is an OcteonTX2, false otherwise. + */ +static inline bool octeon_i2c_is_otx2(struct pci_dev *pdev) +{ + u32 chip_id =3D FIELD_GET(PCI_SUBSYS_MASK, pdev->subsystem_device); + + return (chip_id =3D=3D PCI_SUBSYS_DEVID_9XXX); +} + /* Prototypes */ irqreturn_t octeon_i2c_isr(int irq, void *dev_id); int octeon_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg *msgs, int nu= m); diff --git a/drivers/i2c/busses/i2c-thunderx-pcidrv.c b/drivers/i2c/busses/= i2c-thunderx-pcidrv.c index a77cd86fe75ed7401bc041b27c651b9fedf67285..75569774003857dc984e8540ef8= f4d1bb084cfb0 100644 --- a/drivers/i2c/busses/i2c-thunderx-pcidrv.c +++ b/drivers/i2c/busses/i2c-thunderx-pcidrv.c @@ -28,6 +28,7 @@ #define PCI_DEVICE_ID_THUNDER_TWSI 0xa012 =20 #define SYS_FREQ_DEFAULT 700000000 +#define OTX2_REF_FREQ_DEFAULT 100000000 =20 #define TWSI_INT_ENA_W1C 0x1028 #define TWSI_INT_ENA_W1S 0x1030 @@ -205,6 +206,12 @@ static int thunder_i2c_probe_pci(struct pci_dev *pdev, if (ret) goto error; =20 + /* + * For OcteonTX2 chips, set reference frequency to 100MHz + * as refclk_src in TWSI_MODE register defaults to 100MHz. + */ + if (octeon_i2c_is_otx2(pdev)) + i2c->sys_freq =3D OTX2_REF_FREQ_DEFAULT; octeon_i2c_set_clock(i2c); =20 i2c->adap =3D thunderx_i2c_ops; --=20 2.43.0