From nobody Sat May 18 04:30:16 2024 Received: from mx0b-0016f401.pphosted.com (mx0a-0016f401.pphosted.com [67.231.148.174]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C46F447A5D; Tue, 23 Apr 2024 07:46:34 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=67.231.148.174 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1713858396; cv=none; b=ncRg806JzTkzv2e4fHCa1xdsoVD26PzR9xdHKdLe96gntC6KATCWjFtf9BbGb/CFjmjCGDzc+kPQBg+yisiCQ777aVrjqnyvjFkBqLF01+gSvmsfaw4pIGi2DpHTGLZ3i+a1zNr838ZwxRc5WYuy+XR9nxFTbYG1DV53kk/rIRA= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1713858396; c=relaxed/simple; bh=O4I7PnUrQ4yKzKJJoqB42JrYaglC3t0N7VGuEuP7EvM=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=egsV/Zhe4N3n/wPGVEw53vS0WWIwIrCeGjwfDBDsE71eScFv8wEF2Hg0gZJ1YFL8gZW3rYi0OQ4CQXpbiZJ80BbryeBUlxkx0llmo4ffMyCdRpiDyRWgKBNw8HkxhGxxQJdtvCePJlShCODVWUCuHJWQTjwiCKmPEP755zx9xUc= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=marvell.com; spf=pass smtp.mailfrom=marvell.com; dkim=pass (2048-bit key) header.d=marvell.com header.i=@marvell.com header.b=GlAkExta; arc=none smtp.client-ip=67.231.148.174 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=marvell.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=marvell.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=marvell.com header.i=@marvell.com header.b="GlAkExta" Received: from pps.filterd (m0045849.ppops.net [127.0.0.1]) by mx0a-0016f401.pphosted.com (8.18.1.2/8.18.1.2) with ESMTP id 43MJQqSY013946; Tue, 23 Apr 2024 00:46:32 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h= from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding:content-type; s= pfpt0220; bh=tg85wy9gKnkj+wZNeONRKHtdHs+hZhP285GqdLuMH7Y=; b=GlA kExtai/qMcZ40BBsbx6VdAkMELMIs387Q67ZtDewUnqaN3JSW1RSXpFAmJsb0lX0 UVCiy09NNkYCVPtKDbV9+xfdT0CV12RZXOq6li5egYGGBC0yrw7IBT54+Hv8XeeG oKh+Elppg5rUG1Ah8jBs9/ffzGxbOeLStwTQdS/9GvZj5ZTfegltkcZ0PyMggAi5 guTDWnKzL0+qf4XDPxQa8N7kKrUbVXw61sEni7DIEe4ir/cEcl/YehpvvP5ZFGWj udfZFnRqqjuuwTvnymisW7cPbvcMLh15ysUcepVe3dIoJuzuBpFQfPXMz2MIv1KN JhLsw495B9A3qSl35Eg== Received: from dc6wp-exch02.marvell.com ([4.21.29.225]) by mx0a-0016f401.pphosted.com (PPS) with ESMTPS id 3xnngcv9jx-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Tue, 23 Apr 2024 00:46:32 -0700 (PDT) Received: from DC6WP-EXCH02.marvell.com (10.76.176.209) by DC6WP-EXCH02.marvell.com (10.76.176.209) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.4; Tue, 23 Apr 2024 00:46:30 -0700 Received: from maili.marvell.com (10.69.176.80) by DC6WP-EXCH02.marvell.com (10.76.176.209) with Microsoft SMTP Server id 15.2.1544.4 via Frontend Transport; Tue, 23 Apr 2024 00:46:30 -0700 Received: from Dell2s-9.sclab.marvell.com (unknown [10.110.150.250]) by maili.marvell.com (Postfix) with ESMTP id 846FB3F7051; Tue, 23 Apr 2024 00:46:30 -0700 (PDT) From: Piyush Malgujar To: , , CC: , , , Piyush Malgujar Subject: [PATCH v7 1/5] i2c: thunderx: Clock divisor logic changes Date: Tue, 23 Apr 2024 00:46:04 -0700 Message-ID: <20240423074618.3278609-2-pmalgujar@marvell.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240423074618.3278609-1-pmalgujar@marvell.com> References: <20240423074618.3278609-1-pmalgujar@marvell.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Proofpoint-GUID: M0-YPlDiUY1SBUnqjzrVUKxIszLTRQEA X-Proofpoint-ORIG-GUID: M0-YPlDiUY1SBUnqjzrVUKxIszLTRQEA X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1011,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2024-04-23_04,2024-04-22_01,2023-05-22_02 Content-Type: text/plain; charset="utf-8" From: Suneel Garapati Handle changes to clock divisor logic for OcteonTX2 SoC family using subsystem ID and using default reference clock source as 100MHz. Signed-off-by: Suneel Garapati Signed-off-by: Piyush Malgujar Acked-by: Andi Shyti --- drivers/i2c/busses/i2c-octeon-core.c | 39 +++++++++++++++++++++--- drivers/i2c/busses/i2c-octeon-core.h | 17 +++++++++++ drivers/i2c/busses/i2c-thunderx-pcidrv.c | 7 +++++ 3 files changed, 59 insertions(+), 4 deletions(-) diff --git a/drivers/i2c/busses/i2c-octeon-core.c b/drivers/i2c/busses/i2c-= octeon-core.c index 845eda70b8cab52a0453c9f4cb545010fba4305d..75efb375d8e49479267e214772d= 4df48352be358 100644 --- a/drivers/i2c/busses/i2c-octeon-core.c +++ b/drivers/i2c/busses/i2c-octeon-core.c @@ -17,9 +17,14 @@ #include #include #include +#include =20 #include "i2c-octeon-core.h" =20 +#define INITIAL_DELTA_HZ 1000000 +#define TWSI_MASTER_CLK_REG_DEF_VAL 0x18 +#define TWSI_MASTER_CLK_REG_OTX2_VAL 0x3 + /* interrupt service routine */ irqreturn_t octeon_i2c_isr(int irq, void *dev_id) { @@ -658,31 +663,57 @@ int octeon_i2c_xfer(struct i2c_adapter *adap, struct = i2c_msg *msgs, int num) void octeon_i2c_set_clock(struct octeon_i2c *i2c) { int tclk, thp_base, inc, thp_idx, mdiv_idx, ndiv_idx, foscl, diff; - int thp =3D 0x18, mdiv =3D 2, ndiv =3D 0, delta_hz =3D 1000000; + bool is_plat_otx2; + unsigned int mdiv_min =3D 2; + /* + * Find divisors to produce target frequency, start with large delta + * to cover wider range of divisors, note thp =3D TCLK half period. + */ + unsigned int thp =3D TWSI_MASTER_CLK_REG_DEF_VAL, mdiv =3D 2, ndiv =3D 0; + unsigned int delta_hz =3D INITIAL_DELTA_HZ; + + is_plat_otx2 =3D octeon_i2c_is_otx2(to_pci_dev(i2c->dev)); + + if (is_plat_otx2) { + thp =3D TWSI_MASTER_CLK_REG_OTX2_VAL; + mdiv_min =3D 0; + } =20 for (ndiv_idx =3D 0; ndiv_idx < 8 && delta_hz !=3D 0; ndiv_idx++) { /* * An mdiv value of less than 2 seems to not work well * with ds1337 RTCs, so we constrain it to larger values. */ - for (mdiv_idx =3D 15; mdiv_idx >=3D 2 && delta_hz !=3D 0; mdiv_idx--) { + for (mdiv_idx =3D 15; mdiv_idx >=3D mdiv_min && delta_hz !=3D 0; mdiv_id= x--) { /* * For given ndiv and mdiv values check the * two closest thp values. */ tclk =3D i2c->twsi_freq * (mdiv_idx + 1) * 10; tclk *=3D (1 << ndiv_idx); - thp_base =3D (i2c->sys_freq / (tclk * 2)) - 1; + if (is_plat_otx2) + thp_base =3D (i2c->sys_freq / tclk) - 2; + else + thp_base =3D (i2c->sys_freq / (tclk * 2)) - 1; =20 for (inc =3D 0; inc <=3D 1; inc++) { thp_idx =3D thp_base + inc; if (thp_idx < 5 || thp_idx > 0xff) continue; =20 - foscl =3D i2c->sys_freq / (2 * (thp_idx + 1)); + if (is_plat_otx2) + foscl =3D i2c->sys_freq / (thp_idx + 2); + else + foscl =3D i2c->sys_freq / + (2 * (thp_idx + 1)); foscl =3D foscl / (1 << ndiv_idx); foscl =3D foscl / (mdiv_idx + 1) / 10; diff =3D abs(foscl - i2c->twsi_freq); + /* + * Diff holds difference between calculated frequency + * value vs desired frequency. + * Delta_hz is updated with last minimum diff. + */ if (diff < delta_hz) { delta_hz =3D diff; thp =3D thp_idx; diff --git a/drivers/i2c/busses/i2c-octeon-core.h b/drivers/i2c/busses/i2c-= octeon-core.h index 9bb9f64fdda0392364638ecbaafe3fab5612baf6..69bd62940f99eb786877026380c= d1d02a4eaadb9 100644 --- a/drivers/i2c/busses/i2c-octeon-core.h +++ b/drivers/i2c/busses/i2c-octeon-core.h @@ -1,5 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0 */ #include +#include #include #include #include @@ -7,6 +8,7 @@ #include #include #include +#include =20 /* Controller command patterns */ #define SW_TWSI_V BIT_ULL(63) /* Valid bit */ @@ -211,6 +213,21 @@ static inline void octeon_i2c_write_int(struct octeon_= i2c *i2c, u64 data) octeon_i2c_writeq_flush(data, i2c->twsi_base + TWSI_INT(i2c)); } =20 +#define PCI_SUBSYS_DEVID_9XXX 0xB +#define PCI_SUBSYS_MASK GENMASK(15, 12) +/** + * octeon_i2c_is_otx2 - check for chip ID + * @pdev: PCI dev structure + * + * Returns true if the device is an OcteonTX2, false otherwise. + */ +static inline bool octeon_i2c_is_otx2(struct pci_dev *pdev) +{ + u32 chip_id =3D FIELD_GET(PCI_SUBSYS_MASK, pdev->subsystem_device); + + return (chip_id =3D=3D PCI_SUBSYS_DEVID_9XXX); +} + /* Prototypes */ irqreturn_t octeon_i2c_isr(int irq, void *dev_id); int octeon_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg *msgs, int nu= m); diff --git a/drivers/i2c/busses/i2c-thunderx-pcidrv.c b/drivers/i2c/busses/= i2c-thunderx-pcidrv.c index a77cd86fe75ed7401bc041b27c651b9fedf67285..75569774003857dc984e8540ef8= f4d1bb084cfb0 100644 --- a/drivers/i2c/busses/i2c-thunderx-pcidrv.c +++ b/drivers/i2c/busses/i2c-thunderx-pcidrv.c @@ -28,6 +28,7 @@ #define PCI_DEVICE_ID_THUNDER_TWSI 0xa012 =20 #define SYS_FREQ_DEFAULT 700000000 +#define OTX2_REF_FREQ_DEFAULT 100000000 =20 #define TWSI_INT_ENA_W1C 0x1028 #define TWSI_INT_ENA_W1S 0x1030 @@ -205,6 +206,12 @@ static int thunder_i2c_probe_pci(struct pci_dev *pdev, if (ret) goto error; =20 + /* + * For OcteonTX2 chips, set reference frequency to 100MHz + * as refclk_src in TWSI_MODE register defaults to 100MHz. + */ + if (octeon_i2c_is_otx2(pdev)) + i2c->sys_freq =3D OTX2_REF_FREQ_DEFAULT; octeon_i2c_set_clock(i2c); =20 i2c->adap =3D thunderx_i2c_ops; --=20 2.43.0 From nobody Sat May 18 04:30:16 2024 Received: from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com [67.231.156.173]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 915375102F; Tue, 23 Apr 2024 07:46:45 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=67.231.156.173 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1713858407; cv=none; b=DVpXP9sDJtjgFWsT8zFCvR8hENthaV2AEQsZ6EsayfjogZ4Gvd387mI3QuqRRSUx37Abb4o1GnWGNbXl8kuGx+nqF+IrpfapRGjOxQBb5nh+M3WmgnYYnjuSQyspq5n2ulE2fhFNagpIK+NfYsMZ+HnHNDwKaqMeamzgnd0VICw= ARC-Message-Signature: i=1; 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Tue, 23 Apr 2024 00:46:38 -0700 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH05.marvell.com (10.69.176.209) with Microsoft SMTP Server id 15.2.1544.4 via Frontend Transport; Tue, 23 Apr 2024 00:46:38 -0700 Received: from Dell2s-9.sclab.marvell.com (unknown [10.110.150.250]) by maili.marvell.com (Postfix) with ESMTP id 22A713F7051; Tue, 23 Apr 2024 00:46:38 -0700 (PDT) From: Piyush Malgujar To: , , CC: , , , Piyush Malgujar Subject: [PATCH v7 2/5] i2c: thunderx: Support for High speed mode Date: Tue, 23 Apr 2024 00:46:05 -0700 Message-ID: <20240423074618.3278609-3-pmalgujar@marvell.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240423074618.3278609-1-pmalgujar@marvell.com> References: <20240423074618.3278609-1-pmalgujar@marvell.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-Proofpoint-ORIG-GUID: jroGQQuKje9k23iZxoqVXN4PRV8wk6A- X-Proofpoint-GUID: jroGQQuKje9k23iZxoqVXN4PRV8wk6A- X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1011,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2024-04-23_04,2024-04-22_01,2023-05-22_02 From: Suneel Garapati To support bus operations for high speed bus frequencies greater than 400KHZ following control bits need to be setup accordingly - hs_mode (bit 0) field in Mode register to switch controller between low-speed and high-speed frequency operating mode. - Setup clock divisors for desired TWSI bus frequency using FOSCL output frequency divisor (D): 0 - sets the divisor to 10 for low speed mode 1 - sets the divisor to 15 for high speed mode. The TWSI bus output frequency, in master mode is based on: TCLK =3D 100MHz / (THP + 2) FOSCL =3D FSAMP / (M+1)=C3=97D =3D TCLK / (2 ^ N =C3=97 (M = + 1) =C3=97 15) FSAMP =3D TCLK / 2 ^ N where, N is <2:0> and M is <6:3> of TWSI Clock Control Register D is 10 for low speed or 15 for HS_MODE With high speed mode support, HLC mode usage is limited to low speed frequency (<=3D400KHz) bus transfers in hardware. Signed-off-by: Suneel Garapati Signed-off-by: Piyush Malgujar --- drivers/i2c/busses/i2c-octeon-core.c | 68 +++++++++++++++--------- drivers/i2c/busses/i2c-octeon-core.h | 8 +++ drivers/i2c/busses/i2c-thunderx-pcidrv.c | 3 +- 3 files changed, 54 insertions(+), 25 deletions(-) diff --git a/drivers/i2c/busses/i2c-octeon-core.c b/drivers/i2c/busses/i2c-= octeon-core.c index 75efb375d8e49479267e214772d4df48352be358..86be597866f81c1bce54563047e= 14d099743f593 100644 --- a/drivers/i2c/busses/i2c-octeon-core.c +++ b/drivers/i2c/busses/i2c-octeon-core.c @@ -612,25 +612,27 @@ int octeon_i2c_xfer(struct i2c_adapter *adap, struct = i2c_msg *msgs, int num) struct octeon_i2c *i2c =3D i2c_get_adapdata(adap); int i, ret =3D 0; =20 - if (num =3D=3D 1) { - if (msgs[0].len > 0 && msgs[0].len <=3D 8) { - if (msgs[0].flags & I2C_M_RD) - ret =3D octeon_i2c_hlc_read(i2c, msgs); - else - ret =3D octeon_i2c_hlc_write(i2c, msgs); - goto out; - } - } else if (num =3D=3D 2) { - if ((msgs[0].flags & I2C_M_RD) =3D=3D 0 && - (msgs[1].flags & I2C_M_RECV_LEN) =3D=3D 0 && - msgs[0].len > 0 && msgs[0].len <=3D 2 && - msgs[1].len > 0 && msgs[1].len <=3D 8 && - msgs[0].addr =3D=3D msgs[1].addr) { - if (msgs[1].flags & I2C_M_RD) - ret =3D octeon_i2c_hlc_comp_read(i2c, msgs); - else - ret =3D octeon_i2c_hlc_comp_write(i2c, msgs); - goto out; + if (IS_LS_FREQ(i2c->twsi_freq)) { + if (num =3D=3D 1) { + if (msgs[0].len > 0 && msgs[0].len <=3D 8) { + if (msgs[0].flags & I2C_M_RD) + ret =3D octeon_i2c_hlc_read(i2c, msgs); + else + ret =3D octeon_i2c_hlc_write(i2c, msgs); + goto out; + } + } else if (num =3D=3D 2) { + if ((msgs[0].flags & I2C_M_RD) =3D=3D 0 && + (msgs[1].flags & I2C_M_RECV_LEN) =3D=3D 0 && + msgs[0].len > 0 && msgs[0].len <=3D 2 && + msgs[1].len > 0 && msgs[1].len <=3D 8 && + msgs[0].addr =3D=3D msgs[1].addr) { + if (msgs[1].flags & I2C_M_RD) + ret =3D octeon_i2c_hlc_comp_read(i2c, msgs); + else + ret =3D octeon_i2c_hlc_comp_write(i2c, msgs); + goto out; + } } } =20 @@ -664,12 +666,12 @@ void octeon_i2c_set_clock(struct octeon_i2c *i2c) { int tclk, thp_base, inc, thp_idx, mdiv_idx, ndiv_idx, foscl, diff; bool is_plat_otx2; - unsigned int mdiv_min =3D 2; /* * Find divisors to produce target frequency, start with large delta - * to cover wider range of divisors, note thp =3D TCLK half period. + * to cover wider range of divisors, note thp =3D TCLK half period and + * ds is OSCL output frequency divisor. */ - unsigned int thp =3D TWSI_MASTER_CLK_REG_DEF_VAL, mdiv =3D 2, ndiv =3D 0; + unsigned int thp, mdiv_min, mdiv =3D 2, ndiv =3D 0, ds =3D 10; unsigned int delta_hz =3D INITIAL_DELTA_HZ; =20 is_plat_otx2 =3D octeon_i2c_is_otx2(to_pci_dev(i2c->dev)); @@ -677,6 +679,11 @@ void octeon_i2c_set_clock(struct octeon_i2c *i2c) if (is_plat_otx2) { thp =3D TWSI_MASTER_CLK_REG_OTX2_VAL; mdiv_min =3D 0; + if (!IS_LS_FREQ(i2c->twsi_freq)) + ds =3D 15; + } else { + thp =3D TWSI_MASTER_CLK_REG_DEF_VAL; + mdiv_min =3D 2; } =20 for (ndiv_idx =3D 0; ndiv_idx < 8 && delta_hz !=3D 0; ndiv_idx++) { @@ -689,7 +696,7 @@ void octeon_i2c_set_clock(struct octeon_i2c *i2c) * For given ndiv and mdiv values check the * two closest thp values. */ - tclk =3D i2c->twsi_freq * (mdiv_idx + 1) * 10; + tclk =3D i2c->twsi_freq * (mdiv_idx + 1) * ds; tclk *=3D (1 << ndiv_idx); if (is_plat_otx2) thp_base =3D (i2c->sys_freq / tclk) - 2; @@ -707,7 +714,9 @@ void octeon_i2c_set_clock(struct octeon_i2c *i2c) foscl =3D i2c->sys_freq / (2 * (thp_idx + 1)); foscl =3D foscl / (1 << ndiv_idx); - foscl =3D foscl / (mdiv_idx + 1) / 10; + foscl =3D foscl / (mdiv_idx + 1) / ds; + if (foscl > i2c->twsi_freq) + continue; diff =3D abs(foscl - i2c->twsi_freq); /* * Diff holds difference between calculated frequency @@ -725,6 +734,17 @@ void octeon_i2c_set_clock(struct octeon_i2c *i2c) } octeon_i2c_reg_write(i2c, SW_TWSI_OP_TWSI_CLK, thp); octeon_i2c_reg_write(i2c, SW_TWSI_EOP_TWSI_CLKCTL, (mdiv << 3) | ndiv); + if (is_plat_otx2) { + u64 mode; + + mode =3D __raw_readq(i2c->twsi_base + MODE(i2c)); + /* Set REFCLK_SRC and HS_MODE in TWSX_MODE register */ + if (!IS_LS_FREQ(i2c->twsi_freq)) + mode |=3D TWSX_MODE_HS_MASK; + else + mode &=3D ~TWSX_MODE_HS_MASK; + octeon_i2c_writeq_flush(mode, i2c->twsi_base + MODE(i2c)); + } } =20 int octeon_i2c_init_lowlevel(struct octeon_i2c *i2c) diff --git a/drivers/i2c/busses/i2c-octeon-core.h b/drivers/i2c/busses/i2c-= octeon-core.h index 69bd62940f99eb786877026380cd1d02a4eaadb9..94c4401a4a567c3bbe15ddb219b= cb1a4fcb751bf 100644 --- a/drivers/i2c/busses/i2c-octeon-core.h +++ b/drivers/i2c/busses/i2c-octeon-core.h @@ -94,11 +94,18 @@ struct octeon_i2c_reg_offset { unsigned int sw_twsi; unsigned int twsi_int; unsigned int sw_twsi_ext; + unsigned int mode; }; =20 #define SW_TWSI(x) (x->roff.sw_twsi) #define TWSI_INT(x) (x->roff.twsi_int) #define SW_TWSI_EXT(x) (x->roff.sw_twsi_ext) +#define MODE(x) ((x)->roff.mode) + +/* Set REFCLK_SRC and HS_MODE in TWSX_MODE register */ +#define TWSX_MODE_REFCLK_SRC BIT(4) +#define TWSX_MODE_HS_MODE BIT(0) +#define TWSX_MODE_HS_MASK (TWSX_MODE_REFCLK_SRC | TWSX_MODE_HS_MODE) =20 struct octeon_i2c { wait_queue_head_t queue; @@ -213,6 +220,7 @@ static inline void octeon_i2c_write_int(struct octeon_i= 2c *i2c, u64 data) octeon_i2c_writeq_flush(data, i2c->twsi_base + TWSI_INT(i2c)); } =20 +#define IS_LS_FREQ(twsi_freq) ((twsi_freq) <=3D 400000) #define PCI_SUBSYS_DEVID_9XXX 0xB #define PCI_SUBSYS_MASK GENMASK(15, 12) /** diff --git a/drivers/i2c/busses/i2c-thunderx-pcidrv.c b/drivers/i2c/busses/= i2c-thunderx-pcidrv.c index 75569774003857dc984e8540ef8f4d1bb084cfb0..31f11b77ab663626967c86086a0= 3213876bf4a07 100644 --- a/drivers/i2c/busses/i2c-thunderx-pcidrv.c +++ b/drivers/i2c/busses/i2c-thunderx-pcidrv.c @@ -166,6 +166,7 @@ static int thunder_i2c_probe_pci(struct pci_dev *pdev, i2c->roff.sw_twsi =3D 0x1000; i2c->roff.twsi_int =3D 0x1010; i2c->roff.sw_twsi_ext =3D 0x1018; + i2c->roff.mode =3D 0x1038; =20 i2c->dev =3D dev; pci_set_drvdata(pdev, i2c); @@ -210,7 +211,7 @@ static int thunder_i2c_probe_pci(struct pci_dev *pdev, * For OcteonTX2 chips, set reference frequency to 100MHz * as refclk_src in TWSI_MODE register defaults to 100MHz. */ - if (octeon_i2c_is_otx2(pdev)) + if (octeon_i2c_is_otx2(pdev) && IS_LS_FREQ(i2c->twsi_freq)) i2c->sys_freq =3D OTX2_REF_FREQ_DEFAULT; octeon_i2c_set_clock(i2c); =20 --=20 2.43.0 From nobody Sat May 18 04:30:16 2024 Received: from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com [67.231.156.173]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 7F1BA481B7; Tue, 23 Apr 2024 07:46:48 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=67.231.156.173 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; 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Tue, 23 Apr 2024 00:46:45 -0700 (PDT) Received: from DC5-EXCH05.marvell.com (10.69.176.209) by DC5-EXCH05.marvell.com (10.69.176.209) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.4; Tue, 23 Apr 2024 00:46:43 -0700 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH05.marvell.com (10.69.176.209) with Microsoft SMTP Server id 15.2.1544.4 via Frontend Transport; Tue, 23 Apr 2024 00:46:43 -0700 Received: from Dell2s-9.sclab.marvell.com (unknown [10.110.150.250]) by maili.marvell.com (Postfix) with ESMTP id 8321D3F7051; Tue, 23 Apr 2024 00:46:43 -0700 (PDT) From: Piyush Malgujar To: , , CC: , , , Piyush Malgujar Subject: [PATCH v7 3/5] i2c: octeon: Add platform prefix to macros Date: Tue, 23 Apr 2024 00:46:06 -0700 Message-ID: <20240423074618.3278609-4-pmalgujar@marvell.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240423074618.3278609-1-pmalgujar@marvell.com> References: <20240423074618.3278609-1-pmalgujar@marvell.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Proofpoint-ORIG-GUID: in0PuS3VnhcOZRurVuCcPfL3CNCb2i5d X-Proofpoint-GUID: in0PuS3VnhcOZRurVuCcPfL3CNCb2i5d X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1011,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2024-04-23_04,2024-04-22_01,2023-05-22_02 Content-Type: text/plain; charset="utf-8" The macros for TWSI register's offset are generically named, rename them to be platform specific macros by adding 'OCTEON_REG' as prefix. Signed-off-by: Piyush Malgujar --- drivers/i2c/busses/i2c-octeon-core.c | 36 ++++++++++++++-------------- drivers/i2c/busses/i2c-octeon-core.h | 26 ++++++++++---------- 2 files changed, 31 insertions(+), 31 deletions(-) diff --git a/drivers/i2c/busses/i2c-octeon-core.c b/drivers/i2c/busses/i2c-= octeon-core.c index 86be597866f81c1bce54563047e14d099743f593..76a5ec100d3039b840ba28ae7a8= 17da447923d4f 100644 --- a/drivers/i2c/busses/i2c-octeon-core.c +++ b/drivers/i2c/busses/i2c-octeon-core.c @@ -85,7 +85,7 @@ static int octeon_i2c_wait(struct octeon_i2c *i2c) =20 static bool octeon_i2c_hlc_test_valid(struct octeon_i2c *i2c) { - return (__raw_readq(i2c->twsi_base + SW_TWSI(i2c)) & SW_TWSI_V) =3D=3D 0; + return (__raw_readq(i2c->twsi_base + OCTEON_REG_SW_TWSI(i2c)) & SW_TWSI_V= ) =3D=3D 0; } =20 static void octeon_i2c_hlc_int_clear(struct octeon_i2c *i2c) @@ -185,10 +185,10 @@ static int octeon_i2c_check_status(struct octeon_i2c = *i2c, int final_read) =20 /* * This is ugly... in HLC mode the status is not in the status register - * but in the lower 8 bits of SW_TWSI. + * but in the lower 8 bits of OCTEON_REG_SW_TWSI. */ if (i2c->hlc_enabled) - stat =3D __raw_readq(i2c->twsi_base + SW_TWSI(i2c)); + stat =3D __raw_readq(i2c->twsi_base + OCTEON_REG_SW_TWSI(i2c)); else stat =3D octeon_i2c_stat_read(i2c); =20 @@ -424,12 +424,12 @@ static int octeon_i2c_hlc_read(struct octeon_i2c *i2c= , struct i2c_msg *msgs) else cmd |=3D SW_TWSI_OP_7; =20 - octeon_i2c_writeq_flush(cmd, i2c->twsi_base + SW_TWSI(i2c)); + octeon_i2c_writeq_flush(cmd, i2c->twsi_base + OCTEON_REG_SW_TWSI(i2c)); ret =3D octeon_i2c_hlc_wait(i2c); if (ret) goto err; =20 - cmd =3D __raw_readq(i2c->twsi_base + SW_TWSI(i2c)); + cmd =3D __raw_readq(i2c->twsi_base + OCTEON_REG_SW_TWSI(i2c)); if ((cmd & SW_TWSI_R) =3D=3D 0) return octeon_i2c_check_status(i2c, false); =20 @@ -437,7 +437,7 @@ static int octeon_i2c_hlc_read(struct octeon_i2c *i2c, = struct i2c_msg *msgs) msgs[0].buf[j] =3D (cmd >> (8 * i)) & 0xff; =20 if (msgs[0].len > 4) { - cmd =3D __raw_readq(i2c->twsi_base + SW_TWSI_EXT(i2c)); + cmd =3D __raw_readq(i2c->twsi_base + OCTEON_REG_SW_TWSI_EXT(i2c)); for (i =3D 0; i < msgs[0].len - 4 && i < 4; i++, j--) msgs[0].buf[j] =3D (cmd >> (8 * i)) & 0xff; } @@ -474,15 +474,15 @@ static int octeon_i2c_hlc_write(struct octeon_i2c *i2= c, struct i2c_msg *msgs) =20 for (i =3D 0; i < msgs[0].len - 4 && i < 4; i++, j--) ext |=3D (u64)msgs[0].buf[j] << (8 * i); - octeon_i2c_writeq_flush(ext, i2c->twsi_base + SW_TWSI_EXT(i2c)); + octeon_i2c_writeq_flush(ext, i2c->twsi_base + OCTEON_REG_SW_TWSI_EXT(i2c= )); } =20 - octeon_i2c_writeq_flush(cmd, i2c->twsi_base + SW_TWSI(i2c)); + octeon_i2c_writeq_flush(cmd, i2c->twsi_base + OCTEON_REG_SW_TWSI(i2c)); ret =3D octeon_i2c_hlc_wait(i2c); if (ret) goto err; =20 - cmd =3D __raw_readq(i2c->twsi_base + SW_TWSI(i2c)); + cmd =3D __raw_readq(i2c->twsi_base + OCTEON_REG_SW_TWSI(i2c)); if ((cmd & SW_TWSI_R) =3D=3D 0) return octeon_i2c_check_status(i2c, false); =20 @@ -515,19 +515,19 @@ static int octeon_i2c_hlc_comp_read(struct octeon_i2c= *i2c, struct i2c_msg *msgs cmd |=3D SW_TWSI_EIA; ext =3D (u64)msgs[0].buf[0] << SW_TWSI_IA_SHIFT; cmd |=3D (u64)msgs[0].buf[1] << SW_TWSI_IA_SHIFT; - octeon_i2c_writeq_flush(ext, i2c->twsi_base + SW_TWSI_EXT(i2c)); + octeon_i2c_writeq_flush(ext, i2c->twsi_base + OCTEON_REG_SW_TWSI_EXT(i2c= )); } else { cmd |=3D (u64)msgs[0].buf[0] << SW_TWSI_IA_SHIFT; } =20 octeon_i2c_hlc_int_clear(i2c); - octeon_i2c_writeq_flush(cmd, i2c->twsi_base + SW_TWSI(i2c)); + octeon_i2c_writeq_flush(cmd, i2c->twsi_base + OCTEON_REG_SW_TWSI(i2c)); =20 ret =3D octeon_i2c_hlc_wait(i2c); if (ret) goto err; =20 - cmd =3D __raw_readq(i2c->twsi_base + SW_TWSI(i2c)); + cmd =3D __raw_readq(i2c->twsi_base + OCTEON_REG_SW_TWSI(i2c)); if ((cmd & SW_TWSI_R) =3D=3D 0) return octeon_i2c_check_status(i2c, false); =20 @@ -535,7 +535,7 @@ static int octeon_i2c_hlc_comp_read(struct octeon_i2c *= i2c, struct i2c_msg *msgs msgs[1].buf[j] =3D (cmd >> (8 * i)) & 0xff; =20 if (msgs[1].len > 4) { - cmd =3D __raw_readq(i2c->twsi_base + SW_TWSI_EXT(i2c)); + cmd =3D __raw_readq(i2c->twsi_base + OCTEON_REG_SW_TWSI_EXT(i2c)); for (i =3D 0; i < msgs[1].len - 4 && i < 4; i++, j--) msgs[1].buf[j] =3D (cmd >> (8 * i)) & 0xff; } @@ -582,16 +582,16 @@ static int octeon_i2c_hlc_comp_write(struct octeon_i2= c *i2c, struct i2c_msg *msg set_ext =3D true; } if (set_ext) - octeon_i2c_writeq_flush(ext, i2c->twsi_base + SW_TWSI_EXT(i2c)); + octeon_i2c_writeq_flush(ext, i2c->twsi_base + OCTEON_REG_SW_TWSI_EXT(i2c= )); =20 octeon_i2c_hlc_int_clear(i2c); - octeon_i2c_writeq_flush(cmd, i2c->twsi_base + SW_TWSI(i2c)); + octeon_i2c_writeq_flush(cmd, i2c->twsi_base + OCTEON_REG_SW_TWSI(i2c)); =20 ret =3D octeon_i2c_hlc_wait(i2c); if (ret) goto err; =20 - cmd =3D __raw_readq(i2c->twsi_base + SW_TWSI(i2c)); + cmd =3D __raw_readq(i2c->twsi_base + OCTEON_REG_SW_TWSI(i2c)); if ((cmd & SW_TWSI_R) =3D=3D 0) return octeon_i2c_check_status(i2c, false); =20 @@ -737,13 +737,13 @@ void octeon_i2c_set_clock(struct octeon_i2c *i2c) if (is_plat_otx2) { u64 mode; =20 - mode =3D __raw_readq(i2c->twsi_base + MODE(i2c)); + mode =3D __raw_readq(i2c->twsi_base + OCTEON_REG_MODE(i2c)); /* Set REFCLK_SRC and HS_MODE in TWSX_MODE register */ if (!IS_LS_FREQ(i2c->twsi_freq)) mode |=3D TWSX_MODE_HS_MASK; else mode &=3D ~TWSX_MODE_HS_MASK; - octeon_i2c_writeq_flush(mode, i2c->twsi_base + MODE(i2c)); + octeon_i2c_writeq_flush(mode, i2c->twsi_base + OCTEON_REG_MODE(i2c)); } } =20 diff --git a/drivers/i2c/busses/i2c-octeon-core.h b/drivers/i2c/busses/i2c-= octeon-core.h index 94c4401a4a567c3bbe15ddb219bcb1a4fcb751bf..39481e23e36fad098cf72dfd764= e368e778f2840 100644 --- a/drivers/i2c/busses/i2c-octeon-core.h +++ b/drivers/i2c/busses/i2c-octeon-core.h @@ -97,10 +97,10 @@ struct octeon_i2c_reg_offset { unsigned int mode; }; =20 -#define SW_TWSI(x) (x->roff.sw_twsi) -#define TWSI_INT(x) (x->roff.twsi_int) -#define SW_TWSI_EXT(x) (x->roff.sw_twsi_ext) -#define MODE(x) ((x)->roff.mode) +#define OCTEON_REG_SW_TWSI(x) ((x)->roff.sw_twsi) +#define OCTEON_REG_TWSI_INT(x) ((x)->roff.twsi_int) +#define OCTEON_REG_SW_TWSI_EXT(x) ((x)->roff.sw_twsi_ext) +#define OCTEON_REG_MODE(x) ((x)->roff.mode) =20 /* Set REFCLK_SRC and HS_MODE in TWSX_MODE register */ #define TWSX_MODE_REFCLK_SRC BIT(4) @@ -143,16 +143,16 @@ static inline void octeon_i2c_writeq_flush(u64 val, v= oid __iomem *addr) * @eop_reg: Register selector * @data: Value to be written * - * The I2C core registers are accessed indirectly via the SW_TWSI CSR. + * The I2C core registers are accessed indirectly via the OCTEON_REG_SW_TW= SI CSR. */ static inline void octeon_i2c_reg_write(struct octeon_i2c *i2c, u64 eop_re= g, u8 data) { int tries =3D 1000; u64 tmp; =20 - __raw_writeq(SW_TWSI_V | eop_reg | data, i2c->twsi_base + SW_TWSI(i2c)); + __raw_writeq(SW_TWSI_V | eop_reg | data, i2c->twsi_base + OCTEON_REG_SW_T= WSI(i2c)); do { - tmp =3D __raw_readq(i2c->twsi_base + SW_TWSI(i2c)); + tmp =3D __raw_readq(i2c->twsi_base + OCTEON_REG_SW_TWSI(i2c)); if (--tries < 0) return; } while ((tmp & SW_TWSI_V) !=3D 0); @@ -178,9 +178,9 @@ static inline int octeon_i2c_reg_read(struct octeon_i2c= *i2c, u64 eop_reg, int tries =3D 1000; u64 tmp; =20 - __raw_writeq(SW_TWSI_V | eop_reg | SW_TWSI_R, i2c->twsi_base + SW_TWSI(i2= c)); + __raw_writeq(SW_TWSI_V | eop_reg | SW_TWSI_R, i2c->twsi_base + OCTEON_REG= _SW_TWSI(i2c)); do { - tmp =3D __raw_readq(i2c->twsi_base + SW_TWSI(i2c)); + tmp =3D __raw_readq(i2c->twsi_base + OCTEON_REG_SW_TWSI(i2c)); if (--tries < 0) { /* signal that the returned data is invalid */ if (error) @@ -200,24 +200,24 @@ static inline int octeon_i2c_reg_read(struct octeon_i= 2c *i2c, u64 eop_reg, octeon_i2c_reg_read(i2c, SW_TWSI_EOP_TWSI_STAT, NULL) =20 /** - * octeon_i2c_read_int - read the TWSI_INT register + * octeon_i2c_read_int - read the OCTEON_REG_TWSI_INT register * @i2c: The struct octeon_i2c * * Returns the value of the register. */ static inline u64 octeon_i2c_read_int(struct octeon_i2c *i2c) { - return __raw_readq(i2c->twsi_base + TWSI_INT(i2c)); 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charset="utf-8" From: Suneel Garapati Add watchdog timeout handling to cater to the unhandled warnings seen during validation on boards with different I2C slaves. This status code reflects the state that controller couldn't receive any response from slave while being in non-idle state and HW recommends to reset before any further bus access. Signed-off-by: Suneel Garapati Signed-off-by: Piyush Malgujar Acked-by: Andi Shyti --- drivers/i2c/busses/i2c-octeon-core.c | 8 ++++++++ drivers/i2c/busses/i2c-octeon-core.h | 4 ++++ 2 files changed, 12 insertions(+) diff --git a/drivers/i2c/busses/i2c-octeon-core.c b/drivers/i2c/busses/i2c-= octeon-core.c index 76a5ec100d3039b840ba28ae7a817da447923d4f..5b7b942141e725c7f9071c217c7= 28efce067cee6 100644 --- a/drivers/i2c/busses/i2c-octeon-core.c +++ b/drivers/i2c/busses/i2c-octeon-core.c @@ -182,6 +182,7 @@ static int octeon_i2c_hlc_wait(struct octeon_i2c *i2c) static int octeon_i2c_check_status(struct octeon_i2c *i2c, int final_read) { u8 stat; + u64 mode; =20 /* * This is ugly... in HLC mode the status is not in the status register @@ -244,6 +245,13 @@ static int octeon_i2c_check_status(struct octeon_i2c *= i2c, int final_read) case STAT_RXADDR_NAK: case STAT_AD2W_NAK: return -ENXIO; + + case STAT_WDOG_TOUT: + mode =3D __raw_readq(i2c->twsi_base + OCTEON_REG_MODE(i2c)); + /* Set BUS_MON_RST to reset bus monitor */ + mode |=3D BUS_MON_RST_MASK; + octeon_i2c_writeq_flush(mode, i2c->twsi_base + OCTEON_REG_MODE(i2c)); + return -EIO; default: dev_err(i2c->dev, "unhandled state: %d\n", stat); return -EIO; diff --git a/drivers/i2c/busses/i2c-octeon-core.h b/drivers/i2c/busses/i2c-= octeon-core.h index 39481e23e36fad098cf72dfd764e368e778f2840..7af01864da7522fc9485511e1fe= b184e8659c74f 100644 --- a/drivers/i2c/busses/i2c-octeon-core.h +++ b/drivers/i2c/busses/i2c-octeon-core.h @@ -73,6 +73,7 @@ #define STAT_SLAVE_ACK 0xC8 #define STAT_AD2W_ACK 0xD0 #define STAT_AD2W_NAK 0xD8 +#define STAT_WDOG_TOUT 0xF0 #define STAT_IDLE 0xF8 =20 /* TWSI_INT values */ @@ -107,6 +108,9 @@ struct octeon_i2c_reg_offset { #define TWSX_MODE_HS_MODE BIT(0) #define TWSX_MODE_HS_MASK (TWSX_MODE_REFCLK_SRC | TWSX_MODE_HS_MODE) =20 +/* Set BUS_MON_RST to reset bus monitor */ +#define BUS_MON_RST_MASK BIT(3) + struct octeon_i2c { wait_queue_head_t queue; struct i2c_adapter adap; --=20 2.43.0 From nobody Sat May 18 04:30:16 2024 Received: from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com [67.231.156.173]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A386653398; 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charset="utf-8" Read the ioclk property as reference clock if sclk not present in acpi table to make it SOC agnostic. In case, it's not populated from dts/acpi table, use the default clock of 800 MHz which is optimal in either case of sclk/ioclk. Signed-off-by: Piyush Malgujar Acked-by: Andi Shyti --- drivers/i2c/busses/i2c-thunderx-pcidrv.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/drivers/i2c/busses/i2c-thunderx-pcidrv.c b/drivers/i2c/busses/= i2c-thunderx-pcidrv.c index 31f11b77ab663626967c86086a03213876bf4a07..32d0e3930b675484138084e1bbe= d2e7cf898e1e1 100644 --- a/drivers/i2c/busses/i2c-thunderx-pcidrv.c +++ b/drivers/i2c/busses/i2c-thunderx-pcidrv.c @@ -27,7 +27,7 @@ =20 #define PCI_DEVICE_ID_THUNDER_TWSI 0xa012 =20 -#define SYS_FREQ_DEFAULT 700000000 +#define SYS_FREQ_DEFAULT 800000000 #define OTX2_REF_FREQ_DEFAULT 100000000 =20 #define TWSI_INT_ENA_W1C 0x1028 @@ -100,7 +100,8 @@ static void thunder_i2c_clock_enable(struct device *dev= , struct octeon_i2c *i2c) i2c->sys_freq =3D clk_get_rate(i2c->clk); } else { /* ACPI */ - device_property_read_u32(dev, "sclk", &i2c->sys_freq); + if (device_property_read_u32(dev, "sclk", &i2c->sys_freq)) + device_property_read_u32(dev, "ioclk", &i2c->sys_freq); } =20 skip: --=20 2.43.0