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Reviewed-by: Rob Herring Signed-off-by: Sibi Sankar --- V3: * Fix Maintainer info in cpucp mbox bindings. [Bjorn] .../bindings/mailbox/qcom,cpucp-mbox.yaml | 49 +++++++++++++++++++ 1 file changed, 49 insertions(+) create mode 100644 Documentation/devicetree/bindings/mailbox/qcom,cpucp-mb= ox.yaml diff --git a/Documentation/devicetree/bindings/mailbox/qcom,cpucp-mbox.yaml= b/Documentation/devicetree/bindings/mailbox/qcom,cpucp-mbox.yaml new file mode 100644 index 000000000000..f7342d04beec --- /dev/null +++ b/Documentation/devicetree/bindings/mailbox/qcom,cpucp-mbox.yaml @@ -0,0 +1,49 @@ +# SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/mailbox/qcom,cpucp-mbox.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Technologies, Inc. CPUCP Mailbox Controller + +maintainers: + - Sibi Sankar + +description: + The CPUSS Control Processor (CPUCP) mailbox controller enables communica= tion + between AP and CPUCP by acting as a doorbell between them. + +properties: + compatible: + items: + - const: qcom,x1e80100-cpucp-mbox + + reg: + items: + - description: CPUCP rx register region + - description: CPUCP tx register region + + interrupts: + maxItems: 1 + + "#mbox-cells": + const: 1 + +required: + - compatible + - reg + - interrupts + - "#mbox-cells" + +additionalProperties: false + +examples: + - | + #include + + mailbox@17430000 { + compatible =3D "qcom,x1e80100-cpucp-mbox"; + reg =3D <0x17430000 0x10000>, <0x18830000 0x10000>; + interrupts =3D ; + #mbox-cells =3D <1>; + }; --=20 2.34.1 From nobody Thu Jun 13 11:28:09 2024 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 0217C154C12; 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charset="utf-8" Add support for CPUSS Control Processor (CPUCP) mailbox controller, this driver enables communication between AP and CPUCP by acting as a doorbell between them. Reviewed-by: Dmitry Baryshkov Signed-off-by: Sibi Sankar --- V3: * Fix copyright info in cpucp driver. [Bjorn] * Drop unused APSS_CPUCP_TX_MBOX_IDR, value init and drv_data. [Bjorn/Dmitr= y] * Convert to lower case hex. [Bjorn] * Convert irq and dev to local variables. [Bjorn] * Replace for and if with for_each_set_bit. [Bjorn] * Document the need for spinlock. [Bjorn] * Add space after " for aesthetics. [Bjorn] * Include io.h and re-order platform_device.h * Use GENMASK_ULL to generate APSS_CPUCP_RX_MBOX_CMD_MASK. * Pick Rb. drivers/mailbox/Kconfig | 8 ++ drivers/mailbox/Makefile | 2 + drivers/mailbox/qcom-cpucp-mbox.c | 179 ++++++++++++++++++++++++++++++ 3 files changed, 189 insertions(+) create mode 100644 drivers/mailbox/qcom-cpucp-mbox.c diff --git a/drivers/mailbox/Kconfig b/drivers/mailbox/Kconfig index 42940108a187..23741a6f054e 100644 --- a/drivers/mailbox/Kconfig +++ b/drivers/mailbox/Kconfig @@ -273,6 +273,14 @@ config SPRD_MBOX to send message between application processors and MCU. Say Y here if you want to build the Spreatrum mailbox controller driver. =20 +config QCOM_CPUCP_MBOX + tristate "Qualcomm Technologies, Inc. CPUCP mailbox driver" + depends on ARCH_QCOM || COMPILE_TEST + help + Qualcomm Technologies, Inc. CPUSS Control Processor (CPUCP) mailbox + controller driver enables communication between AP and CPUCP. Say + Y here if you want to build this driver. + config QCOM_IPCC tristate "Qualcomm Technologies, Inc. IPCC driver" depends on ARCH_QCOM || COMPILE_TEST diff --git a/drivers/mailbox/Makefile b/drivers/mailbox/Makefile index 18793e6caa2f..53b512800bde 100644 --- a/drivers/mailbox/Makefile +++ b/drivers/mailbox/Makefile @@ -59,4 +59,6 @@ obj-$(CONFIG_SUN6I_MSGBOX) +=3D sun6i-msgbox.o =20 obj-$(CONFIG_SPRD_MBOX) +=3D sprd-mailbox.o =20 +obj-$(CONFIG_QCOM_CPUCP_MBOX) +=3D qcom-cpucp-mbox.o + obj-$(CONFIG_QCOM_IPCC) +=3D qcom-ipcc.o diff --git a/drivers/mailbox/qcom-cpucp-mbox.c b/drivers/mailbox/qcom-cpucp= -mbox.c new file mode 100644 index 000000000000..78d0872a0e33 --- /dev/null +++ b/drivers/mailbox/qcom-cpucp-mbox.c @@ -0,0 +1,179 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2024, Qualcomm Innovation Center, Inc. All rights reserve= d. + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +#define APSS_CPUCP_IPC_CHAN_SUPPORTED 3 +#define APSS_CPUCP_MBOX_CMD_OFF 0x4 + +/* Tx Registers */ +#define APSS_CPUCP_TX_MBOX_CMD(i) (0x100 + ((i) * 8)) + +/* Rx Registers */ +#define APSS_CPUCP_RX_MBOX_CMD(i) (0x100 + ((i) * 8)) +#define APSS_CPUCP_RX_MBOX_MAP 0x4000 +#define APSS_CPUCP_RX_MBOX_STAT 0x4400 +#define APSS_CPUCP_RX_MBOX_CLEAR 0x4800 +#define APSS_CPUCP_RX_MBOX_EN 0x4c00 +#define APSS_CPUCP_RX_MBOX_CMD_MASK GENMASK_ULL(63, 0) + +/** + * struct qcom_cpucp_mbox - Holder for the mailbox driver + * @chans: The mailbox channel + * @mbox: The mailbox controller + * @tx_base: Base address of the CPUCP tx registers + * @rx_base: Base address of the CPUCP rx registers + */ +struct qcom_cpucp_mbox { + struct mbox_chan chans[APSS_CPUCP_IPC_CHAN_SUPPORTED]; + struct mbox_controller mbox; + void __iomem *tx_base; + void __iomem *rx_base; +}; + +static inline int channel_number(struct mbox_chan *chan) +{ + return chan - chan->mbox->chans; +} + +static irqreturn_t qcom_cpucp_mbox_irq_fn(int irq, void *data) +{ + struct qcom_cpucp_mbox *cpucp =3D data; + struct mbox_chan *chan; + unsigned long flags; + u64 status; + u32 val; + int i; + + status =3D readq(cpucp->rx_base + APSS_CPUCP_RX_MBOX_STAT); + + for_each_set_bit(i, (unsigned long *)&status, APSS_CPUCP_IPC_CHAN_SUPPORT= ED) { + val =3D readl(cpucp->rx_base + APSS_CPUCP_RX_MBOX_CMD(i) + APSS_CPUCP_MB= OX_CMD_OFF); + chan =3D &cpucp->chans[i]; + /* Provide mutual exclusion with changes to chan->cl */ + spin_lock_irqsave(&chan->lock, flags); + if (chan->cl) + mbox_chan_received_data(chan, &val); + writeq(BIT(i), cpucp->rx_base + APSS_CPUCP_RX_MBOX_CLEAR); + spin_unlock_irqrestore(&chan->lock, flags); + } + + return IRQ_HANDLED; +} + +static int qcom_cpucp_mbox_startup(struct mbox_chan *chan) +{ + struct qcom_cpucp_mbox *cpucp =3D container_of(chan->mbox, struct qcom_cp= ucp_mbox, mbox); + unsigned long chan_id =3D channel_number(chan); + u64 val; + + val =3D readq(cpucp->rx_base + APSS_CPUCP_RX_MBOX_EN); + val |=3D BIT(chan_id); + writeq(val, cpucp->rx_base + APSS_CPUCP_RX_MBOX_EN); + + return 0; +} + +static void qcom_cpucp_mbox_shutdown(struct mbox_chan *chan) +{ + struct qcom_cpucp_mbox *cpucp =3D container_of(chan->mbox, struct qcom_cp= ucp_mbox, mbox); + unsigned long chan_id =3D channel_number(chan); + u64 val; + + val =3D readq(cpucp->rx_base + APSS_CPUCP_RX_MBOX_EN); + val &=3D ~BIT(chan_id); + writeq(val, cpucp->rx_base + APSS_CPUCP_RX_MBOX_EN); +} + +static int qcom_cpucp_mbox_send_data(struct mbox_chan *chan, void *data) +{ + struct qcom_cpucp_mbox *cpucp =3D container_of(chan->mbox, struct qcom_cp= ucp_mbox, mbox); + unsigned long chan_id =3D channel_number(chan); + u32 *val =3D data; + + writel(*val, cpucp->tx_base + APSS_CPUCP_TX_MBOX_CMD(chan_id) + APSS_CPUC= P_MBOX_CMD_OFF); + + return 0; +} + +static const struct mbox_chan_ops qcom_cpucp_mbox_chan_ops =3D { + .startup =3D qcom_cpucp_mbox_startup, + .send_data =3D qcom_cpucp_mbox_send_data, + .shutdown =3D qcom_cpucp_mbox_shutdown +}; + +static int qcom_cpucp_mbox_probe(struct platform_device *pdev) +{ + struct device *dev =3D &pdev->dev; + struct qcom_cpucp_mbox *cpucp; + struct mbox_controller *mbox; + int irq, ret; + + cpucp =3D devm_kzalloc(dev, sizeof(*cpucp), GFP_KERNEL); + if (!cpucp) + return -ENOMEM; + + cpucp->rx_base =3D devm_of_iomap(dev, dev->of_node, 0, NULL); + if (IS_ERR(cpucp->rx_base)) + return PTR_ERR(cpucp->rx_base); + + cpucp->tx_base =3D devm_of_iomap(dev, dev->of_node, 1, NULL); + if (IS_ERR(cpucp->tx_base)) + return PTR_ERR(cpucp->tx_base); + + writeq(0, cpucp->rx_base + APSS_CPUCP_RX_MBOX_EN); + writeq(0, cpucp->rx_base + APSS_CPUCP_RX_MBOX_CLEAR); + writeq(0, cpucp->rx_base + APSS_CPUCP_RX_MBOX_MAP); + + irq =3D platform_get_irq(pdev, 0); + if (irq < 0) + return irq; + + ret =3D devm_request_irq(dev, irq, qcom_cpucp_mbox_irq_fn, + IRQF_TRIGGER_HIGH, "apss_cpucp_mbox", cpucp); + if (ret < 0) + return dev_err_probe(dev, ret, "Failed to register irq: %d\n", irq); + + writeq(APSS_CPUCP_RX_MBOX_CMD_MASK, cpucp->rx_base + APSS_CPUCP_RX_MBOX_M= AP); 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charset="utf-8" Resize the GICR register region as it currently seeps into the CPU Control Processor mailbox RX region. Fixes: af16b00578a7 ("arm64: dts: qcom: Add base X1E80100 dtsi and the QCP = dts") Reviewed-by: Dmitry Baryshkov Signed-off-by: Sibi Sankar --- V3: * Fix err in calc and add fixes tag. [Bjorn] arch/arm64/boot/dts/qcom/x1e80100.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/x1e80100.dtsi b/arch/arm64/boot/dts/q= com/x1e80100.dtsi index 5f90a0b3c016..c48b3fdc550b 100644 --- a/arch/arm64/boot/dts/qcom/x1e80100.dtsi +++ b/arch/arm64/boot/dts/qcom/x1e80100.dtsi @@ -4947,7 +4947,7 @@ apps_smmu: iommu@15000000 { intc: interrupt-controller@17000000 { compatible =3D "arm,gic-v3"; reg =3D <0 0x17000000 0 0x10000>, /* GICD */ - <0 0x17080000 0 0x480000>; /* GICR * 12 */ + <0 0x17080000 0 0x300000>; /* GICR * 12 */ =20 interrupts =3D ; =20 --=20 2.34.1 From nobody Thu Jun 13 11:28:09 2024 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 579AA155326; Mon, 22 Apr 2024 16:41:27 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; 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charset="utf-8" Add the cpucp mailbox and sram nodes required by SCMI perf protocol on X1E80100 SoCs. Signed-off-by: Sibi Sankar --- arch/arm64/boot/dts/qcom/x1e80100.dtsi | 26 ++++++++++++++++++++++++++ 1 file changed, 26 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/x1e80100.dtsi b/arch/arm64/boot/dts/q= com/x1e80100.dtsi index c48b3fdc550b..6dcd851f31b2 100644 --- a/arch/arm64/boot/dts/qcom/x1e80100.dtsi +++ b/arch/arm64/boot/dts/qcom/x1e80100.dtsi @@ -4972,6 +4972,13 @@ gic_its: msi-controller@17040000 { }; }; =20 + cpucp_mbox: mailbox@17430000 { + compatible =3D "qcom,x1e80100-cpucp-mbox"; + reg =3D <0 0x17430000 0 0x10000>, <0 0x18830000 0 0x10000>; + interrupts =3D ; + #mbox-cells =3D <1>; + }; + apps_rsc: rsc@17500000 { compatible =3D "qcom,rpmh-rsc"; reg =3D <0 0x17500000 0 0x10000>, @@ -5155,6 +5162,25 @@ frame@1780d000 { }; }; =20 + sram: sram@18b4e000 { + compatible =3D "mmio-sram"; + reg =3D <0x0 0x18b4e000 0x0 0x400>; + + #address-cells =3D <1>; + #size-cells =3D <1>; + ranges =3D <0x0 0x0 0x18b4e000 0x400>; + + cpu_scp_lpri0: scp-sram-section@0 { + compatible =3D "arm,scmi-shmem"; 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charset="utf-8" Enable cpufreq on X1E80100 SoCs through the SCMI perf protocol node. Signed-off-by: Sibi Sankar --- arch/arm64/boot/dts/qcom/x1e80100.dtsi | 63 ++++++++++++++++---------- 1 file changed, 39 insertions(+), 24 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/x1e80100.dtsi b/arch/arm64/boot/dts/q= com/x1e80100.dtsi index 6dcd851f31b2..96d1c5bab13f 100644 --- a/arch/arm64/boot/dts/qcom/x1e80100.dtsi +++ b/arch/arm64/boot/dts/qcom/x1e80100.dtsi @@ -69,8 +69,8 @@ CPU0: cpu@0 { reg =3D <0x0 0x0>; enable-method =3D "psci"; next-level-cache =3D <&L2_0>; - power-domains =3D <&CPU_PD0>; - power-domain-names =3D "psci"; + power-domains =3D <&CPU_PD0>, <&scmi_dvfs 0>; + power-domain-names =3D "psci", "perf"; cpu-idle-states =3D <&CLUSTER_C4>; =20 L2_0: l2-cache { @@ -86,8 +86,8 @@ CPU1: cpu@100 { reg =3D <0x0 0x100>; enable-method =3D "psci"; next-level-cache =3D <&L2_0>; - power-domains =3D <&CPU_PD1>; - power-domain-names =3D "psci"; + power-domains =3D <&CPU_PD1>, <&scmi_dvfs 0>; + power-domain-names =3D "psci", "perf"; cpu-idle-states =3D <&CLUSTER_C4>; }; =20 @@ -97,8 +97,8 @@ CPU2: cpu@200 { reg =3D <0x0 0x200>; enable-method =3D "psci"; next-level-cache =3D <&L2_0>; - power-domains =3D <&CPU_PD2>; - power-domain-names =3D "psci"; + power-domains =3D <&CPU_PD2>, <&scmi_dvfs 0>; + power-domain-names =3D "psci", "perf"; cpu-idle-states =3D <&CLUSTER_C4>; }; =20 @@ -108,8 +108,8 @@ CPU3: cpu@300 { reg =3D <0x0 0x300>; enable-method =3D "psci"; next-level-cache =3D <&L2_0>; - power-domains =3D <&CPU_PD3>; - power-domain-names =3D "psci"; + power-domains =3D <&CPU_PD3>, <&scmi_dvfs 0>; + power-domain-names =3D "psci", "perf"; cpu-idle-states =3D <&CLUSTER_C4>; }; =20 @@ -119,8 +119,8 @@ CPU4: cpu@10000 { reg =3D <0x0 0x10000>; enable-method =3D "psci"; next-level-cache =3D <&L2_1>; - power-domains =3D <&CPU_PD4>; - power-domain-names =3D "psci"; + power-domains =3D <&CPU_PD4>, <&scmi_dvfs 1>; + power-domain-names =3D "psci", "perf"; cpu-idle-states =3D <&CLUSTER_C4>; =20 L2_1: l2-cache { @@ -136,8 +136,8 @@ CPU5: cpu@10100 { reg =3D <0x0 0x10100>; enable-method =3D "psci"; next-level-cache =3D <&L2_1>; - power-domains =3D <&CPU_PD5>; - power-domain-names =3D "psci"; + power-domains =3D <&CPU_PD5>, <&scmi_dvfs 1>; + power-domain-names =3D "psci", "perf"; cpu-idle-states =3D <&CLUSTER_C4>; }; =20 @@ -147,8 +147,8 @@ CPU6: cpu@10200 { reg =3D <0x0 0x10200>; enable-method =3D "psci"; next-level-cache =3D <&L2_1>; - power-domains =3D <&CPU_PD6>; - power-domain-names =3D "psci"; + power-domains =3D <&CPU_PD6>, <&scmi_dvfs 1>; + power-domain-names =3D "psci", "perf"; cpu-idle-states =3D <&CLUSTER_C4>; }; =20 @@ -158,8 +158,8 @@ CPU7: cpu@10300 { reg =3D <0x0 0x10300>; enable-method =3D "psci"; next-level-cache =3D <&L2_1>; - power-domains =3D <&CPU_PD7>; - power-domain-names =3D "psci"; + power-domains =3D <&CPU_PD7>, <&scmi_dvfs 1>; + power-domain-names =3D "psci", "perf"; cpu-idle-states =3D <&CLUSTER_C4>; }; =20 @@ -169,8 +169,8 @@ CPU8: cpu@20000 { reg =3D <0x0 0x20000>; enable-method =3D "psci"; next-level-cache =3D <&L2_2>; - power-domains =3D <&CPU_PD8>; - power-domain-names =3D "psci"; + power-domains =3D <&CPU_PD8>, <&scmi_dvfs 2>; + power-domain-names =3D "psci", "perf"; cpu-idle-states =3D <&CLUSTER_C4>; =20 L2_2: l2-cache { @@ -186,8 +186,8 @@ CPU9: cpu@20100 { reg =3D <0x0 0x20100>; enable-method =3D "psci"; next-level-cache =3D <&L2_2>; - power-domains =3D <&CPU_PD9>; - power-domain-names =3D "psci"; + power-domains =3D <&CPU_PD9>, <&scmi_dvfs 2>; + power-domain-names =3D "psci", "perf"; cpu-idle-states =3D <&CLUSTER_C4>; }; =20 @@ -197,8 +197,8 @@ CPU10: cpu@20200 { reg =3D <0x0 0x20200>; enable-method =3D "psci"; next-level-cache =3D <&L2_2>; - power-domains =3D <&CPU_PD10>; - power-domain-names =3D "psci"; + power-domains =3D <&CPU_PD10>, <&scmi_dvfs 2>; + power-domain-names =3D "psci", "perf"; cpu-idle-states =3D <&CLUSTER_C4>; }; =20 @@ -208,8 +208,8 @@ CPU11: cpu@20300 { reg =3D <0x0 0x20300>; enable-method =3D "psci"; next-level-cache =3D <&L2_2>; - power-domains =3D <&CPU_PD11>; - power-domain-names =3D "psci"; + power-domains =3D <&CPU_PD11>, <&scmi_dvfs 2>; + power-domain-names =3D "psci", "perf"; cpu-idle-states =3D <&CLUSTER_C4>; }; =20 @@ -309,6 +309,21 @@ scm: scm { interconnects =3D <&aggre2_noc MASTER_CRYPTO QCOM_ICC_TAG_ALWAYS &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; }; + + scmi { + compatible =3D "arm,scmi"; + mboxes =3D <&cpucp_mbox 0>, <&cpucp_mbox 2>; + mbox-names =3D "tx", "rx"; + shmem =3D <&cpu_scp_lpri0>, <&cpu_scp_lpri1>; + + #address-cells =3D <1>; + #size-cells =3D <0>; + + scmi_dvfs: protocol@13 { + reg =3D <0x13>; + #power-domain-cells =3D <1>; + }; + }; }; =20 clk_virt: interconnect-0 { --=20 2.34.1