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AJvYcCX2PZn7saUzTkbhFUbxearjgCAsVLjOSCsniFcrP0W8fCitwTbIAk5LbVTp/LgK63uQsyE3bjC93/6NZQV0DWSqWdSMbGJapORqU2pX X-Gm-Message-State: AOJu0YxHg0mqKFQEXFyAgIAHGttTlBFfTP/mlIDyip8X9lGYXYwAoAbY 6zgwlBs4zHUucPros4lHGe+PGyiDatKUDmqeWFlrTxASRFhBcwY5oFf2829XIQE= X-Google-Smtp-Source: AGHT+IEaiQYP/KCYuI9CEUWUt/o7raG5CR1YU5Wdx2qsjoQUQGLPQpfFGt9Hb4m/Tvf1FuiO3Zy/nw== X-Received: by 2002:a05:6871:742a:b0:22e:8576:bcd8 with SMTP id nw42-20020a056871742a00b0022e8576bcd8mr11458913oac.42.1713776636107; Mon, 22 Apr 2024 02:03:56 -0700 (PDT) Received: from localhost.localdomain ([116.66.212.162]) by smtp.gmail.com with ESMTPSA id by42-20020a056a0205aa00b005fdd11c0874sm1919137pgb.64.2024.04.22.02.03.53 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 22 Apr 2024 02:03:55 -0700 (PDT) From: Cong Yang To: sam@ravnborg.org, neil.armstrong@linaro.org, daniel@ffwll.ch, dianders@chromium.org, linus.walleij@linaro.org, krzysztof.kozlowski+dt@linaro.org, robh+dt@kernel.org, conor+dt@kernel.org, airlied@gmail.com Cc: dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, xuxinxiong@huaqin.corp-partner.google.com, Cong Yang Subject: [PATCH v2 7/7] drm/panel: himax-hx83102: Support for IVO t109nw41 MIPI-DSI panel Date: Mon, 22 Apr 2024 17:03:10 +0800 Message-Id: <20240422090310.3311429-8-yangcong5@huaqin.corp-partner.google.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20240422090310.3311429-1-yangcong5@huaqin.corp-partner.google.com> References: <20240422090310.3311429-1-yangcong5@huaqin.corp-partner.google.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The IVO t109nw41 is a 11.0" WUXGA TFT LCD panel, use hx83102 controller which fits in nicely with the existing panel-himax-hx83102 driver. Hence, we add a new compatible with panel specific config. Signed-off-by: Cong Yang --- drivers/gpu/drm/panel/panel-himax-hx83102.c | 178 ++++++++++++++++++++ 1 file changed, 178 insertions(+) diff --git a/drivers/gpu/drm/panel/panel-himax-hx83102.c b/drivers/gpu/drm/= panel/panel-himax-hx83102.c index 963438a2b245..0aef1cc80dea 100644 --- a/drivers/gpu/drm/panel/panel-himax-hx83102.c +++ b/drivers/gpu/drm/panel/panel-himax-hx83102.c @@ -26,6 +26,7 @@ #define HX83102_SETPOWER 0xb1 #define HX83102_SETDISP 0xb2 #define HX83102_SETCYC 0xb4 +#define HX83102_UNKNOWN6 0xb6 #define HX83102_SETEXTC 0xb9 #define HX83102_SETMIPI 0xba #define HX83102_SETVDC 0xbc @@ -401,6 +402,152 @@ static int boe_nv110wum_init_cmd(struct hx83102 *ctx) return 0; }; =20 +static int ivo_t109nw41_init_cmd(struct hx83102 *ctx) +{ + struct mipi_dsi_device *dsi =3D ctx->dsi; + + msleep(60); + + mipi_dsi_dcs_write_seq(dsi, HX83102_SETEXTC, 0x83, 0x10, 0x21, 0x55, 0x00= ); + + mipi_dsi_dcs_write_seq(dsi, HX83102_SETPOWER, 0x2C, 0xED, 0xED, 0x27, 0xE= 7, 0x42, 0xF5, 0x39, + 0x36, 0x36, 0x36, 0x36, 0x32, 0x8B, 0x11, 0x65, 0x00, 0x88, 0xFA, = 0xFF, + 0xFF, 0x8F, 0xFF, 0x08, 0xD6, 0x33); + + mipi_dsi_dcs_write_seq(dsi, HX83102_SETDISP, 0x00, 0x47, 0xB0, 0x80, 0x00= , 0x12, 0x71, 0x3C, + 0xA3, 0x22, 0x20, 0x00, 0x00, 0x88, 0x01); + + mipi_dsi_dcs_write_seq(dsi, HX83102_SETCYC, 0x35, 0x35, 0x43, 0x43, 0x35,= 0x35, 0x30, 0x7A, + 0x30, 0x7A, 0x01, 0x9D); + + mipi_dsi_dcs_write_seq(dsi, HX83102_UNKNOWN6, 0x34, 0x34, 0x03); + + mipi_dsi_dcs_write_seq(dsi, HX83102_SETSPCCMD, 0xCD); + + mipi_dsi_dcs_write_seq(dsi, HX83102_SETMIPI, 0x84); + + mipi_dsi_dcs_write_seq(dsi, HX83102_SETSPCCMD, 0x3F); + + mipi_dsi_dcs_write_seq(dsi, HX83102_SETVDC, 0x1B, 0x04); + + mipi_dsi_dcs_write_seq(dsi, HX83102_UNKNOWN1, 0x20); + + mipi_dsi_dcs_write_seq(dsi, HX83102_SETPTBA, 0xFC, 0xC4); + + mipi_dsi_dcs_write_seq(dsi, HX83102_SETSTBA, 0x34, 0x34, 0x22, 0x11, 0x22= , 0xA0, 0x31, 0x08, + 0xF5, 0x03); + + mipi_dsi_dcs_write_seq(dsi, HX83102_SETSPCCMD, 0xCC); + + mipi_dsi_dcs_write_seq(dsi, HX83102_SETTCON, 0x80); + + mipi_dsi_dcs_write_seq(dsi, HX83102_SETSPCCMD, 0x3F); + + mipi_dsi_dcs_write_seq(dsi, HX83102_SETSPCCMD, 0xC6); + + mipi_dsi_dcs_write_seq(dsi, HX83102_SETRAMDMY, 0x97); + + mipi_dsi_dcs_write_seq(dsi, HX83102_SETSPCCMD, 0x3F); + + mipi_dsi_dcs_write_seq(dsi, HX83102_SETPWM, 0x00, 0x1E, 0x13, 0x88, 0x01); + + mipi_dsi_dcs_write_seq(dsi, HX83102_SETCLOCK, 0x08, 0x13, 0x07, 0x00, 0x0= F, 0x34); + + mipi_dsi_dcs_write_seq(dsi, HX83102_SETPANEL, 0x02, 0x03, 0x44); + + mipi_dsi_dcs_write_seq(dsi, HX83102_SETSPCCMD, 0xC4); + + mipi_dsi_dcs_write_seq(dsi, HX83102_SETCASCADE, 0x03); + + mipi_dsi_dcs_write_seq(dsi, HX83102_SETSPCCMD, 0x3F); + + mipi_dsi_dcs_write_seq(dsi, HX83102_SETPCTRL, 0x07, 0x06, 0x00, 0x02, 0x0= 4, 0x2C, 0xFF); + + mipi_dsi_dcs_write_seq(dsi, HX83102_SETGIP0, 0x06, 0x00, 0x00, 0x00, 0x00= , 0x08, 0x08, 0x08, + 0x08, 0x37, 0x07, 0x64, 0x7C, 0x11, 0x11, 0x03, 0x03, 0x32, 0x10, = 0x0E, + 0x00, 0x0E, 0x32, 0x17, 0x97, 0x07, 0x97, 0x32, 0x00, 0x02, 0x00, = 0x02, + 0x00, 0x00); + + mipi_dsi_dcs_write_seq(dsi, HX83102_SETGIP1, 0x25, 0x24, 0x25, 0x24, 0x18= , 0x18, 0x18, 0x18, + 0x07, 0x06, 0x07, 0x06, 0x05, 0x04, 0x05, 0x04, 0x03, 0x02, 0x03, = 0x02, + 0x01, 0x00, 0x01, 0x00, 0xA8, 0xA8, 0xA8, 0xA8, 0x29, 0x29, 0x29, = 0x29, + 0x21, 0x20, 0x21, 0x20, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, = 0x18); + + mipi_dsi_dcs_write_seq(dsi, HX83102_SETGIP3, 0xAA, 0xAA, 0xAA, 0xAA, 0xAA= , 0xA0, 0xAA, 0xAA, + 0xAA, 0xAA, 0xAA, 0xA0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, = 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, = 0x00, + 0x00, 0x00, 0x00, 0x00); + + mipi_dsi_dcs_write_seq(dsi, HX83102_SETTP1, 0x07, 0x10, 0x10, 0x1A, 0x26,= 0x9E, 0x00, 0x4F, + 0xA0, 0x14, 0x14, 0x00, 0x00, 0x00, 0x00, 0x12, 0x0A, 0x02, 0x02, = 0x00, + 0x33, 0x02, 0x04, 0x18, 0x01); + + mipi_dsi_dcs_write_seq(dsi, HX83102_SETBANK, 0x01); + + mipi_dsi_dcs_write_seq(dsi, HX83102_SETPOWER, 0x01, 0x7F, 0x11, 0xFD); + + mipi_dsi_dcs_write_seq(dsi, HX83102_SETCLOCK, 0x86); + + mipi_dsi_dcs_write_seq(dsi, HX83102_SETGIP3, 0x00, 0x00, 0x00, 0x00, 0x00= , 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0xAA, 0xAA, 0xAA, 0xAA, 0xAA, 0xA0, 0xAA, = 0xAA, + 0xAA, 0xAA, 0xAA, 0xA0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, = 0x00, + 0x00, 0x00, 0x00, 0x00); + + mipi_dsi_dcs_write_seq(dsi, HX83102_SETTP1, 0x02, 0x00, 0x2B, 0x01, 0x7E,= 0x0F, 0x7E, 0x10, + 0xA0, 0x00, 0x00, 0x77, 0x00, 0x00, 0x00); + + mipi_dsi_dcs_write_seq(dsi, HX83102_SETBANK, 0x02); + + mipi_dsi_dcs_write_seq(dsi, HX83102_SETPTBA, 0xF2); + + mipi_dsi_dcs_write_seq(dsi, HX83102_SETCLOCK, 0x03, 0x07, 0x00, 0x10, 0x7= 9); + + mipi_dsi_dcs_write_seq(dsi, HX83102_SETGIP3, 0xFF, 0xFF, 0xFF, 0xFF, 0xFA= , 0xA0, + 0xFF, 0xFF, 0xFF, 0xFF, 0xFA, 0xA0); + + mipi_dsi_dcs_write_seq(dsi, HX83102_SETTP1, 0xFE, 0x01, 0xFE, 0x01, 0xFE,= 0x01, 0x00, 0x00, + 0x00, 0x23, 0x00, 0x23, 0x81, 0x02, 0x40, 0x00, 0x20, 0x6E, 0x02, = 0x01, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00); + + mipi_dsi_dcs_write_seq(dsi, HX83102_SETBANK, 0x03); + + mipi_dsi_dcs_write_seq(dsi, HX83102_SETSPCCMD, 0xAA, 0xAA, 0xAA, 0xAA, 0x= AA, 0xA0, 0xAA, 0xAA, + 0xAA, 0xAA, 0xAA, 0xA0, 0xFF, 0xFF, 0xFF, 0xFF, 0xFA, 0xA0, 0xFF, = 0xFF, + 0xFF, 0xFF, 0xFA, 0xA0, 0xAA, 0xAA, 0xAA, 0xAA, 0xAA, 0xA0, 0xAA, = 0xAA, + 0xAA, 0xAA, 0xAA, 0xA0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, = 0x00, + 0x00, 0x00, 0x00, 0x00); + + mipi_dsi_dcs_write_seq(dsi, HX83102_SETSPCCMD, 0xC6); + + mipi_dsi_dcs_write_seq(dsi, HX83102_SETCYC, 0x03, 0xFF, 0xF8); + + mipi_dsi_dcs_write_seq(dsi, HX83102_SETSPCCMD, 0x3F); + + mipi_dsi_dcs_write_seq(dsi, HX83102_UNKNOWN5, 0x00); + + mipi_dsi_dcs_write_seq(dsi, HX83102_SETBANK, 0x00); + + mipi_dsi_dcs_write_seq(dsi, HX83102_SETSPCCMD, 0xC4); + + mipi_dsi_dcs_write_seq(dsi, HX83102_SETMIPI, 0x96); + + mipi_dsi_dcs_write_seq(dsi, HX83102_SETSPCCMD, 0x3F); + + mipi_dsi_dcs_write_seq(dsi, HX83102_SETBANK, 0x01); + + mipi_dsi_dcs_write_seq(dsi, HX83102_SETSPCCMD, 0xC5); + + mipi_dsi_dcs_write_seq(dsi, HX83102_SETMIPI, 0x4F); + + mipi_dsi_dcs_write_seq(dsi, HX83102_SETSPCCMD, 0x3F); + + mipi_dsi_dcs_write_seq(dsi, HX83102_SETBANK, 0x00); + + msleep(60); + + return 0; +}; + static const struct drm_display_mode starry_mode =3D { .clock =3D 162680, .hdisplay =3D 1200, @@ -457,6 +604,34 @@ static const struct hx83102_panel_desc boe_nv110wum_de= sc =3D { .lp11_before_reset =3D true }; =20 +static const struct drm_display_mode ivo_t109nw41_default_mode =3D { + .clock =3D 166400, + .hdisplay =3D 1200, + .hsync_start =3D 1200 + 75, + .hsync_end =3D 1200 + 75 + 20, + .htotal =3D 1200 + 75 + 20 + 55, + .vdisplay =3D 1920, + .vsync_start =3D 1920 + 115, + .vsync_end =3D 1920 + 115 + 8, + .vtotal =3D 1920 + 115 + 8 + 12, + .type =3D DRM_MODE_TYPE_DRIVER | DRM_MODE_TYPE_PREFERRED, +}; + +static const struct hx83102_panel_desc ivo_t109nw41_desc =3D { + .modes =3D &ivo_t109nw41_default_mode, + .bpc =3D 8, + .size =3D { + .width_mm =3D 147, + .height_mm =3D 235, + }, + .lanes =3D 4, + .format =3D MIPI_DSI_FMT_RGB888, + .mode_flags =3D MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_SYNC_PULSE | + MIPI_DSI_MODE_LPM, + .init_cmds =3D ivo_t109nw41_init_cmd, + .lp11_before_reset =3D true +}; + static int hx83102_enable(struct drm_panel *panel) { struct hx83102 *ctx =3D panel_to_hx83102(panel); @@ -743,6 +918,9 @@ static const struct of_device_id hx83102_of_match[] =3D= { { .compatible =3D "boe,nv110wum-l60", .data =3D &boe_nv110wum_desc }, + { .compatible =3D "ivo,t109nw41", + .data =3D &ivo_t109nw41_desc + }, { .compatible =3D "starry,himax83102-j02", .data =3D &starry_desc }, --=20 2.25.1