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charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20240422-topic-sm8x50-upstream-pcie-1-phy-aux-clk-v3-1-799475a27cce@linaro.org> References: <20240422-topic-sm8x50-upstream-pcie-1-phy-aux-clk-v3-0-799475a27cce@linaro.org> In-Reply-To: <20240422-topic-sm8x50-upstream-pcie-1-phy-aux-clk-v3-0-799475a27cce@linaro.org> To: Bjorn Andersson , Konrad Dybcio , Vinod Koul , Kishon Vijay Abraham I , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Krzysztof Kozlowski Cc: linux-arm-msm@vger.kernel.org, linux-phy@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Neil Armstrong , Dmitry Baryshkov X-Mailer: b4 0.12.4 X-Developer-Signature: v=1; a=openpgp-sha256; l=1175; i=neil.armstrong@linaro.org; h=from:subject:message-id; bh=1bqm37cHBp77XacdQMnUI5xOez5SEa+Brh+86TcfY3k=; b=owEBbAKT/ZANAwAKAXfc29rIyEnRAcsmYgBmJiDI6pxVr0gA/n+E41e6tENZ2BTnQpZZk0QoVMZe ZjN5DHCJAjIEAAEKAB0WIQQ9U8YmyFYF/h30LIt33NvayMhJ0QUCZiYgyAAKCRB33NvayMhJ0UsFD/ dXgjhQb2AfQt7uk4tf71uWR5pq4c4HxdkCK+T30MKoFhN40JukvMNWTm2Lo8HrG+eCQ3lvabXVPli4 2YFizwjobRbZc1yQ5zikDLllpW0YFlc7Uq1Ng6N6neQl9ibqZYnk5S2EqaOPSzup10SOznaDAfFNlt R8KRdBPgbULrpUNi5BPHRs2SKPhXY8Qsu+znuW24+zCNu5/Bax2PIjXQyS2OqPauw6+Z8lMu2bTgM0 hpXwnLQ6R42uzPbictmvD1kzY2MEYxScvb62DrdW8yKyjBpXet0GOZ5o12lvKmp0THX2HM8bKDc7EV M0WXrB/pxYMuBvWRxgElS/EFxbbJb+1/+BJxRATX3c23DjiDGb4bi8ZV+n7jsQU3Ia8r12p89NH0Ka kvcsq2MDJXQAQ1hOQTR/hbQJGjw/GXfTqvkfsCeNVqq3Jzp2suRwRKiOg5BaGEciCqZSgI8jJwD0mg SDX6ifm9jqyu8ji97Bl/+Ug7JmlDVP+D93tPbbWpTPRRT2ff1vogKnt9GBQzPxOls6gUIgfryGiULl ix3gHppYOZjrSpjMMhbuM1JwY7NyZG9dH0JnPM3aq2R7psmoKOiXyUWTcdio7IVa3TeoOdaSz2LUnK r3KQVDFaE1DeCnIYn8jU9EULmiSaGJuO7eHfI7dhAcvzxCtURp5zagHZvQ X-Developer-Key: i=neil.armstrong@linaro.org; a=openpgp; fpr=89EC3D058446217450F22848169AB7B1A4CFF8AE Remove the dummy pcie-1-phy-aux-clk clock and replace with the pcie1_phy provided QMP_PCIE_PHY_AUX_CLK. Reviewed-by: Dmitry Baryshkov Signed-off-by: Neil Armstrong --- arch/arm64/boot/dts/qcom/sm8450.dtsi | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sm8450.dtsi b/arch/arm64/boot/dts/qco= m/sm8450.dtsi index 616461fcbab9..71797f337d19 100644 --- a/arch/arm64/boot/dts/qcom/sm8450.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8450.dtsi @@ -754,8 +754,8 @@ gcc: clock-controller@100000 { clocks =3D <&rpmhcc RPMH_CXO_CLK>, <&sleep_clk>, <&pcie0_phy>, - <&pcie1_phy>, - <0>, + <&pcie1_phy QMP_PCIE_PIPE_CLK>, + <&pcie1_phy QMP_PCIE_PHY_AUX_CLK>, <&ufs_mem_phy 0>, <&ufs_mem_phy 1>, <&ufs_mem_phy 2>, @@ -2000,8 +2000,8 @@ pcie1_phy: phy@1c0e000 { "rchng", "pipe"; =20 - clock-output-names =3D "pcie_1_pipe_clk"; - #clock-cells =3D <0>; + clock-output-names =3D "pcie_1_pipe_clk", "pcie_1_phy_aux_clk"; + #clock-cells =3D <1>; =20 #phy-cells =3D <0>; =20 --=20 2.34.1 From nobody Wed Feb 11 00:55:19 2026 Received: from mail-wm1-f41.google.com (mail-wm1-f41.google.com [209.85.128.41]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 33439179AB for ; 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a=openpgp; fpr=89EC3D058446217450F22848169AB7B1A4CFF8AE Remove the dummy pcie-1-phy-aux-clk clock and replace with the pcie1_phy provided QMP_PCIE_PHY_AUX_CLK. Reviewed-by: Dmitry Baryshkov Signed-off-by: Neil Armstrong --- arch/arm64/boot/dts/qcom/sm8550-hdk.dts | 4 ---- arch/arm64/boot/dts/qcom/sm8550-mtp.dts | 4 ---- arch/arm64/boot/dts/qcom/sm8550-qrd.dts | 8 -------- arch/arm64/boot/dts/qcom/sm8550.dtsi | 13 ++++--------- 4 files changed, 4 insertions(+), 25 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sm8550-hdk.dts b/arch/arm64/boot/dts/= qcom/sm8550-hdk.dts index 12d60a0ee095..ccff744dcd14 100644 --- a/arch/arm64/boot/dts/qcom/sm8550-hdk.dts +++ b/arch/arm64/boot/dts/qcom/sm8550-hdk.dts @@ -979,10 +979,6 @@ &pcie1_phy { status =3D "okay"; }; =20 -&pcie_1_phy_aux_clk { - clock-frequency =3D <1000>; -}; - &pm8550_gpios { sdc2_card_det_n: sdc2-card-det-state { pins =3D "gpio12"; diff --git a/arch/arm64/boot/dts/qcom/sm8550-mtp.dts b/arch/arm64/boot/dts/= qcom/sm8550-mtp.dts index 3d4ad5aac70f..1fa7c4492057 100644 --- a/arch/arm64/boot/dts/qcom/sm8550-mtp.dts +++ b/arch/arm64/boot/dts/qcom/sm8550-mtp.dts @@ -739,10 +739,6 @@ &mdss_dp0_out { remote-endpoint =3D <&usb_dp_qmpphy_dp_in>; }; =20 -&pcie_1_phy_aux_clk { - clock-frequency =3D <1000>; -}; - &pcie0 { wake-gpios =3D <&tlmm 96 GPIO_ACTIVE_HIGH>; perst-gpios =3D <&tlmm 94 GPIO_ACTIVE_LOW>; diff --git a/arch/arm64/boot/dts/qcom/sm8550-qrd.dts b/arch/arm64/boot/dts/= qcom/sm8550-qrd.dts index 92f015017418..da3cfa697969 100644 --- a/arch/arm64/boot/dts/qcom/sm8550-qrd.dts +++ b/arch/arm64/boot/dts/qcom/sm8550-qrd.dts @@ -810,10 +810,6 @@ &mdss_dp0_out { remote-endpoint =3D <&usb_dp_qmpphy_dp_in>; }; =20 -&pcie_1_phy_aux_clk { - status =3D "disabled"; -}; - &pcie0 { wake-gpios =3D <&tlmm 96 GPIO_ACTIVE_HIGH>; perst-gpios =3D <&tlmm 94 GPIO_ACTIVE_LOW>; @@ -907,10 +903,6 @@ &pon_resin { status =3D "okay"; }; =20 -&pcie_1_phy_aux_clk { - clock-frequency =3D <1000>; -}; - &qupv3_id_0 { status =3D "okay"; }; diff --git a/arch/arm64/boot/dts/qcom/sm8550.dtsi b/arch/arm64/boot/dts/qco= m/sm8550.dtsi index bc5aeb05ffc3..143994d1e6ca 100644 --- a/arch/arm64/boot/dts/qcom/sm8550.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8550.dtsi @@ -58,11 +58,6 @@ bi_tcxo_ao_div2: bi-tcxo-ao-div2-clk { clock-mult =3D <1>; clock-div =3D <2>; }; - - pcie_1_phy_aux_clk: pcie-1-phy-aux-clk { - compatible =3D "fixed-clock"; - #clock-cells =3D <0>; - }; }; =20 cpus { @@ -776,8 +771,8 @@ gcc: clock-controller@100000 { #power-domain-cells =3D <1>; clocks =3D <&bi_tcxo_div2>, <&sleep_clk>, <&pcie0_phy>, - <&pcie1_phy>, - <&pcie_1_phy_aux_clk>, + <&pcie1_phy QMP_PCIE_PIPE_CLK>, + <&pcie1_phy QMP_PCIE_PHY_AUX_CLK>, <&ufs_mem_phy 0>, <&ufs_mem_phy 1>, <&ufs_mem_phy 2>, @@ -1928,8 +1923,8 @@ pcie1_phy: phy@1c0e000 { =20 power-domains =3D <&gcc PCIE_1_PHY_GDSC>; =20 - #clock-cells =3D <0>; - clock-output-names =3D "pcie1_pipe_clk"; + #clock-cells =3D <1>; + clock-output-names =3D "pcie1_pipe_clk", "pcie1_phy_aux_clk"; =20 #phy-cells =3D <0>; =20 --=20 2.34.1 From nobody Wed Feb 11 00:55:19 2026 Received: from mail-wm1-f42.google.com (mail-wm1-f42.google.com [209.85.128.42]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id DDDE1433CF for ; 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a=openpgp; fpr=89EC3D058446217450F22848169AB7B1A4CFF8AE Remove the dummy pcie-1-phy-aux-clk clock and replace with the pcie1_phy provided QMP_PCIE_PHY_AUX_CLK. Reviewed-by: Dmitry Baryshkov Signed-off-by: Neil Armstrong --- arch/arm64/boot/dts/qcom/sm8650-mtp.dts | 4 ---- arch/arm64/boot/dts/qcom/sm8650-qrd.dts | 4 ---- arch/arm64/boot/dts/qcom/sm8650.dtsi | 13 ++++--------- 3 files changed, 4 insertions(+), 17 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sm8650-mtp.dts b/arch/arm64/boot/dts/= qcom/sm8650-mtp.dts index d04ceaa73c2b..ea092f532e5a 100644 --- a/arch/arm64/boot/dts/qcom/sm8650-mtp.dts +++ b/arch/arm64/boot/dts/qcom/sm8650-mtp.dts @@ -641,10 +641,6 @@ &mdss_dsi0_phy { status =3D "okay"; }; =20 -&pcie_1_phy_aux_clk { - clock-frequency =3D <1000>; -}; - &pcie0 { wake-gpios =3D <&tlmm 96 GPIO_ACTIVE_HIGH>; perst-gpios =3D <&tlmm 94 GPIO_ACTIVE_LOW>; diff --git a/arch/arm64/boot/dts/qcom/sm8650-qrd.dts b/arch/arm64/boot/dts/= qcom/sm8650-qrd.dts index 4e94f7fe4d2d..bd87aa3aa548 100644 --- a/arch/arm64/boot/dts/qcom/sm8650-qrd.dts +++ b/arch/arm64/boot/dts/qcom/sm8650-qrd.dts @@ -835,10 +835,6 @@ &mdss_dp0_out { remote-endpoint =3D <&usb_dp_qmpphy_dp_in>; }; =20 -&pcie_1_phy_aux_clk { - clock-frequency =3D <1000>; -}; - &pcie0 { wake-gpios =3D <&tlmm 96 GPIO_ACTIVE_HIGH>; perst-gpios =3D <&tlmm 94 GPIO_ACTIVE_LOW>; diff --git a/arch/arm64/boot/dts/qcom/sm8650.dtsi b/arch/arm64/boot/dts/qco= m/sm8650.dtsi index 8e0c1841f748..658ad2b41c5a 100644 --- a/arch/arm64/boot/dts/qcom/sm8650.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8650.dtsi @@ -60,11 +60,6 @@ bi_tcxo_ao_div2: bi-tcxo-ao-div2-clk { clock-mult =3D <1>; clock-div =3D <2>; }; - - pcie_1_phy_aux_clk: pcie-1-phy-aux-clk { - compatible =3D "fixed-clock"; - #clock-cells =3D <0>; - }; }; =20 cpus { @@ -758,8 +753,8 @@ gcc: clock-controller@100000 { <&bi_tcxo_ao_div2>, <&sleep_clk>, <&pcie0_phy>, - <&pcie1_phy>, - <&pcie_1_phy_aux_clk>, + <&pcie1_phy QMP_PCIE_PIPE_CLK>, + <&pcie1_phy QMP_PCIE_PHY_AUX_CLK>, <&ufs_mem_phy 0>, <&ufs_mem_phy 1>, <&ufs_mem_phy 2>, @@ -2467,8 +2462,8 @@ pcie1_phy: phy@1c0e000 { =20 power-domains =3D <&gcc PCIE_1_PHY_GDSC>; =20 - #clock-cells =3D <0>; - clock-output-names =3D "pcie1_pipe_clk"; + #clock-cells =3D <1>; + clock-output-names =3D "pcie1_pipe_clk", "pcie1_phy_aux_clk"; =20 #phy-cells =3D <0>; =20 --=20 2.34.1