From nobody Fri Dec 26 01:29:39 2025 Received: from mail-pl1-f181.google.com (mail-pl1-f181.google.com [209.85.214.181]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id CD7DA1494D3 for ; Fri, 19 Apr 2024 23:48:14 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.214.181 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1713570496; cv=none; b=rxF4l/JHgpLQuzNDtL69bd2UA1q0FxoBchtB/418FgdQO+pkwMuAid2CV+mAHcBwed/sifMbDpGH0pHBtUgd+Err46DRwQNuf1E1/Pr1V2MX7z1P+pwGVXG/7PbW6MjHKfYh9wnOiaVlwvQK1yWKhMEb1HidEKw228HQClQplco= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1713570496; c=relaxed/simple; bh=iSleVGmYPORH0YJ6M9GKkX0luLVW1L/lHmqsDNV+cHA=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=S7hU75IlxWs/oAbugxL4JTCmAuanucWzVmw6E9A0AJ1D57kClIwvjpzuZoNRXuuiHvVNUfIDl7CZmXLDkUF6P34wsEBKl9dFPSND+Q1nNwDXG6FDzxVbNyyO5K0SW2NL5JHllgkjhMm2XYbL/e/8YyVgMzW0cww8TQip28kizTQ= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=rivosinc.com; spf=pass smtp.mailfrom=rivosinc.com; dkim=pass (2048-bit key) header.d=rivosinc-com.20230601.gappssmtp.com header.i=@rivosinc-com.20230601.gappssmtp.com header.b=B0nIt34S; arc=none smtp.client-ip=209.85.214.181 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=rivosinc.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=rivosinc.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=rivosinc-com.20230601.gappssmtp.com header.i=@rivosinc-com.20230601.gappssmtp.com header.b="B0nIt34S" Received: by mail-pl1-f181.google.com with SMTP id d9443c01a7336-1e4266673bbso24364535ad.2 for ; Fri, 19 Apr 2024 16:48:14 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20230601.gappssmtp.com; s=20230601; t=1713570494; x=1714175294; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=qvJukw934GuSrXeFuup9ak7dnmqxN0Lb+FQnvb7sFPo=; b=B0nIt34SzHbOIIiQFj1Gnm/61ae9h9NYll6jcU4N92MTlY/AdBw0hvY6Kc+DPF+JWC /uOhUNi0MbOzJCVOR6AOxnr6lqc5ADCDAJPCaT6qy6/ZGZc/bzqjuQTXXBovVkSXNe4b 9pAqjiZ+sT4DH1+2Y6wM7j82VPATjbXM2IREjOiPmMPUWUK8VIRevZbZajO2Tqf9mnWl hG6A+KLNFPSCuTGIDrWwLvp8yZTHrf2HzeEFpyGdEo5ZPfyFLRtL8p/no+8pj6AfFVVY TVrvUyqYgk60WBMXTf1zN1c8QT4zYyl6XvVxxndbnia1LGV3XJGawsNDnj5grBOVeFF5 ySbg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1713570494; x=1714175294; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=qvJukw934GuSrXeFuup9ak7dnmqxN0Lb+FQnvb7sFPo=; b=UqnSWe8EDtpw5Y+p7vzBhLRDq7DAmPM63KXOxLbacJWdx355mJ9Oac4w0deDQr3VU7 sdtERazN4GKz5WJiOS0u6UkcXTs9eADoZEyZ3Mg9ZTg9qPnmaYx0ZSCZZ1yXa75Q3ikm nXz5kiRlbUDSu3m/GmkazL9hukj6Wqc8AMhGxxi4SrSXulfaWyxzjKHeaQzBsCit6Wkm mEDIO5KvzNgXDlUCIVEYh6tpDwlVh41BPpkrjbNk/yhh/ZEeZZq5ptGbr5iLbZ1dGtAX JtYz4LvYe4sto7ekyWbJ0YVkRjhBMGbuRrZsXjer4k1olpIsVMYUm4X1eewe3WOvSkoF Wa1A== X-Gm-Message-State: AOJu0YykPCJ/qWWaz3aXhb62BvoLONHd6L3DIb/F1PJAaxEUSUPSbraT 971K4q+Sk6pXn0IePDvr/1I/fk4eRwWiL6mRuHRaSNzI2Pgd2zYlCROSq5LQ+r94C0niSleCmKR 2 X-Google-Smtp-Source: AGHT+IHNOAevdCsO+x56Lrjstt6VQiieab73uI15/qneokBom5eDca9biRdG55Oycpz2lFWb0UW/7w== X-Received: by 2002:a17:902:e889:b0:1e5:3684:617e with SMTP id w9-20020a170902e88900b001e53684617emr4770983plg.52.1713570494026; Fri, 19 Apr 2024 16:48:14 -0700 (PDT) Received: from atishp.ba.rivosinc.com ([64.71.180.162]) by smtp.gmail.com with ESMTPSA id w17-20020a170902d11100b001e42f215f33sm3924017plw.85.2024.04.19.16.48.12 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 19 Apr 2024 16:48:13 -0700 (PDT) From: Atish Patra To: linux-kernel@vger.kernel.org Cc: Atish Patra , Andrew Jones , Ajay Kaher , Albert Ou , Alexandre Ghiti , Anup Patel , samuel.holland@sifive.com, Conor Dooley , Juergen Gross , kvm-riscv@lists.infradead.org, kvm@vger.kernel.org, linux-kselftest@vger.kernel.org, linux-riscv@lists.infradead.org, Mark Rutland , Palmer Dabbelt , Paolo Bonzini , Paul Walmsley , Shuah Khan , virtualization@lists.linux.dev, Will Deacon , x86@kernel.org Subject: [PATCH v8 16/24] RISC-V: KVM: Improve firmware counter read function Date: Sat, 20 Apr 2024 08:17:32 -0700 Message-Id: <20240420151741.962500-17-atishp@rivosinc.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240420151741.962500-1-atishp@rivosinc.com> References: <20240420151741.962500-1-atishp@rivosinc.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Rename the function to indicate that it is meant for firmware counter read. While at it, add a range sanity check for it as well. Reviewed-by: Andrew Jones Signed-off-by: Atish Patra Reviewed-by: Anup Patel --- arch/riscv/include/asm/kvm_vcpu_pmu.h | 2 +- arch/riscv/kvm/vcpu_pmu.c | 7 ++++++- arch/riscv/kvm/vcpu_sbi_pmu.c | 2 +- 3 files changed, 8 insertions(+), 3 deletions(-) diff --git a/arch/riscv/include/asm/kvm_vcpu_pmu.h b/arch/riscv/include/asm= /kvm_vcpu_pmu.h index 55861b5d3382..fa0f535bbbf0 100644 --- a/arch/riscv/include/asm/kvm_vcpu_pmu.h +++ b/arch/riscv/include/asm/kvm_vcpu_pmu.h @@ -89,7 +89,7 @@ int kvm_riscv_vcpu_pmu_ctr_cfg_match(struct kvm_vcpu *vcp= u, unsigned long ctr_ba unsigned long ctr_mask, unsigned long flags, unsigned long eidx, u64 evtdata, struct kvm_vcpu_sbi_return *retdata); -int kvm_riscv_vcpu_pmu_ctr_read(struct kvm_vcpu *vcpu, unsigned long cidx, +int kvm_riscv_vcpu_pmu_fw_ctr_read(struct kvm_vcpu *vcpu, unsigned long ci= dx, struct kvm_vcpu_sbi_return *retdata); int kvm_riscv_vcpu_pmu_fw_ctr_read_hi(struct kvm_vcpu *vcpu, unsigned long= cidx, struct kvm_vcpu_sbi_return *retdata); diff --git a/arch/riscv/kvm/vcpu_pmu.c b/arch/riscv/kvm/vcpu_pmu.c index e1409ec9afc0..04db1f993c47 100644 --- a/arch/riscv/kvm/vcpu_pmu.c +++ b/arch/riscv/kvm/vcpu_pmu.c @@ -235,6 +235,11 @@ static int pmu_ctr_read(struct kvm_vcpu *vcpu, unsigne= d long cidx, u64 enabled, running; int fevent_code; =20 + if (cidx >=3D kvm_pmu_num_counters(kvpmu) || cidx =3D=3D 1) { + pr_warn("Invalid counter id [%ld] during read\n", cidx); + return -EINVAL; + } + pmc =3D &kvpmu->pmc[cidx]; =20 if (pmc->cinfo.type =3D=3D SBI_PMU_CTR_TYPE_FW) { @@ -747,7 +752,7 @@ int kvm_riscv_vcpu_pmu_fw_ctr_read_hi(struct kvm_vcpu *= vcpu, unsigned long cidx, return 0; } =20 -int kvm_riscv_vcpu_pmu_ctr_read(struct kvm_vcpu *vcpu, unsigned long cidx, +int kvm_riscv_vcpu_pmu_fw_ctr_read(struct kvm_vcpu *vcpu, unsigned long ci= dx, struct kvm_vcpu_sbi_return *retdata) { int ret; diff --git a/arch/riscv/kvm/vcpu_sbi_pmu.c b/arch/riscv/kvm/vcpu_sbi_pmu.c index cf111de51bdb..e4be34e03e83 100644 --- a/arch/riscv/kvm/vcpu_sbi_pmu.c +++ b/arch/riscv/kvm/vcpu_sbi_pmu.c @@ -62,7 +62,7 @@ static int kvm_sbi_ext_pmu_handler(struct kvm_vcpu *vcpu,= struct kvm_run *run, ret =3D kvm_riscv_vcpu_pmu_ctr_stop(vcpu, cp->a0, cp->a1, cp->a2, retdat= a); break; case SBI_EXT_PMU_COUNTER_FW_READ: - ret =3D kvm_riscv_vcpu_pmu_ctr_read(vcpu, cp->a0, retdata); + ret =3D kvm_riscv_vcpu_pmu_fw_ctr_read(vcpu, cp->a0, retdata); break; case SBI_EXT_PMU_COUNTER_FW_READ_HI: if (IS_ENABLED(CONFIG_32BIT)) --=20 2.34.1