From nobody Mon Feb 9 08:54:16 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 7521C12D76E for ; Fri, 19 Apr 2024 14:14:09 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1713536049; cv=none; b=R4+oEk3KUizXgEENzmBR87BPiXNfVOMpRorKze0YRRxM6CtrmUs1fMmgTkgWab9EhS+OWJ2ER0/80swHkc+uZBXkdArGklHXqYfrXbJTEgZKQAC6MEoc7S274Kci00WUmvlQK5lgT8N3hJJgZ0J8EwgqFUykLvAOaIcGEBEyonQ= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1713536049; c=relaxed/simple; bh=WU/MlA5F6U8Yw7nLVGdMlcTE8VeVpWRoQVE2dfuxctY=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=EaBGc432Cuhn0L8njj908e3tMUKi7PRhHocNB2R/BSi2LvvCTiERGS/iSgCzAHTaU5DJrqBGYp2TD88/cQXN19nOVmorNqn69UnRgJwUunYcyAxT8WtBOI2P5eelGC0S7bsVoA5dHdQPwBsY863/wSBTuUe/kDeWeZo6FKHF460= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=hFWe2oXO; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="hFWe2oXO" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 0C1AAC32782; Fri, 19 Apr 2024 14:14:06 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1713536049; bh=WU/MlA5F6U8Yw7nLVGdMlcTE8VeVpWRoQVE2dfuxctY=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=hFWe2oXOO/WrOOgFQ0hYsGzdW/vFXGY0rGUDu4Pre50C/+QnZTr2bMUtpBTops7Fy n76omYvelKPfZrezKoWuIhEL8ZjTTLlctrXDS7rxma4sN0xbH7VjZ1hqiFf2Q2oZY7 WV5+4c1KH3cIP2zNlb5LGsz6G0dWEnwKvoYxlxBgeEbsYrzI69DqterRn+6Ly5mxUp tBVVxxZ5oIrFT3UaQ2sK9Gkkvqwx2wtiWJhBUjOHWB9EYQGjELlI4bE0icFuyWAYVx jlJ70L+uysiSoz628/X6bCw+jL/z7jo2HoQ7lJ/qRnjyY4cFjOiWoGC96fFR86T4eE oGMR0vXA1iUBg== From: Michael Walle To: Tudor Ambarus , Pratyush Yadav , Miquel Raynal , Richard Weinberger , Vignesh Raghavendra Cc: Ricardo Ribalda , linux-kernel@vger.kernel.org, linux-mtd@lists.infradead.org, Michael Walle Subject: [PATCH v2 1/6] mtd: spi-nor: Remove support for Xilinx S3AN flashes Date: Fri, 19 Apr 2024 16:12:44 +0200 Message-Id: <20240419141249.609534-2-mwalle@kernel.org> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20240419141249.609534-1-mwalle@kernel.org> References: <20240419141249.609534-1-mwalle@kernel.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" These flashes are kind of an oddball for the very old Xilinx Spartan 3 FPGAs to store their bitstream. More importantly, they reuse the Atmel JEDEC manufacturer ID and in fact the at45db081d already blocks the use of the 3S700AN flash chip. It's time to sunset support for these flashes. Signed-off-by: Michael Walle Acked-by: Tudor Ambarus Reviewed-by: Pratyush Yadav Cc: Ricardo Ribalda Acked-by: Ricardo Ribalda --- drivers/mtd/spi-nor/Makefile | 1 - drivers/mtd/spi-nor/core.c | 1 - drivers/mtd/spi-nor/core.h | 1 - drivers/mtd/spi-nor/xilinx.c | 169 ----------------------------------- 4 files changed, 172 deletions(-) delete mode 100644 drivers/mtd/spi-nor/xilinx.c diff --git a/drivers/mtd/spi-nor/Makefile b/drivers/mtd/spi-nor/Makefile index 5e68468b72fc..5dd9c35f6b6f 100644 --- a/drivers/mtd/spi-nor/Makefile +++ b/drivers/mtd/spi-nor/Makefile @@ -13,7 +13,6 @@ spi-nor-objs +=3D micron-st.o spi-nor-objs +=3D spansion.o spi-nor-objs +=3D sst.o spi-nor-objs +=3D winbond.o -spi-nor-objs +=3D xilinx.o spi-nor-objs +=3D xmc.o spi-nor-$(CONFIG_DEBUG_FS) +=3D debugfs.o obj-$(CONFIG_MTD_SPI_NOR) +=3D spi-nor.o diff --git a/drivers/mtd/spi-nor/core.c b/drivers/mtd/spi-nor/core.c index 3e1f1913536b..cbe5f92eb0af 100644 --- a/drivers/mtd/spi-nor/core.c +++ b/drivers/mtd/spi-nor/core.c @@ -1986,7 +1986,6 @@ static const struct spi_nor_manufacturer *manufacture= rs[] =3D { &spi_nor_spansion, &spi_nor_sst, &spi_nor_winbond, - &spi_nor_xilinx, &spi_nor_xmc, }; =20 diff --git a/drivers/mtd/spi-nor/core.h b/drivers/mtd/spi-nor/core.h index 442786685515..072c69b0d06c 100644 --- a/drivers/mtd/spi-nor/core.h +++ b/drivers/mtd/spi-nor/core.h @@ -603,7 +603,6 @@ extern const struct spi_nor_manufacturer spi_nor_st; extern const struct spi_nor_manufacturer spi_nor_spansion; extern const struct spi_nor_manufacturer spi_nor_sst; extern const struct spi_nor_manufacturer spi_nor_winbond; -extern const struct spi_nor_manufacturer spi_nor_xilinx; extern const struct spi_nor_manufacturer spi_nor_xmc; =20 extern const struct attribute_group *spi_nor_sysfs_groups[]; diff --git a/drivers/mtd/spi-nor/xilinx.c b/drivers/mtd/spi-nor/xilinx.c deleted file mode 100644 index f99118c691b0..000000000000 --- a/drivers/mtd/spi-nor/xilinx.c +++ /dev/null @@ -1,169 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Copyright (C) 2005, Intec Automation Inc. - * Copyright (C) 2014, Freescale Semiconductor, Inc. - */ - -#include - -#include "core.h" - -#define XILINX_OP_SE 0x50 /* Sector erase */ -#define XILINX_OP_PP 0x82 /* Page program */ -#define XILINX_OP_RDSR 0xd7 /* Read status register */ - -#define XSR_PAGESIZE BIT(0) /* Page size in Po2 or Linear */ -#define XSR_RDY BIT(7) /* Ready */ - -#define XILINX_RDSR_OP(buf) \ - SPI_MEM_OP(SPI_MEM_OP_CMD(XILINX_OP_RDSR, 0), \ - SPI_MEM_OP_NO_ADDR, \ - SPI_MEM_OP_NO_DUMMY, \ - SPI_MEM_OP_DATA_IN(1, buf, 0)) - -#define S3AN_FLASH(_id, _name, _n_sectors, _page_size) \ - .id =3D _id, \ - .name =3D _name, \ - .size =3D 8 * (_page_size) * (_n_sectors), \ - .sector_size =3D (8 * (_page_size)), \ - .page_size =3D (_page_size), \ - .flags =3D SPI_NOR_NO_FR - -/* Xilinx S3AN share MFR with Atmel SPI NOR */ -static const struct flash_info xilinx_nor_parts[] =3D { - /* Xilinx S3AN Internal Flash */ - { S3AN_FLASH(SNOR_ID(0x1f, 0x22, 0x00), "3S50AN", 64, 264) }, - { S3AN_FLASH(SNOR_ID(0x1f, 0x24, 0x00), "3S200AN", 256, 264) }, - { S3AN_FLASH(SNOR_ID(0x1f, 0x24, 0x00), "3S400AN", 256, 264) }, - { S3AN_FLASH(SNOR_ID(0x1f, 0x25, 0x00), "3S700AN", 512, 264) }, - { S3AN_FLASH(SNOR_ID(0x1f, 0x26, 0x00), "3S1400AN", 512, 528) }, -}; - -/* - * This code converts an address to the Default Address Mode, that has non - * power of two page sizes. We must support this mode because it is the de= fault - * mode supported by Xilinx tools, it can access the whole flash area and - * changing over to the Power-of-two mode is irreversible and corrupts the - * original data. - * Addr can safely be unsigned int, the biggest S3AN device is smaller than - * 4 MiB. - */ -static u32 s3an_nor_convert_addr(struct spi_nor *nor, u32 addr) -{ - u32 page_size =3D nor->params->page_size; - u32 offset, page; - - offset =3D addr % page_size; - page =3D addr / page_size; - page <<=3D (page_size > 512) ? 10 : 9; - - return page | offset; -} - -/** - * xilinx_nor_read_sr() - Read the Status Register on S3AN flashes. - * @nor: pointer to 'struct spi_nor'. - * @sr: pointer to a DMA-able buffer where the value of the - * Status Register will be written. - * - * Return: 0 on success, -errno otherwise. - */ -static int xilinx_nor_read_sr(struct spi_nor *nor, u8 *sr) -{ - int ret; - - if (nor->spimem) { - struct spi_mem_op op =3D XILINX_RDSR_OP(sr); - - spi_nor_spimem_setup_op(nor, &op, nor->reg_proto); - - ret =3D spi_mem_exec_op(nor->spimem, &op); - } else { - ret =3D spi_nor_controller_ops_read_reg(nor, XILINX_OP_RDSR, sr, - 1); - } - - if (ret) - dev_dbg(nor->dev, "error %d reading SR\n", ret); - - return ret; -} - -/** - * xilinx_nor_sr_ready() - Query the Status Register of the S3AN flash to = see - * if the flash is ready for new commands. - * @nor: pointer to 'struct spi_nor'. - * - * Return: 1 if ready, 0 if not ready, -errno on errors. - */ -static int xilinx_nor_sr_ready(struct spi_nor *nor) -{ - int ret; - - ret =3D xilinx_nor_read_sr(nor, nor->bouncebuf); - if (ret) - return ret; - - return !!(nor->bouncebuf[0] & XSR_RDY); -} - -static int xilinx_nor_setup(struct spi_nor *nor, - const struct spi_nor_hwcaps *hwcaps) -{ - u32 page_size; - int ret; - - ret =3D xilinx_nor_read_sr(nor, nor->bouncebuf); - if (ret) - return ret; - - nor->erase_opcode =3D XILINX_OP_SE; - nor->program_opcode =3D XILINX_OP_PP; - nor->read_opcode =3D SPINOR_OP_READ; - nor->flags |=3D SNOR_F_NO_OP_CHIP_ERASE; - - /* - * This flashes have a page size of 264 or 528 bytes (known as - * Default addressing mode). It can be changed to a more standard - * Power of two mode where the page size is 256/512. This comes - * with a price: there is 3% less of space, the data is corrupted - * and the page size cannot be changed back to default addressing - * mode. - * - * The current addressing mode can be read from the XRDSR register - * and should not be changed, because is a destructive operation. - */ - if (nor->bouncebuf[0] & XSR_PAGESIZE) { - /* Flash in Power of 2 mode */ - page_size =3D (nor->params->page_size =3D=3D 264) ? 256 : 512; - nor->params->page_size =3D page_size; - nor->mtd.writebufsize =3D page_size; - nor->params->size =3D nor->info->size; - nor->mtd.erasesize =3D 8 * page_size; - } else { - /* Flash in Default addressing mode */ - nor->params->convert_addr =3D s3an_nor_convert_addr; - nor->mtd.erasesize =3D nor->info->sector_size; - } - - return 0; -} - -static int xilinx_nor_late_init(struct spi_nor *nor) -{ - nor->params->setup =3D xilinx_nor_setup; - nor->params->ready =3D xilinx_nor_sr_ready; - - return 0; -} - -static const struct spi_nor_fixups xilinx_nor_fixups =3D { - .late_init =3D xilinx_nor_late_init, -}; - -const struct spi_nor_manufacturer spi_nor_xilinx =3D { - .name =3D "xilinx", - .parts =3D xilinx_nor_parts, - .nparts =3D ARRAY_SIZE(xilinx_nor_parts), - .fixups =3D &xilinx_nor_fixups, -}; --=20 2.39.2 From nobody Mon Feb 9 08:54:16 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B79DF12E1DA for ; Fri, 19 Apr 2024 14:14:11 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1713536051; cv=none; b=msQilXWvPWARdLj/urLUFuRkL44G48x257ECY5WU1KU9N/qnPSXivx0wBJP2xaF5c53aKJH2ufYSupvViY6+yCyhnX1x9Edm9CFIyf9wEdVzwvsIj/7Id0O1K61TOwVErQ625YhdROth6wl+vT13YWL2ErmIjo64RcYSO7kJVkg= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1713536051; c=relaxed/simple; bh=q2bEZDZIudIS1aIa7CkbX4KQHDVLkk1sD20tkmStKgo=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=N2OwJCcMdmKtem5deTkehugpWsphQ5vo8kUIUrBVbn7BzI9123wg6hR6W26zMSaLpjIwVTIjmXg4P5gkxrnUbNSCZsy2zypyCOXtodAAIC+q9+VQRd9hyhWKy/XNU0lk1WTQTztxbABTxG3NKuxnsbEp3VLefqNWs7JsjWMkjSQ= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=Y+pT+XHE; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="Y+pT+XHE" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 6D068C3277B; Fri, 19 Apr 2024 14:14:09 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1713536051; bh=q2bEZDZIudIS1aIa7CkbX4KQHDVLkk1sD20tkmStKgo=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=Y+pT+XHEQrmbwKuAGXrFAPoJzygazswmUPaVuAbqaudckIJXqbZYvfTbyFkk/tWnP sG7XtRzpei9J+MiWAoFJoCMDckSUtF98Kks8UiEm5kM5UnBEAPiLjlGu6acnOkzU5P Irar+7lFMBF9zl1INSMepDc2gzARH4HUmPxxAR9X5yTv7ZzZ4Gi05GI0kYCHTeyKPs /7Tad5JZCoQOA96NHTFQ7/Onrk6cKv7JHDIrZ/K/Bn6RsdByTGVkMqEFUCXN6fSqmH pVfw7HWDHpxjWcSCyFxUO2wr6uURB9eIVppuGwtq+kOOxJP/vNhN/7AU8KZtrzn15G VhsTHZgHUAoXQ== From: Michael Walle To: Tudor Ambarus , Pratyush Yadav , Miquel Raynal , Richard Weinberger , Vignesh Raghavendra Cc: Ricardo Ribalda , linux-kernel@vger.kernel.org, linux-mtd@lists.infradead.org, Michael Walle Subject: [PATCH v2 2/6] mtd: spi-nor: get rid of non-power-of-2 page size handling Date: Fri, 19 Apr 2024 16:12:45 +0200 Message-Id: <20240419141249.609534-3-mwalle@kernel.org> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20240419141249.609534-1-mwalle@kernel.org> References: <20240419141249.609534-1-mwalle@kernel.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The Xilinx flashes were the only user of the page sized that were no power of 2. Support for them were dropped, thus we can also get rid of the special page size handling for it. Signed-off-by: Michael Walle Acked-by: Tudor Ambarus Reviewed-by: Pratyush Yadav --- drivers/mtd/spi-nor/core.c | 41 ++++++++++---------------------------- drivers/mtd/spi-nor/core.h | 4 ---- 2 files changed, 11 insertions(+), 34 deletions(-) diff --git a/drivers/mtd/spi-nor/core.c b/drivers/mtd/spi-nor/core.c index cbe5f92eb0af..31dfdbf96765 100644 --- a/drivers/mtd/spi-nor/core.c +++ b/drivers/mtd/spi-nor/core.c @@ -1463,14 +1463,6 @@ static void spi_nor_unlock_and_unprep_rd(struct spi_= nor *nor, loff_t start, size spi_nor_unprep(nor); } =20 -static u32 spi_nor_convert_addr(struct spi_nor *nor, loff_t addr) -{ - if (!nor->params->convert_addr) - return addr; - - return nor->params->convert_addr(nor, addr); -} - /* * Initiate the erasure of a single sector */ @@ -1478,8 +1470,6 @@ int spi_nor_erase_sector(struct spi_nor *nor, u32 add= r) { int i; =20 - addr =3D spi_nor_convert_addr(nor, addr); - if (nor->spimem) { struct spi_mem_op op =3D SPI_NOR_SECTOR_ERASE_OP(nor->erase_opcode, @@ -2064,8 +2054,6 @@ static int spi_nor_read(struct mtd_info *mtd, loff_t = from, size_t len, while (len) { loff_t addr =3D from; =20 - addr =3D spi_nor_convert_addr(nor, addr); - ret =3D spi_nor_read_data(nor, addr, len, buf); if (ret =3D=3D 0) { /* We shouldn't see 0-length reads */ @@ -2098,7 +2086,7 @@ static int spi_nor_write(struct mtd_info *mtd, loff_t= to, size_t len, size_t *retlen, const u_char *buf) { struct spi_nor *nor =3D mtd_to_spi_nor(mtd); - size_t page_offset, page_remain, i; + size_t i; ssize_t ret; u32 page_size =3D nor->params->page_size; =20 @@ -2111,23 +2099,9 @@ static int spi_nor_write(struct mtd_info *mtd, loff_= t to, size_t len, for (i =3D 0; i < len; ) { ssize_t written; loff_t addr =3D to + i; - - /* - * If page_size is a power of two, the offset can be quickly - * calculated with an AND operation. On the other cases we - * need to do a modulus operation (more expensive). - */ - if (is_power_of_2(page_size)) { - page_offset =3D addr & (page_size - 1); - } else { - u64 aux =3D addr; - - page_offset =3D do_div(aux, page_size); - } + size_t page_offset =3D addr & (page_size - 1); /* the size of data remaining on the first page */ - page_remain =3D min_t(size_t, page_size - page_offset, len - i); - - addr =3D spi_nor_convert_addr(nor, addr); + size_t page_remain =3D min_t(size_t, page_size - page_offset, len - i); =20 ret =3D spi_nor_lock_device(nor); if (ret) @@ -3054,7 +3028,14 @@ static int spi_nor_init_params(struct spi_nor *nor) spi_nor_init_params_deprecated(nor); } =20 - return spi_nor_late_init_params(nor); + ret =3D spi_nor_late_init_params(nor); + if (ret) + return ret; + + if (WARN_ON(!is_power_of_2(nor->params->page_size))) + return -EINVAL; + + return 0; } =20 /** spi_nor_set_octal_dtr() - enable or disable Octal DTR I/O. diff --git a/drivers/mtd/spi-nor/core.h b/drivers/mtd/spi-nor/core.h index 072c69b0d06c..3043d583eac2 100644 --- a/drivers/mtd/spi-nor/core.h +++ b/drivers/mtd/spi-nor/core.h @@ -366,9 +366,6 @@ struct spi_nor_otp { * @set_octal_dtr: enables or disables SPI NOR octal DTR mode. * @quad_enable: enables SPI NOR quad mode. * @set_4byte_addr_mode: puts the SPI NOR in 4 byte addressing mode. - * @convert_addr: converts an absolute address into something the flash - * will understand. Particularly useful when pagesize= is - * not a power-of-2. * @setup: (optional) configures the SPI NOR memory. Useful for * SPI NOR flashes that have peculiarities to the SPI NOR * standard e.g. different opcodes, specific address @@ -403,7 +400,6 @@ struct spi_nor_flash_parameter { int (*set_octal_dtr)(struct spi_nor *nor, bool enable); int (*quad_enable)(struct spi_nor *nor); int (*set_4byte_addr_mode)(struct spi_nor *nor, bool enable); - u32 (*convert_addr)(struct spi_nor *nor, u32 addr); int (*setup)(struct spi_nor *nor, const struct spi_nor_hwcaps *hwcaps); int (*ready)(struct spi_nor *nor); =20 --=20 2.39.2 From nobody Mon Feb 9 08:54:16 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D549212F361 for ; Fri, 19 Apr 2024 14:14:13 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1713536053; cv=none; b=ZVTrrTNXmQ/9Xm3oOK0YNdKtzF1MrWOVWSlZqM2NTg8InyPdMGlBMKV/v0bI7K8QBrZCRrFNIxaiF0pnoaSPJOVy2Bd26V3L/uIQrKG03nR86jeVzgXjih5uctBAQ+9/37ThcdGRSceBedrcFZ5tHCoRNnsfV2bWrlwZ1GHzW30= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1713536053; c=relaxed/simple; bh=eu/b53uh7QEFQfeTA4Rx9Iizk5MHoafPYkrPYXyPtFA=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=p+u3YT9Bu0gquoMQJoHu+XQ+3ZUoLtyqx1dD0e3kZwHqhuq9Qh6sfVoNQHYI9NZFhnFFbCFGY9s4uYVXg5KxNGWybD0uiZlS1mA0oVISFmfSRA+m9feHt72GcO26OJ3Nz6sBSQMk3x2pdxI1FxIcQsw8z9XmULXPVgZoWZWaYh4= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=MLl+bryC; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="MLl+bryC" Received: by smtp.kernel.org (Postfix) with ESMTPSA id C8952C32781; Fri, 19 Apr 2024 14:14:11 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1713536053; bh=eu/b53uh7QEFQfeTA4Rx9Iizk5MHoafPYkrPYXyPtFA=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=MLl+bryCZObdL2ffb7sW5QC3jVBjzYkzfaV9dUxZUtCxNHCLyq/LZq4ncPugboy8f Q/599cuOFSG/hNlOFcpLRuef+Y+BnQN+h6081JDRYArHG/PNrf77TJbHmeS7iNpqgt OtFilIw1nOaIXUUWkYVV/2/CrwaQirZY+UindCrZvR615g3ailFIL4OI1bwjHE4SlI u+LU3L2mHurSnrOeKUw98PeTXBAWpUxEnnGWYyoEyf1nGAn97NqVPwxiSVc4vWKNp0 cL4MyRYyX4GImZ00GH+OXje7NmqporXnlw+EHjgybGdy7f0rm1FHQnx9qSCK7ESLb4 YyOUUAxa9XG8Q== From: Michael Walle To: Tudor Ambarus , Pratyush Yadav , Miquel Raynal , Richard Weinberger , Vignesh Raghavendra Cc: Ricardo Ribalda , linux-kernel@vger.kernel.org, linux-mtd@lists.infradead.org, Michael Walle Subject: [PATCH v2 3/6] mtd: spi-nor: remove .setup() callback Date: Fri, 19 Apr 2024 16:12:46 +0200 Message-Id: <20240419141249.609534-4-mwalle@kernel.org> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20240419141249.609534-1-mwalle@kernel.org> References: <20240419141249.609534-1-mwalle@kernel.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" With the removal of the Xilinx flashes, there is no more flash driver using that hook. The original intention was to let the driver configure special requirements like page size an opcodes. This is already possible by other means and it is unlikely a flash will overwrite the (more or less complex) setup function. Signed-off-by: Michael Walle Acked-by: Tudor Ambarus Reviewed-by: Pratyush Yadav --- drivers/mtd/spi-nor/core.c | 105 ++++++++++++++++--------------------- drivers/mtd/spi-nor/core.h | 5 -- 2 files changed, 45 insertions(+), 65 deletions(-) diff --git a/drivers/mtd/spi-nor/core.c b/drivers/mtd/spi-nor/core.c index 31dfdbf96765..f4c0b5185818 100644 --- a/drivers/mtd/spi-nor/core.c +++ b/drivers/mtd/spi-nor/core.c @@ -2554,8 +2554,51 @@ static int spi_nor_select_erase(struct spi_nor *nor) return 0; } =20 -static int spi_nor_default_setup(struct spi_nor *nor, - const struct spi_nor_hwcaps *hwcaps) +static int spi_nor_set_addr_nbytes(struct spi_nor *nor) +{ + if (nor->params->addr_nbytes) { + nor->addr_nbytes =3D nor->params->addr_nbytes; + } else if (nor->read_proto =3D=3D SNOR_PROTO_8_8_8_DTR) { + /* + * In 8D-8D-8D mode, one byte takes half a cycle to transfer. So + * in this protocol an odd addr_nbytes cannot be used because + * then the address phase would only span a cycle and a half. + * Half a cycle would be left over. We would then have to start + * the dummy phase in the middle of a cycle and so too the data + * phase, and we will end the transaction with half a cycle left + * over. + * + * Force all 8D-8D-8D flashes to use an addr_nbytes of 4 to + * avoid this situation. + */ + nor->addr_nbytes =3D 4; + } else if (nor->info->addr_nbytes) { + nor->addr_nbytes =3D nor->info->addr_nbytes; + } else { + nor->addr_nbytes =3D 3; + } + + if (nor->addr_nbytes =3D=3D 3 && nor->params->size > 0x1000000) { + /* enable 4-byte addressing if the device exceeds 16MiB */ + nor->addr_nbytes =3D 4; + } + + if (nor->addr_nbytes > SPI_NOR_MAX_ADDR_NBYTES) { + dev_dbg(nor->dev, "The number of address bytes is too large: %u\n", + nor->addr_nbytes); + return -EINVAL; + } + + /* Set 4byte opcodes when possible. */ + if (nor->addr_nbytes =3D=3D 4 && nor->flags & SNOR_F_4B_OPCODES && + !(nor->flags & SNOR_F_HAS_4BAIT)) + spi_nor_set_4byte_opcodes(nor); + + return 0; +} + +static int spi_nor_setup(struct spi_nor *nor, + const struct spi_nor_hwcaps *hwcaps) { struct spi_nor_flash_parameter *params =3D nor->params; u32 ignored_mask, shared_mask; @@ -2612,64 +2655,6 @@ static int spi_nor_default_setup(struct spi_nor *nor, return err; } =20 - return 0; -} - -static int spi_nor_set_addr_nbytes(struct spi_nor *nor) -{ - if (nor->params->addr_nbytes) { - nor->addr_nbytes =3D nor->params->addr_nbytes; - } else if (nor->read_proto =3D=3D SNOR_PROTO_8_8_8_DTR) { - /* - * In 8D-8D-8D mode, one byte takes half a cycle to transfer. So - * in this protocol an odd addr_nbytes cannot be used because - * then the address phase would only span a cycle and a half. - * Half a cycle would be left over. We would then have to start - * the dummy phase in the middle of a cycle and so too the data - * phase, and we will end the transaction with half a cycle left - * over. - * - * Force all 8D-8D-8D flashes to use an addr_nbytes of 4 to - * avoid this situation. - */ - nor->addr_nbytes =3D 4; - } else if (nor->info->addr_nbytes) { - nor->addr_nbytes =3D nor->info->addr_nbytes; - } else { - nor->addr_nbytes =3D 3; - } - - if (nor->addr_nbytes =3D=3D 3 && nor->params->size > 0x1000000) { - /* enable 4-byte addressing if the device exceeds 16MiB */ - nor->addr_nbytes =3D 4; - } - - if (nor->addr_nbytes > SPI_NOR_MAX_ADDR_NBYTES) { - dev_dbg(nor->dev, "The number of address bytes is too large: %u\n", - nor->addr_nbytes); - return -EINVAL; - } - - /* Set 4byte opcodes when possible. */ - if (nor->addr_nbytes =3D=3D 4 && nor->flags & SNOR_F_4B_OPCODES && - !(nor->flags & SNOR_F_HAS_4BAIT)) - spi_nor_set_4byte_opcodes(nor); - - return 0; -} - -static int spi_nor_setup(struct spi_nor *nor, - const struct spi_nor_hwcaps *hwcaps) -{ - int ret; - - if (nor->params->setup) - ret =3D nor->params->setup(nor, hwcaps); - else - ret =3D spi_nor_default_setup(nor, hwcaps); - if (ret) - return ret; - return spi_nor_set_addr_nbytes(nor); } =20 diff --git a/drivers/mtd/spi-nor/core.h b/drivers/mtd/spi-nor/core.h index 3043d583eac2..497957b64906 100644 --- a/drivers/mtd/spi-nor/core.h +++ b/drivers/mtd/spi-nor/core.h @@ -366,10 +366,6 @@ struct spi_nor_otp { * @set_octal_dtr: enables or disables SPI NOR octal DTR mode. * @quad_enable: enables SPI NOR quad mode. * @set_4byte_addr_mode: puts the SPI NOR in 4 byte addressing mode. - * @setup: (optional) configures the SPI NOR memory. Useful for - * SPI NOR flashes that have peculiarities to the SPI NOR - * standard e.g. different opcodes, specific address - * calculation, page size, etc. * @ready: (optional) flashes might use a different mechanism * than reading the status register to indicate they * are ready for a new command @@ -400,7 +396,6 @@ struct spi_nor_flash_parameter { int (*set_octal_dtr)(struct spi_nor *nor, bool enable); int (*quad_enable)(struct spi_nor *nor); int (*set_4byte_addr_mode)(struct spi_nor *nor, bool enable); - int (*setup)(struct spi_nor *nor, const struct spi_nor_hwcaps *hwcaps); int (*ready)(struct spi_nor *nor); =20 const struct spi_nor_locking_ops *locking_ops; --=20 2.39.2 From nobody Mon Feb 9 08:54:16 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 8621012F59A for ; Fri, 19 Apr 2024 14:14:16 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1713536056; cv=none; b=SkCW4Lwq7wBKucYvG+CKIOvnTtiZ03m78Cz9udbHacX8L51Pp9X6pKZDGsJJmS4LfELAaeJT3/z1r6mOXf51+SqB5JzEZt99f2u2lfQjs+OLWFzXGFLyfPNTROBPnv2BmQ8N/3SvK5okdKjZLzw91Z9eaxAcbUV0+AEVk0GoXvI= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1713536056; c=relaxed/simple; bh=ZiwsAW01Vo0W/LIsWonJMl/TomhMGShCbtNy1DqFzs4=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=YhN5zUlR93oZmGv1bwGIU1ZJSP8/2erdF0wzoPXANPo2rXYnuHZqbRZyia4ZSNcKtkiKEDPmrOMsl4pjqP1V+D1RnwkgeUjg9DZ76ytETMcAGUqoc+EbXxAd86yULazJ9mSsXWETfjZza3LhdrkS5W2Um6CjaDoIadpldnzOILw= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=deB2QTFG; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="deB2QTFG" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 306E4C072AA; Fri, 19 Apr 2024 14:14:14 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1713536056; bh=ZiwsAW01Vo0W/LIsWonJMl/TomhMGShCbtNy1DqFzs4=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=deB2QTFGDKjdUBu0Q5WELIIiO5HhzOLZ7gcHlleifYuS24mXPFrzTu6lN28JmfA6P TUw+RBKKNKoZXDLgx1b3cO3niv8S5w5oRwdiYxnVutR1KsBiwB++p5lrAjCBoBVv5J f2NedEPAOjVHxT3sj6Mz4ZXq/e607XsamxO/tOyCfvXcdPdp865QfErNOOiK9FMJhs l62w8gCcMeGFWu5/ppd7DvoLdJ8Ad770WMuSibO58MrpVOQkKtc3Yb9xB4P3x0MrgF WysT3sAN6Mw77z8sBKpZg10JcwOwOHjJSgzVpZ4dOdvaJaej7zgSficI9SDPzeMtuP +CQrT5SiL+KyA== From: Michael Walle To: Tudor Ambarus , Pratyush Yadav , Miquel Raynal , Richard Weinberger , Vignesh Raghavendra Cc: Ricardo Ribalda , linux-kernel@vger.kernel.org, linux-mtd@lists.infradead.org, Michael Walle Subject: [PATCH v2 4/6] mtd: spi-nor: get rid of SPI_NOR_NO_FR Date: Fri, 19 Apr 2024 16:12:47 +0200 Message-Id: <20240419141249.609534-5-mwalle@kernel.org> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20240419141249.609534-1-mwalle@kernel.org> References: <20240419141249.609534-1-mwalle@kernel.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The evervision FRAM devices are the only user of the NO_FR flag. Drop the global flag and instead use a manufacturer fixup for the evervision flashes to drop the fast read support. Signed-off-by: Michael Walle Reviewed-by: Pratyush Yadav Reviewed-by: Tudor Ambarus --- Please note, that the fast read opcode will still be set in spi_nor_init_default_params(), but the selection of the read opcodes just depends on the mask. That is also something I want to fix soon: the opcodes can always be set and the drivers/SFDP will only set the mask. Opcodes then can be switched between 3b and 4b ones if necessary. --- drivers/mtd/spi-nor/core.c | 9 ++------- drivers/mtd/spi-nor/core.h | 2 -- drivers/mtd/spi-nor/everspin.c | 19 +++++++++++++++---- 3 files changed, 17 insertions(+), 13 deletions(-) diff --git a/drivers/mtd/spi-nor/core.c b/drivers/mtd/spi-nor/core.c index f4c0b5185818..4e2ae6642d4c 100644 --- a/drivers/mtd/spi-nor/core.c +++ b/drivers/mtd/spi-nor/core.c @@ -2923,15 +2923,10 @@ static void spi_nor_init_default_params(struct spi_= nor *nor) params->page_size =3D info->page_size ?: SPI_NOR_DEFAULT_PAGE_SIZE; params->n_banks =3D info->n_banks ?: SPI_NOR_DEFAULT_N_BANKS; =20 - if (!(info->flags & SPI_NOR_NO_FR)) { - /* Default to Fast Read for DT and non-DT platform devices. */ + /* Default to Fast Read for non-DT and enable it if requested by DT. */ + if (!np || of_property_read_bool(np, "m25p,fast-read")) params->hwcaps.mask |=3D SNOR_HWCAPS_READ_FAST; =20 - /* Mask out Fast Read if not requested at DT instantiation. */ - if (np && !of_property_read_bool(np, "m25p,fast-read")) - params->hwcaps.mask &=3D ~SNOR_HWCAPS_READ_FAST; - } - /* (Fast) Read settings. */ params->hwcaps.mask |=3D SNOR_HWCAPS_READ; spi_nor_set_read_settings(¶ms->reads[SNOR_CMD_READ], diff --git a/drivers/mtd/spi-nor/core.h b/drivers/mtd/spi-nor/core.h index 497957b64906..1516b6d0dc37 100644 --- a/drivers/mtd/spi-nor/core.h +++ b/drivers/mtd/spi-nor/core.h @@ -470,7 +470,6 @@ struct spi_nor_id { * Usually these will power-up in a write-prote= cted * state. * SPI_NOR_NO_ERASE: no erase command needed. - * SPI_NOR_NO_FR: can't do fastread. * SPI_NOR_QUAD_PP: flash supports Quad Input Page Program. * SPI_NOR_RWW: flash supports reads while write. * @@ -519,7 +518,6 @@ struct flash_info { #define SPI_NOR_BP3_SR_BIT6 BIT(4) #define SPI_NOR_SWP_IS_VOLATILE BIT(5) #define SPI_NOR_NO_ERASE BIT(6) -#define SPI_NOR_NO_FR BIT(7) #define SPI_NOR_QUAD_PP BIT(8) #define SPI_NOR_RWW BIT(9) =20 diff --git a/drivers/mtd/spi-nor/everspin.c b/drivers/mtd/spi-nor/everspin.c index 5f321e24ae7d..0720a61947e7 100644 --- a/drivers/mtd/spi-nor/everspin.c +++ b/drivers/mtd/spi-nor/everspin.c @@ -14,28 +14,39 @@ static const struct flash_info everspin_nor_parts[] =3D= { .size =3D SZ_16K, .sector_size =3D SZ_16K, .addr_nbytes =3D 2, - .flags =3D SPI_NOR_NO_ERASE | SPI_NOR_NO_FR, + .flags =3D SPI_NOR_NO_ERASE, }, { .name =3D "mr25h256", .size =3D SZ_32K, .sector_size =3D SZ_32K, .addr_nbytes =3D 2, - .flags =3D SPI_NOR_NO_ERASE | SPI_NOR_NO_FR, + .flags =3D SPI_NOR_NO_ERASE, }, { .name =3D "mr25h10", .size =3D SZ_128K, .sector_size =3D SZ_128K, - .flags =3D SPI_NOR_NO_ERASE | SPI_NOR_NO_FR, + .flags =3D SPI_NOR_NO_ERASE, }, { .name =3D "mr25h40", .size =3D SZ_512K, .sector_size =3D SZ_512K, - .flags =3D SPI_NOR_NO_ERASE | SPI_NOR_NO_FR, + .flags =3D SPI_NOR_NO_ERASE, } }; =20 +static void evervision_nor_default_init(struct spi_nor *nor) +{ + /* Everspin FRAMs don't support the fast read opcode. */ + nor->params->hwcaps.mask &=3D ~SNOR_HWCAPS_READ_FAST; +} + +static const struct spi_nor_fixups evervision_nor_fixups =3D { + .default_init =3D evervision_nor_default_init, +}; + const struct spi_nor_manufacturer spi_nor_everspin =3D { .name =3D "everspin", .parts =3D everspin_nor_parts, .nparts =3D ARRAY_SIZE(everspin_nor_parts), + .fixups =3D &evervision_nor_fixups, }; --=20 2.39.2 From nobody Mon Feb 9 08:54:16 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D15A712F5A1 for ; Fri, 19 Apr 2024 14:14:18 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; 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Fri, 19 Apr 2024 14:14:16 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1713536058; bh=DcpeOrGfxSWHHh5NWmUVMOKN4dI/mFp5Fo+st0c8Sy8=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=MPzfyqZDTSlEOuYwta3lRloXs0YAlULAlSge2d5/w+h0p9F1rCwkCaU190HAsPf+C 1bH9QgzNb5p1UuLAU0OcQBe+loA2WqYp0w8xC0PZz0sHNHTHD7HPgrjctiWJSo9QRE q3Kg5AWBb2Yz9x1lHjsgBe0HHDtImeGhLN8uDxP9dS5UgR4Jzd+vyWlaS1WXuGEOM2 T96DNEIJPb/mIk0fXd9u8ij9sH/wEVbkRJzo+LZuKm1uvn/UlRc4FzelePYoSkQ1Qn QLiJZg/NzE1Kii8Zoq+cRjuyAGzxdtEeJsWKH8NS+sTtLCWe2ESwfn8PUnDXiktuAF qRTUxxFd6VS7A== From: Michael Walle To: Tudor Ambarus , Pratyush Yadav , Miquel Raynal , Richard Weinberger , Vignesh Raghavendra Cc: Ricardo Ribalda , linux-kernel@vger.kernel.org, linux-mtd@lists.infradead.org, Michael Walle Subject: [PATCH v2 5/6] mtd: spi-nor: simplify spi_nor_get_flash_info() Date: Fri, 19 Apr 2024 16:12:48 +0200 Message-Id: <20240419141249.609534-6-mwalle@kernel.org> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20240419141249.609534-1-mwalle@kernel.org> References: <20240419141249.609534-1-mwalle@kernel.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Rework spi_nor_get_flash_info() to make it look more straight forward and esp. don't return early. The latter is a preparation to check for deprecated flashes. Signed-off-by: Michael Walle Reviewed-by: Pratyush Yadav --- drivers/mtd/spi-nor/core.c | 45 ++++++++++++++++++-------------------- 1 file changed, 21 insertions(+), 24 deletions(-) diff --git a/drivers/mtd/spi-nor/core.c b/drivers/mtd/spi-nor/core.c index 4e2ae6642d4c..8e4ae1317870 100644 --- a/drivers/mtd/spi-nor/core.c +++ b/drivers/mtd/spi-nor/core.c @@ -3294,39 +3294,36 @@ static const struct flash_info *spi_nor_match_name(= struct spi_nor *nor, static const struct flash_info *spi_nor_get_flash_info(struct spi_nor *nor, const char *name) { - const struct flash_info *info =3D NULL; + const struct flash_info *jinfo =3D NULL, *info =3D NULL; =20 if (name) info =3D spi_nor_match_name(nor, name); - /* Try to auto-detect if chip name wasn't specified or not found */ - if (!info) - return spi_nor_detect(nor); - /* - * If caller has specified name of flash model that can normally be - * detected using JEDEC, let's verify it. + * Auto-detect if chip name wasn't specified or not found, or the chip + * has an ID. If the chip supposedly has an ID, we also do an + * auto-detection to compare it later. */ - if (name && info->id) { - const struct flash_info *jinfo; - + if (!info || info->id) { jinfo =3D spi_nor_detect(nor); - if (IS_ERR(jinfo)) { + if (IS_ERR(jinfo)) return jinfo; - } else if (jinfo !=3D info) { - /* - * JEDEC knows better, so overwrite platform ID. We - * can't trust partitions any longer, but we'll let - * mtd apply them anyway, since some partitions may be - * marked read-only, and we don't want to loose that - * information, even if it's not 100% accurate. - */ - dev_warn(nor->dev, "found %s, expected %s\n", - jinfo->name, info->name); - info =3D jinfo; - } } =20 - return info; + /* + * If caller has specified name of flash model that can normally be + * detected using JEDEC, let's verify it. + */ + if (info && jinfo && jinfo !=3D info) + dev_warn(nor->dev, "found %s, expected %s\n", + jinfo->name, info->name); + + /* + * JEDEC knows better, so overwrite platform ID. We can't trust + * partitions any longer, but we'll let mtd apply them anyway, since + * some partitions may be marked read-only, and we don't want to loose + * that information, even if it's not 100% accurate. + */ + return jinfo ?: info; } =20 static u32 --=20 2.39.2 From nobody Mon Feb 9 08:54:16 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 446E412FB24 for ; Fri, 19 Apr 2024 14:14:21 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1713536061; cv=none; b=rNh1VQeofkffRzEVF+7Ph9ZeNEJSTcd7aXlRpcJO8tdrDszfpTb5AJZOzweOzp0Te3Td9SdXv1nIK6fN7vR0/ZmlyLqHNBcquE3q1bqFSuDYlHYXmROXjpeETsfIMO6rqyr1l3A/eUY7S74Y+vxBPV3rW1mLEDZ3ypaJ61LdSFM= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1713536061; c=relaxed/simple; bh=p/3JPIvR/iX1VY60SIuTHKNJqMHHtyy/NyXLubcttms=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=CqgqbmvDRE5+f8mOq4Vld1vYOSm5rOp1AIK3omBdr37U3GYifIKnCOMMq+m08G7M76LkZzlBXHZWTTQLVqo094N4O+E6whJ6oRfdomwUG1zIygRVADXStG2FLhlLlYLNZ9KyZ6GEybE8ygMaRkvW5PZe2URuK61C7+hKTvLM2Ug= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=bJVVUFV0; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="bJVVUFV0" Received: by smtp.kernel.org (Postfix) with ESMTPSA id E9E07C3277B; Fri, 19 Apr 2024 14:14:18 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1713536060; bh=p/3JPIvR/iX1VY60SIuTHKNJqMHHtyy/NyXLubcttms=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=bJVVUFV02+KHL3buUmmT6Sw5mV7TaTRqwi/xOTm6e/qPBQK/6S5Qlx4wXwoWL1fzz FQvNPvlQ2aVg3S3LnsuwQ5E6bHxfRg5eszKSVQ9GPpPMuA05ouaGbJ3CDiRHMPje1G a3cvjuMayNDtGnQfBP3LIkplmXPKrhXjtePh8vd9FBGGfM9gtqZEFvrUre3v9+IyeN duB8CzM2Z4GePy/DWd7Eq1FjsJsfM7eGN+Qv7eH1L7s8h6NyhnD+vR56qBZ/Nxb9n9 pZTh1IT/0liGLNoCDFN1KMaVeMn3U/yhRWIoq7kcgvT6suf/3+b+l/Xzos18P+87q5 XjSZ/0xYRt6VQ== From: Michael Walle To: Tudor Ambarus , Pratyush Yadav , Miquel Raynal , Richard Weinberger , Vignesh Raghavendra Cc: Ricardo Ribalda , linux-kernel@vger.kernel.org, linux-mtd@lists.infradead.org, Michael Walle Subject: [PATCH v2 6/6] mtd: spi-nor: introduce support for displaying deprecation message Date: Fri, 19 Apr 2024 16:12:49 +0200 Message-Id: <20240419141249.609534-7-mwalle@kernel.org> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20240419141249.609534-1-mwalle@kernel.org> References: <20240419141249.609534-1-mwalle@kernel.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" SPI-NOR will automatically detect the attached flash device most of the time. We cannot easily find out if boards are using a given flash. Therefore, add a .deprecation_version to the flash_info struct which indicates the kernel version after which the driver support will be removed. Signed-off-by: Michael Walle Reviewed-by: Pratyush Yadav Reviewed-by: Tudor Ambarus --- drivers/mtd/spi-nor/core.c | 11 ++++++++++- drivers/mtd/spi-nor/core.h | 3 +++ 2 files changed, 13 insertions(+), 1 deletion(-) diff --git a/drivers/mtd/spi-nor/core.c b/drivers/mtd/spi-nor/core.c index 8e4ae1317870..bed5209b94de 100644 --- a/drivers/mtd/spi-nor/core.c +++ b/drivers/mtd/spi-nor/core.c @@ -3323,7 +3323,16 @@ static const struct flash_info *spi_nor_get_flash_in= fo(struct spi_nor *nor, * some partitions may be marked read-only, and we don't want to loose * that information, even if it's not 100% accurate. */ - return jinfo ?: info; + if (jinfo) + info =3D jinfo; + + if (info && info->deprecation_version) + pr_warn("Your board is using a SPI NOR flash (%s) with deprecated driver= \n" + "support. It will be removed after kernel version %s.\n" + "If you feel this shouldn't be the case, please contact us at\n" + "linux-mtd@lists.infradead.org\n", + info->name, info->deprecation_version); + return info; } =20 static u32 diff --git a/drivers/mtd/spi-nor/core.h b/drivers/mtd/spi-nor/core.h index 1516b6d0dc37..984155d10fd8 100644 --- a/drivers/mtd/spi-nor/core.h +++ b/drivers/mtd/spi-nor/core.h @@ -447,6 +447,8 @@ struct spi_nor_id { * @id: pointer to struct spi_nor_id or NULL, which means "no ID" (mostly * older chips). * @name: (obsolete) the name of the flash. Do not set it for new addition= s. + * @deprecation_version: the kernel version after which the support f= or + * this flash will be removed. * @size: the size of the flash in bytes. * @sector_size: (optional) the size listed here is what works with * SPINOR_OP_SE, which isn't necessarily called a "sector= " by @@ -504,6 +506,7 @@ struct spi_nor_id { struct flash_info { char *name; const struct spi_nor_id *id; + const char *deprecation_version; size_t size; unsigned sector_size; u16 page_size; --=20 2.39.2