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([202.83.99.71]) by smtp.gmail.com with ESMTPSA id hg19-20020a17090b301300b0029c472ec962sm4430566pjb.47.2024.04.19.01.51.48 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 19 Apr 2024 01:51:51 -0700 (PDT) From: Daniel J Blueman To: Thomas Gleixner , Ingo Molnar , Borislav Petkov , Dave Hansen Cc: x86@kernel.org, "H. Peter Anvin" , "Peter Zijlstra" , linux-kernel@vger.kernel.org, Daniel J Blueman , Steffen Persvold , James Cleverdon , Dimitri Sivanich , Steve Wahl , Prarit Bhargava , Frank Ramsay , Russ Anderson Subject: [PATCH v2] x86: Trust initial offset in architectural TSC-adjust MSRs Date: Fri, 19 Apr 2024 16:51:46 +0800 Message-Id: <20240419085146.175665-1-daniel@quora.org> X-Mailer: git-send-email 2.40.1 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" When the BIOS configures the architectural TSC-adjust MSRs on secondary sockets to correct a constant inter-chassis offset, after Linux brings the cores online, the TSC sync check later resets the core-local MSR to 0, triggering HPET fallback and leading to performance loss. Fix this by unconditionally using the initial adjust values read from the MSRs. Trusting the initial offsets in this architectural mechanism is a better approach than special-casing workarounds for specific platforms. Signed-off-by: Daniel J Blueman Reviewed-by: Steffen Persvold Reviewed-by: James Cleverdon Reviewed-by: Dimitri Sivanich Cc: Steve Wahl Cc: Prarit Bhargava Cc: Frank Ramsay Cc: Russ Anderson Reviewed-by: Prarit Bhargava --- Changes in v2: - Maintain comment based on feedback - Rebase against v6.9-rc4 arch/x86/kernel/tsc_sync.c | 6 ++---- 1 file changed, 2 insertions(+), 4 deletions(-) diff --git a/arch/x86/kernel/tsc_sync.c b/arch/x86/kernel/tsc_sync.c index 1123ef3ccf90..4334033658ed 100644 --- a/arch/x86/kernel/tsc_sync.c +++ b/arch/x86/kernel/tsc_sync.c @@ -193,11 +193,9 @@ bool tsc_store_and_check_tsc_adjust(bool bootcpu) cur->warned =3D false; =20 /* - * If a non-zero TSC value for socket 0 may be valid then the default - * adjusted value cannot assumed to be zero either. + * The default adjust value cannot be assumed to be zero on any socket. */ - if (tsc_async_resets) - cur->adjusted =3D bootval; + cur->adjusted =3D bootval; =20 /* * Check whether this CPU is the first in a package to come up. In --=20 2.40.1