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([2a01:e0a:999:a3a0:7b64:4d1d:16d8:e38b]) by smtp.gmail.com with ESMTPSA id v10-20020a05600c470a00b00418a386c059sm2873645wmo.42.2024.04.18.07.27.10 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 18 Apr 2024 07:27:10 -0700 (PDT) From: =?UTF-8?q?Cl=C3=A9ment=20L=C3=A9ger?= To: Conor Dooley , Rob Herring , Krzysztof Kozlowski , Paul Walmsley , Palmer Dabbelt , Albert Ou , Anup Patel , Atish Patra Cc: =?UTF-8?q?Cl=C3=A9ment=20L=C3=A9ger?= , linux-riscv@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, kvm@vger.kernel.org, kvm-riscv@lists.infradead.org, Ved Shanbhogue Subject: [RFC PATCH 1/7] riscv: kvm: add support for FWFT SBI extension Date: Thu, 18 Apr 2024 16:26:40 +0200 Message-ID: <20240418142701.1493091-2-cleger@rivosinc.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240418142701.1493091-1-cleger@rivosinc.com> References: <20240418142701.1493091-1-cleger@rivosinc.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Add support for FWFT extension in KVM Signed-off-by: Cl=C3=A9ment L=C3=A9ger --- arch/riscv/include/asm/kvm_host.h | 5 + arch/riscv/include/asm/kvm_vcpu_sbi.h | 1 + arch/riscv/include/asm/kvm_vcpu_sbi_fwft.h | 37 ++++++ arch/riscv/include/uapi/asm/kvm.h | 1 + arch/riscv/kvm/Makefile | 1 + arch/riscv/kvm/vcpu.c | 5 + arch/riscv/kvm/vcpu_sbi.c | 4 + arch/riscv/kvm/vcpu_sbi_fwft.c | 136 +++++++++++++++++++++ 8 files changed, 190 insertions(+) create mode 100644 arch/riscv/include/asm/kvm_vcpu_sbi_fwft.h create mode 100644 arch/riscv/kvm/vcpu_sbi_fwft.c diff --git a/arch/riscv/include/asm/kvm_host.h b/arch/riscv/include/asm/kvm= _host.h index 484d04a92fa6..be60aaa07f57 100644 --- a/arch/riscv/include/asm/kvm_host.h +++ b/arch/riscv/include/asm/kvm_host.h @@ -19,6 +19,7 @@ #include #include #include +#include #include #include =20 @@ -169,6 +170,7 @@ struct kvm_vcpu_csr { struct kvm_vcpu_config { u64 henvcfg; u64 hstateen0; + u64 hedeleg; }; =20 struct kvm_vcpu_smstateen_csr { @@ -261,6 +263,9 @@ struct kvm_vcpu_arch { /* Performance monitoring context */ struct kvm_pmu pmu_context; =20 + /* Firmware feature SBI extension context */ + struct kvm_sbi_fwft fwft_context; + /* 'static' configurations which are set only once */ struct kvm_vcpu_config cfg; =20 diff --git a/arch/riscv/include/asm/kvm_vcpu_sbi.h b/arch/riscv/include/asm= /kvm_vcpu_sbi.h index b96705258cf9..3a33bbacc233 100644 --- a/arch/riscv/include/asm/kvm_vcpu_sbi.h +++ b/arch/riscv/include/asm/kvm_vcpu_sbi.h @@ -86,6 +86,7 @@ extern const struct kvm_vcpu_sbi_extension vcpu_sbi_ext_s= rst; extern const struct kvm_vcpu_sbi_extension vcpu_sbi_ext_hsm; extern const struct kvm_vcpu_sbi_extension vcpu_sbi_ext_dbcn; extern const struct kvm_vcpu_sbi_extension vcpu_sbi_ext_sta; +extern const struct kvm_vcpu_sbi_extension vcpu_sbi_ext_fwft; extern const struct kvm_vcpu_sbi_extension vcpu_sbi_ext_experimental; extern const struct kvm_vcpu_sbi_extension vcpu_sbi_ext_vendor; =20 diff --git a/arch/riscv/include/asm/kvm_vcpu_sbi_fwft.h b/arch/riscv/includ= e/asm/kvm_vcpu_sbi_fwft.h new file mode 100644 index 000000000000..7dc1b80c7e6c --- /dev/null +++ b/arch/riscv/include/asm/kvm_vcpu_sbi_fwft.h @@ -0,0 +1,37 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2023 Rivos Inc + * + * Authors: + * Atish Patra + */ + +#ifndef __KVM_VCPU_RISCV_FWFT_H +#define __KVM_VCPU_RISCV_FWFT_H + +#include + +#define KVM_SBI_FWFT_FEATURE_COUNT 1 + +struct kvm_sbi_fwft_config; +struct kvm_vcpu; + +struct kvm_sbi_fwft_feature { + enum sbi_fwft_feature_t id; + int (*set)(struct kvm_vcpu *vcpu, struct kvm_sbi_fwft_config *conf, unsig= ned long value); + int (*get)(struct kvm_vcpu *vcpu, struct kvm_sbi_fwft_config *conf, unsig= ned long *value); +}; + +struct kvm_sbi_fwft_config { + const struct kvm_sbi_fwft_feature *feature; + unsigned long flags; +}; + +/* FWFT data structure per vcpu */ +struct kvm_sbi_fwft { + struct kvm_sbi_fwft_config configs[KVM_SBI_FWFT_FEATURE_COUNT]; +}; + +#define vcpu_to_fwft(vcpu) (&(vcpu)->arch.fwft_context) + +#endif /* !__KVM_VCPU_RISCV_FWFT_H */ diff --git a/arch/riscv/include/uapi/asm/kvm.h b/arch/riscv/include/uapi/as= m/kvm.h index 7499e88a947c..fa3097da91c0 100644 --- a/arch/riscv/include/uapi/asm/kvm.h +++ b/arch/riscv/include/uapi/asm/kvm.h @@ -185,6 +185,7 @@ enum KVM_RISCV_SBI_EXT_ID { KVM_RISCV_SBI_EXT_VENDOR, KVM_RISCV_SBI_EXT_DBCN, KVM_RISCV_SBI_EXT_STA, + KVM_RISCV_SBI_EXT_FWFT, KVM_RISCV_SBI_EXT_MAX, }; =20 diff --git a/arch/riscv/kvm/Makefile b/arch/riscv/kvm/Makefile index c9646521f113..19175bd5b40a 100644 --- a/arch/riscv/kvm/Makefile +++ b/arch/riscv/kvm/Makefile @@ -27,6 +27,7 @@ kvm-y +=3D vcpu_sbi_base.o kvm-y +=3D vcpu_sbi_replace.o kvm-y +=3D vcpu_sbi_hsm.o kvm-y +=3D vcpu_sbi_sta.o +kvm-y +=3D vcpu_sbi_fwft.o kvm-y +=3D vcpu_timer.o kvm-$(CONFIG_RISCV_PMU_SBI) +=3D vcpu_pmu.o vcpu_sbi_pmu.o kvm-y +=3D aia.o diff --git a/arch/riscv/kvm/vcpu.c b/arch/riscv/kvm/vcpu.c index b5ca9f2e98ac..461ef60d4eda 100644 --- a/arch/riscv/kvm/vcpu.c +++ b/arch/riscv/kvm/vcpu.c @@ -505,6 +505,8 @@ static void kvm_riscv_vcpu_setup_config(struct kvm_vcpu= *vcpu) if (riscv_isa_extension_available(isa, SMSTATEEN)) cfg->hstateen0 |=3D SMSTATEEN0_SSTATEEN0; } + + cfg->hedeleg =3D csr_read(CSR_HEDELEG); } =20 void kvm_arch_vcpu_load(struct kvm_vcpu *vcpu, int cpu) @@ -521,6 +523,7 @@ void kvm_arch_vcpu_load(struct kvm_vcpu *vcpu, int cpu) csr_write(CSR_VSTVAL, csr->vstval); csr_write(CSR_HVIP, csr->hvip); csr_write(CSR_VSATP, csr->vsatp); + csr_write(CSR_HEDELEG, cfg->hedeleg); csr_write(CSR_HENVCFG, cfg->henvcfg); if (IS_ENABLED(CONFIG_32BIT)) csr_write(CSR_HENVCFGH, cfg->henvcfg >> 32); @@ -551,6 +554,7 @@ void kvm_arch_vcpu_load(struct kvm_vcpu *vcpu, int cpu) void kvm_arch_vcpu_put(struct kvm_vcpu *vcpu) { struct kvm_vcpu_csr *csr =3D &vcpu->arch.guest_csr; + struct kvm_vcpu_config *cfg =3D &vcpu->arch.cfg; =20 vcpu->cpu =3D -1; =20 @@ -574,6 +578,7 @@ void kvm_arch_vcpu_put(struct kvm_vcpu *vcpu) csr->vstval =3D csr_read(CSR_VSTVAL); csr->hvip =3D csr_read(CSR_HVIP); csr->vsatp =3D csr_read(CSR_VSATP); + cfg->hedeleg =3D csr_read(CSR_HEDELEG); } =20 static void kvm_riscv_check_vcpu_requests(struct kvm_vcpu *vcpu) diff --git a/arch/riscv/kvm/vcpu_sbi.c b/arch/riscv/kvm/vcpu_sbi.c index 72a2ffb8dcd1..76901f0f34b7 100644 --- a/arch/riscv/kvm/vcpu_sbi.c +++ b/arch/riscv/kvm/vcpu_sbi.c @@ -74,6 +74,10 @@ static const struct kvm_riscv_sbi_extension_entry sbi_ex= t[] =3D { .ext_idx =3D KVM_RISCV_SBI_EXT_STA, .ext_ptr =3D &vcpu_sbi_ext_sta, }, + { + .ext_idx =3D KVM_RISCV_SBI_EXT_FWFT, + .ext_ptr =3D &vcpu_sbi_ext_fwft, + }, { .ext_idx =3D KVM_RISCV_SBI_EXT_EXPERIMENTAL, .ext_ptr =3D &vcpu_sbi_ext_experimental, diff --git a/arch/riscv/kvm/vcpu_sbi_fwft.c b/arch/riscv/kvm/vcpu_sbi_fwft.c new file mode 100644 index 000000000000..b9b7f8fa6d22 --- /dev/null +++ b/arch/riscv/kvm/vcpu_sbi_fwft.c @@ -0,0 +1,136 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) 2021 Western Digital Corporation or its affiliates. + * + * Authors: + * Atish Patra + */ + +#include +#include +#include +#include +#include +#include + +#define MIS_DELEG (1UL << EXC_LOAD_MISALIGNED | 1UL << EXC_STORE_MISALIGNE= D) + +static int kvm_sbi_fwft_set_misaligned_delegation(struct kvm_vcpu *vcpu, + struct kvm_sbi_fwft_config *conf, + unsigned long value) +{ + if (value) + csr_set(CSR_HEDELEG, MIS_DELEG); + else + csr_clear(CSR_HEDELEG, MIS_DELEG); + + return SBI_SUCCESS; +} + +static int kvm_sbi_fwft_get_misaligned_delegation(struct kvm_vcpu *vcpu, + struct kvm_sbi_fwft_config *conf, + unsigned long *value) +{ + *value =3D (csr_read(CSR_HEDELEG) & MIS_DELEG) !=3D 0; + + return SBI_SUCCESS; +} + +static struct kvm_sbi_fwft_config * +kvm_sbi_fwft_get_config(struct kvm_vcpu *vcpu, enum sbi_fwft_feature_t fea= ture) +{ + int i =3D 0; + struct kvm_sbi_fwft *fwft =3D vcpu_to_fwft(vcpu); + + for (i =3D 0; i < KVM_SBI_FWFT_FEATURE_COUNT; i++) { + if (fwft->configs[i].feature->id =3D=3D feature) + return &fwft->configs[i]; + } + + return NULL; +} + +static int kvm_sbi_fwft_set(struct kvm_vcpu *vcpu, + enum sbi_fwft_feature_t feature, + unsigned long value, unsigned long flags) +{ + struct kvm_sbi_fwft_config *conf =3D kvm_sbi_fwft_get_config(vcpu, + feature); + if (!conf) + return SBI_ERR_DENIED; + + if ((flags & ~SBI_FWFT_SET_FLAG_LOCK) !=3D 0) + return SBI_ERR_INVALID_PARAM; + + if (conf->flags & SBI_FWFT_SET_FLAG_LOCK) + return SBI_ERR_DENIED; + + conf->flags =3D flags; + + return conf->feature->set(vcpu, conf, value); +} + +static int kvm_sbi_fwft_get(struct kvm_vcpu *vcpu, + enum sbi_fwft_feature_t feature, + unsigned long *value) +{ + struct kvm_sbi_fwft_config *conf =3D kvm_sbi_fwft_get_config(vcpu, + feature); + if (!conf) + return SBI_ERR_DENIED; + + return conf->feature->get(vcpu, conf, value); +} + +static int kvm_sbi_ext_fwft_handler(struct kvm_vcpu *vcpu, struct kvm_run = *run, + struct kvm_vcpu_sbi_return *retdata) +{ + int ret =3D 0; + struct kvm_cpu_context *cp =3D &vcpu->arch.guest_context; + unsigned long funcid =3D cp->a6; + + switch (funcid) { + case SBI_EXT_FWFT_SET: + ret =3D kvm_sbi_fwft_set(vcpu, cp->a0, cp->a1, cp->a2); + break; + case SBI_EXT_FWFT_GET: + ret =3D kvm_sbi_fwft_get(vcpu, cp->a0, &retdata->out_val); + break; + default: + ret =3D SBI_ERR_NOT_SUPPORTED; + break; + } + + retdata->err_val =3D ret; + + return 0; +} + +static const struct kvm_sbi_fwft_feature features[] =3D { + { + .id =3D SBI_FWFT_MISALIGNED_DELEG, + .set =3D kvm_sbi_fwft_set_misaligned_delegation, + .get =3D kvm_sbi_fwft_get_misaligned_delegation, + } +}; + +static_assert(ARRAY_SIZE(features) =3D=3D KVM_SBI_FWFT_FEATURE_COUNT); + + +static unsigned long kvm_sbi_ext_fwft_probe(struct kvm_vcpu *vcpu) +{ + struct kvm_sbi_fwft *fwft =3D vcpu_to_fwft(vcpu); + int i; + + for (i =3D 0; i < ARRAY_SIZE(features); i++) + fwft->configs[i].feature =3D &features[i]; + + return 1; +} + +const struct kvm_vcpu_sbi_extension vcpu_sbi_ext_fwft =3D { + .extid_start =3D SBI_EXT_FWFT, + .extid_end =3D SBI_EXT_FWFT, + .handler =3D kvm_sbi_ext_fwft_handler, + .probe =3D kvm_sbi_ext_fwft_probe, +}; --=20 2.43.0