From nobody Sat May 18 08:35:52 2024 Received: from smtpdh20-1.aruba.it (smtpdh20-1.aruba.it [62.149.155.164]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A77C015FD16 for ; Thu, 18 Apr 2024 13:42:34 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=62.149.155.164 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1713447758; cv=none; b=UCCwsXfWbGMJchTEWuYSLMQRaAwXCWanY8Ra50htwHuvTEO6H4nSNvBiPn2O7s2/Ok5hGYaeGxlm/mmjennpUwc5Bsh0ItNIqwk9rZcsWYIvLPQfX2QwCsJk834h61dD02skXo5vfrvofr/5Hf28JEq2VdqODhZ6z82d2kaOJP4= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1713447758; c=relaxed/simple; bh=BPnGJTtrBvdVCZOyJP7914EN0dAiey74ztwFVJtarM4=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=Nk/Tyg6noyXvFJKusLOlrXwpApKI2A2kC4WNo9TDvwP5keSURZ9R3kNXC+mh1WMWmklU8Zz1I166LscWAlejZau0vjG0RnjNrAeur9Zr4zAgoePF0BeTYTBP1w9K2RF3P/YJoNz/O42a8ScHb7ufxNRQGRYE3IGq8GOSV+dA7OE= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=engicam.com; spf=pass smtp.mailfrom=engicam.com; dkim=pass (2048-bit key) header.d=aruba.it header.i=@aruba.it header.b=FspPPls3; arc=none smtp.client-ip=62.149.155.164 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=engicam.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=engicam.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=aruba.it header.i=@aruba.it header.b="FspPPls3" Received: from engicam.com ([146.241.28.123]) by Aruba Outgoing Smtp with ESMTPSA id xRz2rgYv8wWj2xRz4rpftO; Thu, 18 Apr 2024 15:39:26 +0200 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=aruba.it; s=a1; t=1713447566; bh=BPnGJTtrBvdVCZOyJP7914EN0dAiey74ztwFVJtarM4=; h=From:To:Subject:Date:MIME-Version; b=FspPPls3NCm0nYqZeYqlkCZgQ3zN+iDB9qLoxTr2Pnhtzm2uYtsJaLOZfG2h4jB/8 GmMy7fdKJvEGe+P+4lNshPhKZBnx20HsNCaYzqBHYelZOI8GyzJfIeDd3g3zHU+FQE V4R3ij8SkHYLLJE6iGRh+1P1Iw91/2BmMWO/H/rD8MqhjnVswz9C/7JFK3J7qqlHyL Jh25uR64I/8IWu2s2NBf9l+goMQNsukmRa3N7LulaCYBRx2piZ6baCiLuCGYH+uC+q yr0OMdSH3zBJ2b8Dm/bvGMVJTsfs7qOBYGtl74uFO79lCl9X2bVXag7cZa1sjs7EKK 0tLA0nRJ6e1lg== From: Fabio Aiuto To: Shawn Guo , Sascha Hauer , Krzysztof Kozlowski , Rob Herring , Conor Dooley Cc: devicetree@vger.kernel.org, imx@lists.linux.dev, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Fabio Aiuto , Matteo Lisi , Mirko Ardinghi Subject: [PATCH v2 1/3] dt-bindings: arm: fsl: add Engicam i.Core MX93 EDIMM 2.0 Starter Kit Date: Thu, 18 Apr 2024 15:39:21 +0200 Message-Id: <20240418133923.3705-2-fabio.aiuto@engicam.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240418133923.3705-1-fabio.aiuto@engicam.com> References: <20240418133923.3705-1-fabio.aiuto@engicam.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CMAE-Envelope: MS4xfLPJjMyjuC46EePe1tB96/9btQeWSPEKQd8nMiBOciL4/I/k80FuI2OCQZSoAVSxtrbAPJcmCyYr7zN2Fw1D1aVoW/BQPbue5kadG7bPGNMAufDG97zR DTIqauKgc9+6o+lE9x9k8tvP0SGnOiLgFoE4CGm0MArZmlpdj8ewoVcgtyKWk5HW4YuKlvVnAFB3ZVFOoVAo3Kxf31Lk5Zq1+0eqvx1/c2LKKAmWh7XndKP8 N/JJ+QzDmUN+riSRkQ6cdU25hIxHehCNmNxsLrAndngSlAFFMgSPFlufKBV3LUHAsqB/tVlRsvY1yXQ3l3Diq3amCWHcRQfDFR6N+ZkBfFZ8O1UvcgFZyANW JqHNNg/MCyV1tsjFo6ZZl9KnkMYOYeM7SZGaVqEF+XT+u+8pveRc6kPSZufFfy62wQ1nz30akqCTo8HYCZca+utl010WIQOTmJJ9IH75mxfv39BHfGFVYd9r ZgQG4ywkWD72irQwXnnZpH6xOIL2N7+DgOIxnOP8iG/UTD7kGjE31TgePG/E8U8kIoKI4+ojQZh0Ugplr5H0omiv45+cmkw3eb1puMSGCEw+1lsnxfxyMwsJ nWmb+q0zQkQ09T/HFzrw0wdO Content-Type: text/plain; charset="utf-8" i.Core MX93 is a NXP i.MX93 based EDIMM SoM by Engicam. EDIMM 2.0 Starter Kit is an EDIMM 2.0 Form Factor Capacitive Evaluation Board by Engicam. i.Core MX93 needs to be mounted on top of EDIMM 2.0 Starter Kit to get the full i.Core MX93 EDIMM 2.0 Starter Kit board. Add bindings for this board. Cc: Matteo Lisi Cc: Mirko Ardinghi Signed-off-by: Fabio Aiuto Acked-by: Conor Dooley --- Documentation/devicetree/bindings/arm/fsl.yaml | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/fsl.yaml b/Documentation= /devicetree/bindings/arm/fsl.yaml index 0027201e19f8..b497a01c7418 100644 --- a/Documentation/devicetree/bindings/arm/fsl.yaml +++ b/Documentation/devicetree/bindings/arm/fsl.yaml @@ -1265,6 +1265,13 @@ properties: - fsl,imx93-11x11-evk # i.MX93 11x11 EVK Board - const: fsl,imx93 =20 + - description: Engicam i.Core MX93 based Boards + items: + - enum: + - engicam,icore-mx93-edimm2 # i.MX93 Engicam i.Core = MX93 EDIMM 2.0 Starter Kit + - const: engicam,icore-mx93 # i.MX93 Engicam i.Core = MX93 Som + - const: fsl,imx93 + - description: i.MXRT1050 based Boards items: - enum: --=20 2.34.1 From nobody Sat May 18 08:35:52 2024 Received: from smtpdh20-1.aruba.it (smtpdh20-1.aruba.it [62.149.155.164]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C59CB160790 for ; Thu, 18 Apr 2024 13:42:35 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=62.149.155.164 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1713447758; cv=none; b=loaFl50gvAb081Jqs7GI7HRFjwFfMv80iALgDCJbMMXW3YsLEC7GZQObk+4mtmDURT5qugVs13PBDwKmGep6ht7PrG1zOqU++UDFOic6XBPTYZJrL1Vn8MpvGuVzkB36J6I5euMBp2vnepLHtYiFrIQBoTCGArEFFNC1fO+9uTQ= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1713447758; c=relaxed/simple; bh=mpFZYKCt93SqfoLhuHIZOZAQ++GU5Ok3udg5m7tT/8M=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=oUVzG9U8sUR6yq/KjLkQ2xRL+pzTAPMywFGfwLv4T88QvJtizPhcGGUEGILY38O8uZp1S2qkQh6EAjEuY5gDlocMgEUN21ZveGr9Qsxsqt3VZ47r/g9gNqQ+Z74SJNPUPNL1th4MSOTtaZYFxw9I5pPdb4VqbbPdDcYJgtLRAaI= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=engicam.com; spf=pass smtp.mailfrom=engicam.com; dkim=pass (2048-bit key) header.d=aruba.it header.i=@aruba.it header.b=far4rUyg; arc=none smtp.client-ip=62.149.155.164 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=engicam.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=engicam.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=aruba.it header.i=@aruba.it header.b="far4rUyg" Received: from engicam.com ([146.241.28.123]) by Aruba Outgoing Smtp with ESMTPSA id xRz2rgYv8wWj2xRz4rpftj; Thu, 18 Apr 2024 15:39:27 +0200 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=aruba.it; s=a1; t=1713447567; bh=mpFZYKCt93SqfoLhuHIZOZAQ++GU5Ok3udg5m7tT/8M=; h=From:To:Subject:Date:MIME-Version; b=far4rUygRxzJP/Cp9lGz2OV2dSDHFmi/DwbPBahH49WgUET00QyL5VzranbavdHOk wmRuVe1CPFWi3LmMP1SnGlaKPIoAcItzYWwgleRXziHbK/IBWiJh2gWt0X1HDGG/tN NzxoATGs+esk8Jh8k9V4RW4AGheK3zH6giaolt9V0mJJZZUs4nBu9F9+WqFiSAw4qr 7D+2zyaKMF3yq7GYtRpk+iYoqOZ3VKp9Mq7zSdpjHoChyFo+B8EgSbyrLdLuXLHbp9 sHrgKYKPN1Sjo13hgPsAXglFKB/iGxjmCFouoadcQ+MXfAhpX1i//RcScQsSwR1nlG OdB80tube9Q7Q== From: Fabio Aiuto To: Shawn Guo , Sascha Hauer , Krzysztof Kozlowski , Rob Herring , Conor Dooley Cc: devicetree@vger.kernel.org, imx@lists.linux.dev, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Fabio Aiuto , Matteo Lisi , Mirko Ardinghi Subject: [PATCH v2 2/3] arm64: dts: imx93: add Engicam i.Core MX93 SoM Date: Thu, 18 Apr 2024 15:39:22 +0200 Message-Id: <20240418133923.3705-3-fabio.aiuto@engicam.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240418133923.3705-1-fabio.aiuto@engicam.com> References: <20240418133923.3705-1-fabio.aiuto@engicam.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CMAE-Envelope: MS4xfH0Xu1I2PZhjsA3o4vjTvidBnaRm6j9UVTMgWSASu9RageXyPbhV0dn4aleZWyd/cR5jbpry8cyo2KnOMzSbOtzCHAZJQtNwuceAjFlVc9kwIKPfitUF u27oTAwnz2ggk+Ng1v7r8OVJ55XmzydewgJPZVzS1Pi4wSnKchYh8olYFydFI+R1iPpMh85e1GSDoXLfxAbBlEotcaZjGacXua+lGGIZD6nd7CtP4kNIJiIM O9fL03X8nycWSa5AL6x2G1drH93R9UFOuXAIVs0HmUdMzSbYK0mL6H+piO0PC7vW1f0HDxyHBdLjb/Ta41lBtVa3Vv3ccXKOxW2F2Ks6RT7OLrCrT0CF20eB xTYB0nUrEvad5O8i261CFxVCmS8QcVaVfhhfxiEfVpDNLX+VuobjZttm1hLlexzs7Y15aGjZ2Fm6Bs320P9c6Inah4I5e6hWyFyHNq3Mto3B+BDnmii6gPcT 7nmBo64P0WeYnxPfElDb89KthTFtFjZEcVovLQBP2rjtqPNITsKgQTqakKK2hM//sRCdlHt88oRYOmKE+dSJ72RKATfWudkgcRKbYG7M0KtDS9WddGK0fm2s I0JBpj4qng7F89pieCvP9vKS Content-Type: text/plain; charset="utf-8" i.Core MX93 is a NXP i.MX93 based EDIMM SoM by Engicam. Main features: CPU: NXP i.MX 93 MEMORY: Up to 2GB LPDDR4 NETWORKING: 2x Gb Ethernet USB: USB OTG 2.0, USB HOST 2.0 STORAGE: eMMC starting from 4GB PERIPHERALS: UART, I2C, SPI, CAN, SDIO, GPIO The i.Core MX93 needs to be mounted on top of Engicam baseboards to work. Add devicetree include file. Cc: Matteo Lisi Cc: Mirko Ardinghi Signed-off-by: Fabio Aiuto --- .../boot/dts/freescale/imx93-icore-mx93.dtsi | 270 ++++++++++++++++++ 1 file changed, 270 insertions(+) create mode 100644 arch/arm64/boot/dts/freescale/imx93-icore-mx93.dtsi diff --git a/arch/arm64/boot/dts/freescale/imx93-icore-mx93.dtsi b/arch/arm= 64/boot/dts/freescale/imx93-icore-mx93.dtsi new file mode 100644 index 000000000000..c4bed6da389d --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx93-icore-mx93.dtsi @@ -0,0 +1,270 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2022 NXP + * Copyright 2024 Engicam s.r.l. + */ + +/dts-v1/; + +#include "imx93.dtsi" + +/ { + model =3D "Engicam i.Core MX93 SoM"; + compatible =3D "engicam,icore-mx93", "fsl,imx93"; + + reg_vref_1v8: regulator-adc-vref { + compatible =3D "regulator-fixed"; + regulator-name =3D "vref_1v8"; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + }; +}; + +&adc1 { + vref-supply =3D <®_vref_1v8>; + status =3D "okay"; +}; + +&eqos { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_eqos>; + phy-mode =3D "rgmii-id"; + phy-handle =3D <ðphy1>; + status =3D "okay"; + + mdio { + compatible =3D "snps,dwmac-mdio"; + #address-cells =3D <1>; + #size-cells =3D <0>; + + ethphy1: ethernet-phy@7 { + compatible =3D "ethernet-phy-ieee802.3-c22"; + reg =3D <7>; + }; + }; +}; + +&fec { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_fec>; + phy-mode =3D "rgmii-id"; + phy-handle =3D <ðphy2>; + fsl,magic-packet; + status =3D "okay"; + + mdio { + #address-cells =3D <1>; + #size-cells =3D <0>; + + ethphy2: ethernet-phy@7 { + compatible =3D "ethernet-phy-ieee802.3-c22"; + reg =3D <7>; + }; + }; +}; + +&lpi2c2 { + #address-cells =3D <1>; + #size-cells =3D <0>; + clock-frequency =3D <400000>; + pinctrl-names =3D "default", "sleep"; + pinctrl-0 =3D <&pinctrl_lpi2c2>; + pinctrl-1 =3D <&pinctrl_lpi2c2>; + status =3D "okay"; + + pmic@25 { + compatible =3D "nxp,pca9451a"; + reg =3D <0x25>; + + interrupt-parent =3D <&gpio2>; + interrupts =3D <15 IRQ_TYPE_LEVEL_LOW>; + + regulators { + buck1: BUCK1 { + regulator-name =3D "BUCK1"; + regulator-min-microvolt =3D <600000>; + regulator-max-microvolt =3D <2187500>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay =3D <3125>; + }; + + buck2: BUCK2 { + regulator-name =3D "BUCK2"; + regulator-min-microvolt =3D <600000>; + regulator-max-microvolt =3D <2187500>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay =3D <3125>; + }; + + buck4: BUCK4{ + regulator-name =3D "BUCK4"; + regulator-min-microvolt =3D <600000>; + regulator-max-microvolt =3D <3400000>; + regulator-boot-on; + regulator-always-on; + }; + + buck5: BUCK5{ + regulator-name =3D "BUCK5"; + regulator-min-microvolt =3D <600000>; + regulator-max-microvolt =3D <3400000>; + regulator-boot-on; + regulator-always-on; + }; + + buck6: BUCK6 { + regulator-name =3D "BUCK6"; + regulator-min-microvolt =3D <600000>; + regulator-max-microvolt =3D <3400000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo1: LDO1 { + regulator-name =3D "LDO1"; + regulator-min-microvolt =3D <1600000>; + regulator-max-microvolt =3D <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo2: LDO2 { + regulator-name =3D "LDO2"; + regulator-min-microvolt =3D <800000>; + regulator-max-microvolt =3D <1150000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo3: LDO3 { + regulator-name =3D "LDO3"; + regulator-min-microvolt =3D <800000>; + regulator-max-microvolt =3D <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo4: LDO4 { + regulator-name =3D "LDO4"; + regulator-min-microvolt =3D <800000>; + regulator-max-microvolt =3D <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo5: LDO5 { + regulator-name =3D "LDO5"; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <3300000>; + regulator-boot-on; + regulator-always-on; + }; + }; + }; +}; + +&usdhc1 { + pinctrl-names =3D "default", "state_100mhz", "state_200mhz"; + pinctrl-0 =3D <&pinctrl_usdhc1>; + pinctrl-1 =3D <&pinctrl_usdhc1>; + pinctrl-2 =3D <&pinctrl_usdhc1>; + bus-width =3D <8>; + non-removable; + status =3D "okay"; +}; + +&usdhc2 {/*SD Card*/ + pinctrl-names =3D "default", "state_100mhz", "state_200mhz"; + pinctrl-0 =3D <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; + pinctrl-1 =3D <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; + pinctrl-2 =3D <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; + cd-gpios =3D <&gpio3 00 GPIO_ACTIVE_LOW>; + bus-width =3D <4>; + no-1-8-v; + max-frequency =3D <25000000>; + status =3D "okay"; +}; + +&iomuxc { + + pinctrl_eqos: eqosgrp { + fsl,pins =3D < + MX93_PAD_ENET1_MDC__ENET_QOS_MDC 0x53e + MX93_PAD_ENET1_MDIO__ENET_QOS_MDIO 0x53e + MX93_PAD_ENET1_RD0__ENET_QOS_RGMII_RD0 0x53e + MX93_PAD_ENET1_RD1__ENET_QOS_RGMII_RD1 0x53e + MX93_PAD_ENET1_RD2__ENET_QOS_RGMII_RD2 0x53e + MX93_PAD_ENET1_RD3__ENET_QOS_RGMII_RD3 0x53e + MX93_PAD_ENET1_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK 0x53e + MX93_PAD_ENET1_RX_CTL__ENET_QOS_RGMII_RX_CTL 0x53e + MX93_PAD_ENET1_TD0__ENET_QOS_RGMII_TD0 0x53e + MX93_PAD_ENET1_TD1__ENET_QOS_RGMII_TD1 0x53e + MX93_PAD_ENET1_TD2__ENET_QOS_RGMII_TD2 0x53e + MX93_PAD_ENET1_TD3__ENET_QOS_RGMII_TD3 0x53e + MX93_PAD_ENET1_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK 0x53e + MX93_PAD_ENET1_TX_CTL__ENET_QOS_RGMII_TX_CTL 0x53e + >; + }; + + pinctrl_fec: fecgrp { + fsl,pins =3D < + MX93_PAD_ENET2_MDC__ENET1_MDC 0x57e + MX93_PAD_ENET2_MDIO__ENET1_MDIO 0x57e + MX93_PAD_ENET2_RD0__ENET1_RGMII_RD0 0x57e + MX93_PAD_ENET2_RD1__ENET1_RGMII_RD1 0x57e + MX93_PAD_ENET2_RD2__ENET1_RGMII_RD2 0x57e + MX93_PAD_ENET2_RD3__ENET1_RGMII_RD3 0x57e + MX93_PAD_ENET2_RXC__ENET1_RGMII_RXC 0x5fe + MX93_PAD_ENET2_RX_CTL__ENET1_RGMII_RX_CTL 0x57e + MX93_PAD_ENET2_TD0__ENET1_RGMII_TD0 0x57e + MX93_PAD_ENET2_TD1__ENET1_RGMII_TD1 0x57e + MX93_PAD_ENET2_TD2__ENET1_RGMII_TD2 0x57e + MX93_PAD_ENET2_TD3__ENET1_RGMII_TD3 0x57e + MX93_PAD_ENET2_TXC__ENET1_RGMII_TXC 0x5fe + MX93_PAD_ENET2_TX_CTL__ENET1_RGMII_TX_CTL 0x57e + >; + }; + + pinctrl_lpi2c2: lpi2c2grp { + fsl,pins =3D < + MX93_PAD_I2C2_SCL__LPI2C2_SCL 0x40000b9e + MX93_PAD_I2C2_SDA__LPI2C2_SDA 0x40000b9e + >; + }; + + pinctrl_usdhc1: usdhc1grp { + fsl,pins =3D < + MX93_PAD_SD1_CLK__USDHC1_CLK 0x15fe + MX93_PAD_SD1_CMD__USDHC1_CMD 0x13fe + MX93_PAD_SD1_DATA0__USDHC1_DATA0 0x13fe + MX93_PAD_SD1_DATA1__USDHC1_DATA1 0x13fe + MX93_PAD_SD1_DATA2__USDHC1_DATA2 0x13fe + MX93_PAD_SD1_DATA3__USDHC1_DATA3 0x13fe + MX93_PAD_SD1_DATA4__USDHC1_DATA4 0x13fe + MX93_PAD_SD1_DATA5__USDHC1_DATA5 0x13fe + MX93_PAD_SD1_DATA6__USDHC1_DATA6 0x13fe + MX93_PAD_SD1_DATA7__USDHC1_DATA7 0x13fe + MX93_PAD_SD1_STROBE__USDHC1_STROBE 0x15fe + >; + }; + + pinctrl_usdhc2: usdhc2grp { + fsl,pins =3D < + MX93_PAD_SD2_CLK__USDHC2_CLK 0x170e + MX93_PAD_SD2_CMD__USDHC2_CMD 0x130e + MX93_PAD_SD2_DATA0__USDHC2_DATA0 0x130e + MX93_PAD_SD2_DATA1__USDHC2_DATA1 0x130e + MX93_PAD_SD2_DATA2__USDHC2_DATA2 0x130e + MX93_PAD_SD2_DATA3__USDHC2_DATA3 0x130e + MX93_PAD_SD2_VSELECT__USDHC2_VSELECT 0x51e + >; + }; + + pinctrl_usdhc2_gpio: usdhc2gpiogrp { + fsl,pins =3D < + MX93_PAD_SD2_CD_B__GPIO3_IO00 0x31e + >; + }; +}; --=20 2.34.1 From nobody Sat May 18 08:35:52 2024 Received: from smtpdh20-1.aruba.it (smtpdh20-1.aruba.it [62.149.155.164]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B37C61607B3 for ; Thu, 18 Apr 2024 13:42:36 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=62.149.155.164 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1713447760; cv=none; b=R2fDeCp7lv4ry8BzpEn/DacXoR9n7lePj/qCHZiin+ZiwgrLM0bMz59XxBq2WpouQTTw3/wWtezJxO2ecO6EiXWkHPTOrjZV/6TIqW5EpxjjEl5uOhksUYZpdwfbYu5VQsfco1gIk75L0HeVrK0Hl5Xdeur6tfl9iFP2SD5S8gw= ARC-Message-Signature: i=1; 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Thu, 18 Apr 2024 15:39:27 +0200 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=aruba.it; s=a1; t=1713447567; bh=w83wzKUePQaYVH74jZx8tFI1GQdOIFTgbhaHxFeorBM=; h=From:To:Subject:Date:MIME-Version; b=ZTjvDdWFrIy5yldR0d3KWptedrH9M11EGWFNbdn76V+6Jf7cbd1mfWeM4z5E9Del5 EvVn+85GIsfKNfJXBYrKvZ4CouA/w8XMFHN0J6QoaTv0I8ji1P7JF2NIMmFHH5sA3n p63Z6A7FzzUNwAC2suCxQSOFzKBXJkJcnobkuGvWta6qz3BkkBnBU+nFDpHUNVueB6 SMP8pzKUmViaPGcec+PRI4R0boAlACgWzQIV3IASW4h7tJh/ssmgRTDckBpq+mB9Rd 8uiSMM0Ce0q3Xv12/fJmq11S8tpLFEA4+AGkU8jR1jjZReO9RngRv6w8Y1+E/a5QIQ MhRouppNeSqUw== From: Fabio Aiuto To: Shawn Guo , Sascha Hauer , Krzysztof Kozlowski , Rob Herring , Conor Dooley Cc: devicetree@vger.kernel.org, imx@lists.linux.dev, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Fabio Aiuto , Matteo Lisi , Mirko Ardinghi Subject: [PATCH v2 3/3] arm64: dts: imx93: Add Engicam i.Core MX93 EDIMM 2.0 Starter Kit Date: Thu, 18 Apr 2024 15:39:23 +0200 Message-Id: <20240418133923.3705-4-fabio.aiuto@engicam.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240418133923.3705-1-fabio.aiuto@engicam.com> References: <20240418133923.3705-1-fabio.aiuto@engicam.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CMAE-Envelope: MS4xfH0Xu1I2PZhjsA3o4vjTvidBnaRm6j9UVTMgWSASu9RageXyPbhV0dn4aleZWyd/cR5jbpry8cyo2KnOMzSbOtzCHAZJQtNwuceAjFlVc9kwIKPfitUF u27oTAwnz2ggk+Ng1v7r8OVJ55XmzydewgJPZVzS1Pi4wSnKchYh8olYFydFI+R1iPpMh85e1GSDoXLfxAbBlEotcaZjGacXua+lGGIZD6nd7CtP4kNIJiIM O9fL03X8nycWSa5AL6x2G1drH93R9UFOuXAIVs0HmUdMzSbYK0mL6H+piO0PC7vW1f0HDxyHBdLjb/Ta41lBtVa3Vv3ccXKOxW2F2Ks6RT7OLrCrT0CF20eB xTYB0nUrEvad5O8i261CFxVCmS8QcVaVfhhfxiEfVpDNLX+VuobjZttm1hLlexzs7Y15aGjZ2Fm6Bs320P9c6Inah4I5e6hWyFyHNq3Mto3B+BDnmii6gPcT 7nmBo64P0WeYnxPfElDb89KthTFtFjZEcVovLQBP2rjtqPNITsKgQTqakKK2hM//sRCdlHt88oRYOmKE+dSJ72RKATfWudkgcRKbYG7M0KtDS9WddGK0fm2s I0JBpj4qng7F89pieCvP9vKS Content-Type: text/plain; charset="utf-8" i.Core MX93 is a NXP i.MX93 based SoM by Enigcam which needs to be mounted on top of Engicam baseboards. Add support for EDIMM 2.0 Starter Kit hosting i.Core MX93. Starter Kit main features: 2x LVDS interfaces HDMI output Audio out Mic in Micro SD card slot USB 3.0 A port 3x USB 2.0 A port Gb Ethernet 2x CAN bus, 3x UART interfaces SIM card slot M.2 KEY_B slot Cc: Matteo Lisi Cc: Mirko Ardinghi Signed-off-by: Fabio Aiuto --- arch/arm64/boot/dts/freescale/Makefile | 1 + .../dts/freescale/imx93-icore-mx93-edimm2.dts | 354 ++++++++++++++++++ 2 files changed, 355 insertions(+) create mode 100644 arch/arm64/boot/dts/freescale/imx93-icore-mx93-edimm2.d= ts diff --git a/arch/arm64/boot/dts/freescale/Makefile b/arch/arm64/boot/dts/f= reescale/Makefile index 045250d0a040..d26c0a458a44 100644 --- a/arch/arm64/boot/dts/freescale/Makefile +++ b/arch/arm64/boot/dts/freescale/Makefile @@ -226,6 +226,7 @@ dtb-$(CONFIG_ARCH_MXC) +=3D imx8qxp-mek.dtb dtb-$(CONFIG_ARCH_MXC) +=3D imx8qxp-tqma8xqp-mba8xx.dtb dtb-$(CONFIG_ARCH_MXC) +=3D imx8ulp-evk.dtb dtb-$(CONFIG_ARCH_MXC) +=3D imx93-11x11-evk.dtb +dtb-$(CONFIG_ARCH_MXC) +=3D imx93-icore-mx93-edimm2.dtb dtb-$(CONFIG_ARCH_MXC) +=3D imx93-phyboard-segin.dtb dtb-$(CONFIG_ARCH_MXC) +=3D imx93-tqma9352-mba93xxca.dtb dtb-$(CONFIG_ARCH_MXC) +=3D imx93-tqma9352-mba93xxla.dtb diff --git a/arch/arm64/boot/dts/freescale/imx93-icore-mx93-edimm2.dts b/ar= ch/arm64/boot/dts/freescale/imx93-icore-mx93-edimm2.dts new file mode 100644 index 000000000000..8d57374eebdf --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx93-icore-mx93-edimm2.dts @@ -0,0 +1,354 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2022 NXP + * Copyright 2024 Engicam s.r.l. + */ + +/dts-v1/; + +#include "imx93-icore-mx93.dtsi" + +/ { + model =3D "Engicam i.Core MX93 - EDIMM 2 Starterkit"; + compatible =3D "engicam,icore-mx93-edimm2", "engicam,icore-mx93", + "fsl,imx93"; + + aliases { + rtc1 =3D &bbnsm_rtc; + }; + + bt_reg_on: regulator-btregon { + compatible =3D "regulator-gpio"; + regulator-name =3D "BT_REG_ON"; + pinctrl-names =3D "default"; + regulator-min-microvolt =3D <100000>; + regulator-max-microvolt =3D <3300000>; + states =3D <3300000 0x1>, <100000 0x0>; + gpios =3D <&gpio2 19 GPIO_ACTIVE_HIGH>; + regulator-always-on; + }; + + chosen { + stdout-path =3D &lpuart1; + }; + + reg_1v8_sgtl: regulator-1v8-sgtl { + compatible =3D "regulator-fixed"; + regulator-name =3D "1v8_sgtl"; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + always-on; + }; + + reg_3v3_avdd_sgtl: regulator-3v3-avdd-sgtl { + compatible =3D "regulator-fixed"; + regulator-name =3D "3v3_avdd_sgtl"; + regulator-min-microvolt =3D <3300000>; + regulator-max-microvolt =3D <3300000>; + always-on; + }; + + reg_3v3_sgtl: regulator-3v3-sgtl { + compatible =3D "regulator-fixed"; + regulator-name =3D "3v3_sgtl"; + regulator-min-microvolt =3D <3300000>; + regulator-max-microvolt =3D <3300000>; + always-on; + }; + + reserved-memory { + #address-cells =3D <2>; + #size-cells =3D <2>; + ranges; + + linux,cma { + compatible =3D "shared-dma-pool"; + reusable; + alloc-ranges =3D <0 0x80000000 0 0x40000000>; + size =3D <0 0x10000000>; + linux,cma-default; + }; + + rsc_table: rsc-table@2021f000 { + reg =3D <0 0x2021f000 0 0x1000>; + no-map; + }; + + vdevbuffer: vdevbuffer@a4020000 { + compatible =3D "shared-dma-pool"; + reg =3D <0 0xa4020000 0 0x100000>; + no-map; + }; + + vdev0vring0: vdev0vring0@a4000000 { + reg =3D <0 0xa4000000 0 0x8000>; + no-map; + }; + + vdev0vring1: vdev0vring1@a4008000 { + reg =3D <0 0xa4008000 0 0x8000>; + no-map; + }; + + vdev1vring0: vdev1vring0@a4000000 { + reg =3D <0 0xa4010000 0 0x8000>; + no-map; + }; + + vdev1vring1: vdev1vring1@a4018000 { + reg =3D <0 0xa4018000 0 0x8000>; + no-map; + }; + }; + + sound { + compatible =3D "simple-audio-card"; + simple-audio-card,name =3D "imx93-sgtl5000"; + simple-audio-card,format =3D "i2s"; + simple-audio-card,bitclock-master =3D <&dailink_master>; + simple-audio-card,frame-master =3D <&dailink_master>; + /*simple-audio-card,mclk-fs =3D <1>;*/ + simple-audio-card,cpu { + sound-dai =3D <&sai3>; + }; + + dailink_master: simple-audio-card,codec { + sound-dai =3D <&sgtl5000>; + clocks =3D <&clk IMX93_CLK_SAI3_IPG>; + }; + }; + + usdhc3_pwrseq: usdhc3-pwrseq { + compatible =3D "mmc-pwrseq-simple"; + }; + + wl_reg_on: regulator-wlregon { + compatible =3D "regulator-gpio"; + pinctrl-names =3D "default"; + regulator-name =3D "WL_REG_ON"; + regulator-min-microvolt =3D <100000>; + regulator-max-microvolt =3D <3300000>; + states =3D <3300000 0x1>, + <100000 0x0>; + gpios =3D <&gpio2 22 GPIO_ACTIVE_HIGH>; + enable-active-high; + vin-supply =3D <&bt_reg_on>; + }; +}; + +&cm33 { + mbox-names =3D "tx", "rx", "rxdb"; + mboxes =3D <&mu1 0 1>, + <&mu1 1 1>, + <&mu1 3 1>; + memory-region =3D <&vdevbuffer>, <&vdev0vring0>, <&vdev0vring1>, + <&vdev1vring0>, <&vdev1vring1>, <&rsc_table>; + status =3D "okay"; +}; + +&flexcan1 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_flexcan1>; + fsl,stop-mode =3D <&aonmix_ns_gpr 0x10 4>; + status =3D "okay"; +}; + +&flexcan2 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_flexcan2>; + fsl,stop-mode =3D <&aonmix_ns_gpr 0x10 4>; + status =3D "okay"; +}; + +&lpi2c1 { + #address-cells =3D <1>; + #size-cells =3D <0>; + clock-frequency =3D <400000>; + pinctrl-names =3D "default", "sleep"; + pinctrl-0 =3D <&pinctrl_lpi2c1>; + pinctrl-1 =3D <&pinctrl_lpi2c1>; + status =3D "okay"; + + pcf8523: rtc@68 { + compatible =3D "nxp,pcf8523"; + reg =3D <0x68>; + }; + + sgtl5000: codec@a { + compatible =3D "fsl,sgtl5000"; + status =3D "okay"; + #sound-dai-cells =3D <0>; + reg =3D <0x0a>; + clocks =3D <&clk IMX93_CLK_SAI3_GATE>; + clock-names =3D "mclk"; + assigned-clock-rates =3D <12000000>, <12000000>; + VDDA-supply =3D <®_3v3_avdd_sgtl>; + VDDIO-supply =3D <®_3v3_sgtl>; + VDDD-supply =3D <®_1v8_sgtl>; + }; +}; + +&lpuart1 { /* console */ + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_uart1>; + status =3D "okay"; +}; + +&lpuart5 { /* RS485 */ + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_uart5>; + status =3D "okay"; +}; + +&lpuart8 { /* RS232 */ + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_uart8>; + status =3D "okay"; +}; + +&micfil { + #sound-dai-cells =3D <0>; + pinctrl-names =3D "default"; + assigned-clocks =3D <&clk IMX93_CLK_PDM>; + assigned-clock-parents =3D <&clk IMX93_CLK_AUDIO_PLL>; + assigned-clock-rates =3D <196608000>; + status =3D "okay"; +}; + +&mu1 { + status =3D "okay"; +}; + +&mu2 { + status =3D "okay"; +}; + +&sai1 { + #sound-dai-cells =3D <0>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_sai1>; + assigned-clocks =3D <&clk IMX93_CLK_SAI1>; + assigned-clock-parents =3D <&clk IMX93_CLK_AUDIO_PLL>; + assigned-clock-rates =3D <12288000>; + status =3D "okay"; +}; + +&sai3 { + pinctrl-names =3D "default"; + #sound-dai-cells =3D <0>; + pinctrl-0 =3D <&pinctrl_sai3>; + assigned-clocks =3D <&clk IMX93_CLK_SAI3>; + assigned-clock-parents =3D <&clk IMX93_CLK_AUDIO_PLL>; + assigned-clock-rates =3D <24576000>; + fsl,sai-mclk-direction-output; + status =3D "okay"; +}; + +&usdhc3 { /* WiFi */ + pinctrl-names =3D "default", "state_100mhz", "state_200mhz"; + pinctrl-0 =3D <&pinctrl_usdhc3>, <&pinctrl_laird>; + pinctrl-1 =3D <&pinctrl_usdhc3>, <&pinctrl_laird>; + pinctrl-2 =3D <&pinctrl_usdhc3>, <&pinctrl_laird>; + vmmc-supply =3D <&wl_reg_on>; + bus-width =3D <4>; + no-1-8-v; + non-removable; + max-frequency =3D <25000000>; + status =3D "okay"; + + #address-cells =3D <1>; + #size-cells =3D <0>; + + brcmf: bcrmf@1 { + reg =3D <1>; + compatible =3D "brcm,bcm4329-fmac"; + }; +}; + +&wdog3 { + status =3D "okay"; +}; + +&iomuxc { + + pinctrl_flexcan1: flexcan1grp { + fsl,pins =3D < + MX93_PAD_PDM_CLK__CAN1_TX 0x139e + MX93_PAD_PDM_BIT_STREAM0__CAN1_RX 0x139e + >; + }; + + pinctrl_flexcan2: flexcan2grp { + fsl,pins =3D < + MX93_PAD_GPIO_IO25__CAN2_TX 0x139e + MX93_PAD_GPIO_IO27__CAN2_RX 0x139e + >; + }; + + pinctrl_laird: lairdgrp { + fsl,pins =3D < + MX93_PAD_GPIO_IO22__GPIO2_IO22 0x31e // WL_REG_ON + MX93_PAD_GPIO_IO19__GPIO2_IO19 0x31e // BT_REG_ON + >; + }; + + pinctrl_lpi2c1: lpi2c1grp { + fsl,pins =3D < + MX93_PAD_I2C1_SCL__LPI2C1_SCL 0x40000b9e + MX93_PAD_I2C1_SDA__LPI2C1_SDA 0x40000b9e + >; + }; + + pinctrl_sai1: sai1grp { + fsl,pins =3D < + MX93_PAD_SAI1_TXC__SAI1_TX_BCLK 0x31e + MX93_PAD_SAI1_TXFS__SAI1_TX_SYNC 0x31e + MX93_PAD_SAI1_TXD0__SAI1_TX_DATA00 0x31e + MX93_PAD_SAI1_RXD0__SAI1_RX_DATA00 0x31e + >; + }; + + pinctrl_sai3: sai3grp { + fsl,pins =3D < + MX93_PAD_GPIO_IO26__SAI3_TX_SYNC 0x31e + MX93_PAD_GPIO_IO16__SAI3_TX_BCLK 0x31e + MX93_PAD_GPIO_IO17__SAI3_MCLK 0x31e + MX93_PAD_GPIO_IO21__SAI3_TX_DATA00 0x31e + MX93_PAD_GPIO_IO20__SAI3_RX_DATA00 0x31e + >; + }; + + pinctrl_uart1: uart1grp { + fsl,pins =3D < + MX93_PAD_UART1_RXD__LPUART1_RX 0x31e + MX93_PAD_UART1_TXD__LPUART1_TX 0x31e + >; + }; + + pinctrl_uart5: uart5grp { + fsl,pins =3D < + MX93_PAD_GPIO_IO01__LPUART5_RX 0x31e + MX93_PAD_GPIO_IO00__LPUART5_TX 0x31e + MX93_PAD_GPIO_IO02__LPUART5_CTS_B 0x31e + MX93_PAD_GPIO_IO03__LPUART5_RTS_B 0x31e + >; + }; + + pinctrl_uart8: uart8grp { + fsl,pins =3D < + MX93_PAD_GPIO_IO13__LPUART8_RX 0x31e + MX93_PAD_GPIO_IO12__LPUART8_TX 0x31e + >; + }; + + pinctrl_usdhc3: usdhc3grp { + fsl,pins =3D < + MX93_PAD_SD3_CLK__USDHC3_CLK 0x17fe + MX93_PAD_SD3_CMD__USDHC3_CMD 0x13fe + MX93_PAD_SD3_DATA0__USDHC3_DATA0 0x13fe + MX93_PAD_SD3_DATA1__USDHC3_DATA1 0x13fe + MX93_PAD_SD3_DATA2__USDHC3_DATA2 0x13fe + MX93_PAD_SD3_DATA3__USDHC3_DATA3 0x13fe + >; + }; +}; --=20 2.34.1