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Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , linux-kernel@vger.kernel.org Subject: [PATCH net-next v2 1/5] net: dsa: vsc73xx: use read_poll_timeout instead delay loop Date: Wed, 17 Apr 2024 22:50:44 +0200 Message-Id: <20240417205048.3542839-2-paweldembicki@gmail.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240417205048.3542839-1-paweldembicki@gmail.com> References: <20240417205048.3542839-1-paweldembicki@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Switch the delay loop during the Arbiter empty check from vsc73xx_adjust_link() to use read_poll_timeout(). Functionally, one msleep() call is eliminated at the end of the loop in the timeout case. As Russell King suggested: "This [change] avoids the issue that on the last iteration, the code reads the register, tests it, finds the condition that's being waiting for is false, _then_ waits and end up printing the error message - that last wait is rather useless, and as the arbiter state isn't checked after waiting, it could be that we had success during the last wait." Suggested-by: Russell King Reviewed-by: Andrew Lunn Reviewed-by: Linus Walleij Reviewed-by: Florian Fainelli Signed-off-by: Pawel Dembicki --- v2: - resend only drivers/net/dsa/vitesse-vsc73xx-core.c | 30 ++++++++++++++------------ 1 file changed, 16 insertions(+), 14 deletions(-) diff --git a/drivers/net/dsa/vitesse-vsc73xx-core.c b/drivers/net/dsa/vites= se-vsc73xx-core.c index ae70eac3be28..ab5771d4d828 100644 --- a/drivers/net/dsa/vitesse-vsc73xx-core.c +++ b/drivers/net/dsa/vitesse-vsc73xx-core.c @@ -17,6 +17,7 @@ #include #include #include +#include #include #include #include @@ -268,6 +269,9 @@ #define IS_7398(a) ((a)->chipid =3D=3D VSC73XX_CHIPID_ID_7398) #define IS_739X(a) (IS_7395(a) || IS_7398(a)) =20 +#define VSC73XX_POLL_SLEEP_US 1000 +#define VSC73XX_POLL_TIMEOUT_US 10000 + struct vsc73xx_counter { u8 counter; const char *name; @@ -779,7 +783,7 @@ static void vsc73xx_adjust_link(struct dsa_switch *ds, = int port, * after a PHY or the CPU port comes up or down. */ if (!phydev->link) { - int maxloop =3D 10; + int ret, err; =20 dev_dbg(vsc->dev, "port %d: went down\n", port); @@ -794,19 +798,17 @@ static void vsc73xx_adjust_link(struct dsa_switch *ds= , int port, VSC73XX_ARBDISC, BIT(port), BIT(port)); =20 /* Wait until queue is empty */ - vsc73xx_read(vsc, VSC73XX_BLOCK_ARBITER, 0, - VSC73XX_ARBEMPTY, &val); - while (!(val & BIT(port))) { - msleep(1); - vsc73xx_read(vsc, VSC73XX_BLOCK_ARBITER, 0, - VSC73XX_ARBEMPTY, &val); - if (--maxloop =3D=3D 0) { - dev_err(vsc->dev, - "timeout waiting for block arbiter\n"); - /* Continue anyway */ - break; - } - } + ret =3D read_poll_timeout(vsc73xx_read, err, + err < 0 || (val & BIT(port)), + VSC73XX_POLL_SLEEP_US, + VSC73XX_POLL_TIMEOUT_US, false, + vsc, VSC73XX_BLOCK_ARBITER, 0, + VSC73XX_ARBEMPTY, &val); + if (ret) + dev_err(vsc->dev, + "timeout waiting for block arbiter\n"); + else if (err < 0) + dev_err(vsc->dev, "error reading arbiter\n"); =20 /* Put this port into reset */ vsc73xx_write(vsc, VSC73XX_BLOCK_MAC, port, VSC73XX_MAC_CFG, --=20 2.34.1 From nobody Tue May 21 22:07:45 2024 Received: from mail-ej1-f52.google.com (mail-ej1-f52.google.com [209.85.218.52]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 93B4C482C2; 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Wed, 17 Apr 2024 13:51:40 -0700 (PDT) Received: from WBEC325.dom.lan ([185.188.71.122]) by smtp.gmail.com with ESMTPSA id tx24-20020a1709078e9800b00a554177a2cdsm31752ejc.85.2024.04.17.13.51.39 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 17 Apr 2024 13:51:40 -0700 (PDT) From: Pawel Dembicki To: netdev@vger.kernel.org Cc: Pawel Dembicki , Andrew Lunn , Florian Fainelli , Vladimir Oltean , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Russell King , linux-kernel@vger.kernel.org Subject: [PATCH net-next v2 2/5] net: dsa: vsc73xx: convert to PHYLINK Date: Wed, 17 Apr 2024 22:50:45 +0200 Message-Id: <20240417205048.3542839-3-paweldembicki@gmail.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240417205048.3542839-1-paweldembicki@gmail.com> References: <20240417205048.3542839-1-paweldembicki@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" This patch replaces the adjust_link api with the phylink apis that provide equivalent functionality. The remaining functionality from the adjust_link is now covered in the mac_link_* and mac_config from phylink_mac_ops structure. Removes: .adjust_link Adds phylink_mac_ops structure: .mac_config .mac_link_up .mac_link_down Signed-off-by: Pawel Dembicki --- v2: - use 'phylink_mac_ops' structure instead '.phylink_mac*' drivers/net/dsa/vitesse-vsc73xx-core.c | 242 ++++++++++++------------- 1 file changed, 116 insertions(+), 126 deletions(-) diff --git a/drivers/net/dsa/vitesse-vsc73xx-core.c b/drivers/net/dsa/vites= se-vsc73xx-core.c index ab5771d4d828..3f8edac9aa5c 100644 --- a/drivers/net/dsa/vitesse-vsc73xx-core.c +++ b/drivers/net/dsa/vitesse-vsc73xx-core.c @@ -717,51 +717,44 @@ static void vsc73xx_init_port(struct vsc73xx *vsc, in= t port) port, VSC73XX_C_RX0, 0); } =20 -static void vsc73xx_adjust_enable_port(struct vsc73xx *vsc, - int port, struct phy_device *phydev, - u32 initval) +static void vsc73xx_reset_port(struct vsc73xx *vsc, int port, u32 initval) { - u32 val =3D initval; - u8 seed; - - /* Reset this port FIXME: break out subroutine */ - val |=3D VSC73XX_MAC_CFG_RESET; - vsc73xx_write(vsc, VSC73XX_BLOCK_MAC, port, VSC73XX_MAC_CFG, val); - - /* Seed the port randomness with randomness */ - get_random_bytes(&seed, 1); - val |=3D seed << VSC73XX_MAC_CFG_SEED_OFFSET; - val |=3D VSC73XX_MAC_CFG_SEED_LOAD; - val |=3D VSC73XX_MAC_CFG_WEXC_DIS; - vsc73xx_write(vsc, VSC73XX_BLOCK_MAC, port, VSC73XX_MAC_CFG, val); + int ret, err; + u32 val; =20 - /* Flow control for the PHY facing ports: - * Use a zero delay pause frame when pause condition is left - * Obey pause control frames - * When generating pause frames, use 0xff as pause value - */ - vsc73xx_write(vsc, VSC73XX_BLOCK_MAC, port, VSC73XX_FCCONF, - VSC73XX_FCCONF_ZERO_PAUSE_EN | - VSC73XX_FCCONF_FLOW_CTRL_OBEY | - 0xff); + /* Disable RX on this port */ + vsc73xx_update_bits(vsc, VSC73XX_BLOCK_MAC, port, + VSC73XX_MAC_CFG, + VSC73XX_MAC_CFG_RX_EN, 0); =20 - /* Disallow backward dropping of frames from this port */ + /* Discard packets */ vsc73xx_update_bits(vsc, VSC73XX_BLOCK_ARBITER, 0, - VSC73XX_SBACKWDROP, BIT(port), 0); + VSC73XX_ARBDISC, BIT(port), BIT(port)); + + /* Wait until queue is empty */ + ret =3D read_poll_timeout(vsc73xx_read, err, + err < 0 || (val & BIT(port)), + VSC73XX_POLL_SLEEP_US, + VSC73XX_POLL_TIMEOUT_US, false, + vsc, VSC73XX_BLOCK_ARBITER, 0, + VSC73XX_ARBEMPTY, &val); + if (ret) + dev_err(vsc->dev, + "timeout waiting for block arbiter\n"); + else if (err < 0) + dev_err(vsc->dev, "error reading arbiter\n"); =20 - /* Enable TX, RX, deassert reset, stop loading seed */ - vsc73xx_update_bits(vsc, VSC73XX_BLOCK_MAC, port, - VSC73XX_MAC_CFG, - VSC73XX_MAC_CFG_RESET | VSC73XX_MAC_CFG_SEED_LOAD | - VSC73XX_MAC_CFG_TX_EN | VSC73XX_MAC_CFG_RX_EN, - VSC73XX_MAC_CFG_TX_EN | VSC73XX_MAC_CFG_RX_EN); + /* Put this port into reset */ + vsc73xx_write(vsc, VSC73XX_BLOCK_MAC, port, VSC73XX_MAC_CFG, + VSC73XX_MAC_CFG_RESET | initval); } =20 -static void vsc73xx_adjust_link(struct dsa_switch *ds, int port, - struct phy_device *phydev) +static void vsc73xx_mac_config(struct phylink_config *config, unsigned int= mode, + const struct phylink_link_state *state) { - struct vsc73xx *vsc =3D ds->priv; - u32 val; + struct dsa_port *dp =3D dsa_phylink_to_port(config); + struct vsc73xx *vsc =3D dp->ds->priv; + int port =3D dp->index; =20 /* Special handling of the CPU-facing port */ if (port =3D=3D CPU_PORT) { @@ -778,102 +771,93 @@ static void vsc73xx_adjust_link(struct dsa_switch *d= s, int port, VSC73XX_ADVPORTM_ENA_GTX | VSC73XX_ADVPORTM_DDR_MODE); } +} + +static void vsc73xx_mac_link_down(struct phylink_config *config, + unsigned int mode, phy_interface_t interface) +{ + struct dsa_port *dp =3D dsa_phylink_to_port(config); + struct vsc73xx *vsc =3D dp->ds->priv; + int port =3D dp->index; =20 - /* This is the MAC confiuration that always need to happen - * after a PHY or the CPU port comes up or down. + /* This routine is described in the datasheet (below ARBDISC register + * description) */ - if (!phydev->link) { - int ret, err; - - dev_dbg(vsc->dev, "port %d: went down\n", - port); - - /* Disable RX on this port */ - vsc73xx_update_bits(vsc, VSC73XX_BLOCK_MAC, port, - VSC73XX_MAC_CFG, - VSC73XX_MAC_CFG_RX_EN, 0); - - /* Discard packets */ - vsc73xx_update_bits(vsc, VSC73XX_BLOCK_ARBITER, 0, - VSC73XX_ARBDISC, BIT(port), BIT(port)); - - /* Wait until queue is empty */ - ret =3D read_poll_timeout(vsc73xx_read, err, - err < 0 || (val & BIT(port)), - VSC73XX_POLL_SLEEP_US, - VSC73XX_POLL_TIMEOUT_US, false, - vsc, VSC73XX_BLOCK_ARBITER, 0, - VSC73XX_ARBEMPTY, &val); - if (ret) - dev_err(vsc->dev, - "timeout waiting for block arbiter\n"); - else if (err < 0) - dev_err(vsc->dev, "error reading arbiter\n"); - - /* Put this port into reset */ - vsc73xx_write(vsc, VSC73XX_BLOCK_MAC, port, VSC73XX_MAC_CFG, - VSC73XX_MAC_CFG_RESET); - - /* Accept packets again */ - vsc73xx_update_bits(vsc, VSC73XX_BLOCK_ARBITER, 0, - VSC73XX_ARBDISC, BIT(port), 0); - - /* Allow backward dropping of frames from this port */ - vsc73xx_update_bits(vsc, VSC73XX_BLOCK_ARBITER, 0, - VSC73XX_SBACKWDROP, BIT(port), BIT(port)); - - /* Receive mask (disable forwarding) */ - vsc73xx_update_bits(vsc, VSC73XX_BLOCK_ANALYZER, 0, - VSC73XX_RECVMASK, BIT(port), 0); + vsc73xx_reset_port(vsc, port, 0); =20 - return; - } + /* Allow backward dropping of frames from this port */ + vsc73xx_update_bits(vsc, VSC73XX_BLOCK_ARBITER, 0, + VSC73XX_SBACKWDROP, BIT(port), BIT(port)); =20 - /* Figure out what speed was negotiated */ - if (phydev->speed =3D=3D SPEED_1000) { - dev_dbg(vsc->dev, "port %d: 1000 Mbit mode full duplex\n", - port); - - /* Set up default for internal port or external RGMII */ - if (phydev->interface =3D=3D PHY_INTERFACE_MODE_RGMII) - val =3D VSC73XX_MAC_CFG_1000M_F_RGMII; - else - val =3D VSC73XX_MAC_CFG_1000M_F_PHY; - vsc73xx_adjust_enable_port(vsc, port, phydev, val); - } else if (phydev->speed =3D=3D SPEED_100) { - if (phydev->duplex =3D=3D DUPLEX_FULL) { - val =3D VSC73XX_MAC_CFG_100_10M_F_PHY; - dev_dbg(vsc->dev, - "port %d: 100 Mbit full duplex mode\n", - port); - } else { - val =3D VSC73XX_MAC_CFG_100_10M_H_PHY; - dev_dbg(vsc->dev, - "port %d: 100 Mbit half duplex mode\n", - port); - } - vsc73xx_adjust_enable_port(vsc, port, phydev, val); - } else if (phydev->speed =3D=3D SPEED_10) { - if (phydev->duplex =3D=3D DUPLEX_FULL) { - val =3D VSC73XX_MAC_CFG_100_10M_F_PHY; - dev_dbg(vsc->dev, - "port %d: 10 Mbit full duplex mode\n", - port); - } else { - val =3D VSC73XX_MAC_CFG_100_10M_H_PHY; - dev_dbg(vsc->dev, - "port %d: 10 Mbit half duplex mode\n", - port); - } - vsc73xx_adjust_enable_port(vsc, port, phydev, val); - } else { - dev_err(vsc->dev, - "could not adjust link: unknown speed\n"); - } + /* Receive mask (disable forwarding) */ + vsc73xx_update_bits(vsc, VSC73XX_BLOCK_ANALYZER, 0, + VSC73XX_RECVMASK, BIT(port), 0); +} + +static void vsc73xx_mac_link_up(struct phylink_config *config, + struct phy_device *phy, unsigned int mode, + phy_interface_t interface, int speed, + int duplex, bool tx_pause, bool rx_pause) +{ + struct dsa_port *dp =3D dsa_phylink_to_port(config); + struct vsc73xx *vsc =3D dp->ds->priv; + int port =3D dp->index; + u32 val; + u8 seed; + + if (speed =3D=3D SPEED_1000) + val =3D VSC73XX_MAC_CFG_GIGA_MODE | VSC73XX_MAC_CFG_TX_IPG_1000M; + else + val =3D VSC73XX_MAC_CFG_TX_IPG_100_10M; + + if (interface =3D=3D PHY_INTERFACE_MODE_RGMII) + val |=3D VSC73XX_MAC_CFG_CLK_SEL_1000M; + else + val |=3D VSC73XX_MAC_CFG_CLK_SEL_EXT; + + if (duplex =3D=3D DUPLEX_FULL) + val |=3D VSC73XX_MAC_CFG_FDX; + + /* This routine is described in the datasheet (below ARBDISC register + * description) + */ + vsc73xx_reset_port(vsc, port, val); + + /* Seed the port randomness with randomness */ + get_random_bytes(&seed, 1); + val |=3D seed << VSC73XX_MAC_CFG_SEED_OFFSET; + val |=3D VSC73XX_MAC_CFG_SEED_LOAD; + val |=3D VSC73XX_MAC_CFG_WEXC_DIS; + vsc73xx_write(vsc, VSC73XX_BLOCK_MAC, port, VSC73XX_MAC_CFG, val); + + /* Flow control for the PHY facing ports: + * Use a zero delay pause frame when pause condition is left + * Obey pause control frames + * When generating pause frames, use 0xff as pause value + */ + vsc73xx_write(vsc, VSC73XX_BLOCK_MAC, port, VSC73XX_FCCONF, + VSC73XX_FCCONF_ZERO_PAUSE_EN | + VSC73XX_FCCONF_FLOW_CTRL_OBEY | + 0xff); + + /* Accept packets again */ + vsc73xx_update_bits(vsc, VSC73XX_BLOCK_ARBITER, 0, + VSC73XX_ARBDISC, BIT(port), 0); =20 /* Enable port (forwarding) in the receieve mask */ vsc73xx_update_bits(vsc, VSC73XX_BLOCK_ANALYZER, 0, VSC73XX_RECVMASK, BIT(port), BIT(port)); + + /* Disallow backward dropping of frames from this port */ + vsc73xx_update_bits(vsc, VSC73XX_BLOCK_ARBITER, 0, + VSC73XX_SBACKWDROP, BIT(port), 0); + + /* Enable TX, RX, deassert reset, stop loading seed */ + vsc73xx_update_bits(vsc, VSC73XX_BLOCK_MAC, port, + VSC73XX_MAC_CFG, + VSC73XX_MAC_CFG_RESET | VSC73XX_MAC_CFG_SEED_LOAD | + VSC73XX_MAC_CFG_TX_EN | VSC73XX_MAC_CFG_RX_EN, + VSC73XX_MAC_CFG_TX_EN | VSC73XX_MAC_CFG_RX_EN); } =20 static int vsc73xx_port_enable(struct dsa_switch *ds, int port, @@ -1055,12 +1039,17 @@ static void vsc73xx_phylink_get_caps(struct dsa_swi= tch *dsa, int port, config->mac_capabilities =3D MAC_SYM_PAUSE | MAC_10 | MAC_100 | MAC_1000; } =20 +static const struct phylink_mac_ops vsc73xx_phylink_mac_ops =3D { + .mac_config =3D vsc73xx_mac_config, + .mac_link_down =3D vsc73xx_mac_link_down, + .mac_link_up =3D vsc73xx_mac_link_up, +}; + static const struct dsa_switch_ops vsc73xx_ds_ops =3D { .get_tag_protocol =3D vsc73xx_get_tag_protocol, .setup =3D vsc73xx_setup, .phy_read =3D vsc73xx_phy_read, .phy_write =3D vsc73xx_phy_write, - .adjust_link =3D vsc73xx_adjust_link, .get_strings =3D vsc73xx_get_strings, .get_ethtool_stats =3D vsc73xx_get_ethtool_stats, .get_sset_count =3D vsc73xx_get_sset_count, @@ -1217,6 +1206,7 @@ int vsc73xx_probe(struct vsc73xx *vsc) vsc->ds->priv =3D vsc; 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Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Russell King , linux-kernel@vger.kernel.org Subject: [PATCH net-next v2 3/5] net: dsa: vsc73xx: use macros for rgmii recognition Date: Wed, 17 Apr 2024 22:50:46 +0200 Message-Id: <20240417205048.3542839-4-paweldembicki@gmail.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240417205048.3542839-1-paweldembicki@gmail.com> References: <20240417205048.3542839-1-paweldembicki@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" It's preparation for future use. At this moment, the RGMII port is used only for a connection to the MAC interface, but in the future, someone could connect a PHY to it. Using the "phy_interface_mode_is_rgmii" macro allows for the proper recognition of all RGMII modes. Suggested-by: Russell King (Oracle) Signed-off-by: Pawel Dembicki Reviewed-by: Linus Walleij Reviewed-by: Florian Fainelli Reviewed-by: Vladimir Oltean Reviewed-by: Russell King (Oracle) --- v2: - resend only drivers/net/dsa/vitesse-vsc73xx-core.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/net/dsa/vitesse-vsc73xx-core.c b/drivers/net/dsa/vites= se-vsc73xx-core.c index 3f8edac9aa5c..09e80aac43e7 100644 --- a/drivers/net/dsa/vitesse-vsc73xx-core.c +++ b/drivers/net/dsa/vitesse-vsc73xx-core.c @@ -810,7 +810,7 @@ static void vsc73xx_mac_link_up(struct phylink_config *= config, else val =3D VSC73XX_MAC_CFG_TX_IPG_100_10M; =20 - if (interface =3D=3D PHY_INTERFACE_MODE_RGMII) + if (phy_interface_mode_is_rgmii(interface)) val |=3D VSC73XX_MAC_CFG_CLK_SEL_1000M; else val |=3D VSC73XX_MAC_CFG_CLK_SEL_EXT; --=20 2.34.1 From nobody Tue May 21 22:07:45 2024 Received: from mail-ej1-f50.google.com (mail-ej1-f50.google.com [209.85.218.50]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 844C54AEE1; Wed, 17 Apr 2024 20:51:46 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.218.50 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1713387108; cv=none; b=rYFyX35KnI+0yNBImP3/5+uIcK55iGGd1DA8h8qE8Al/HDbHTDdrj1cGRhP0tAlPKCxrOekfDbEUyIjxBVFyvbnQQqX1bIdH91pTuYXMhYIg5emGhoV2LNWxtIBBthCBRdUioGNslO8fFMRyUopZbZDKTG+GLwNd/zzEoA5n8JY= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1713387108; c=relaxed/simple; bh=ouVLEUZpWX2UCZN0EuGUEDMf7fMnkTJN0o5J9TEkr9Q=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=IORgzz4u8eXX+EZvrPawHakfFNrkmIkTJCiocrojJ2fjYMXXCppdD52kdHwCIoYkloeyR7TMiJK2D4rL8NU3C/vPMgZhYkjxi1hEL/2VXLFN6GPvu3D4IAhMYObKmS13bXlD5T/f7wNg+ye+yOSNrMwZpjKrnxiXOOiS8901pvI= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=MNBhq5vc; arc=none smtp.client-ip=209.85.218.50 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="MNBhq5vc" Received: by mail-ej1-f50.google.com with SMTP id a640c23a62f3a-a526d381d2fso225873766b.0; Wed, 17 Apr 2024 13:51:46 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1713387105; x=1713991905; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=d/IsHbN6lEzszWOCVj+rAi2aH3mP1bogQa/4bzTSAoU=; b=MNBhq5vc7d32+MVUgdmrPCNQZdPFcbWmfhVWrtjKmASz4Etao5ldDpT0QkkfM82wAF UbmjdBDBlp9lpTYg3PV9ZFpMTt535ASc7mGnkswOcE5NJEf24lI68bCI3NAKy7RjTy5+ r1vo9pTBEYY5f/31HqbnJCQg4faNQ9NH07YF22WnoxF3yBah2KKvt3HAl1mf+Nf0lFdf D3Lst9beqETtdZLZQgDTlsa4KIxc4JEZIVmnVA+QYygaCBtC0uckZSdLBkCOXZlUZRAF zJEBcwjUHER0vzojLUBM7YLIIxPrsy16JHHt6cNnu5wQwAN5zOCNW/7Utt0H8mVFviwL mNfA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1713387105; x=1713991905; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=d/IsHbN6lEzszWOCVj+rAi2aH3mP1bogQa/4bzTSAoU=; b=OYqoAPqI4cz1NqtvM7fjy7u8mDVFj9ImH56Ft/AR0JzIh3w1kMIAWRfjcU7iMjeMXA RXoPbuxFfgr00Uqw9T58bpnDMG8eUuNuLkotQdmww7pLzRGcfmNvNrN9KRpbbVK5DOjj en9bsZKI/XpIHX2FST/9h8VGKEV622UEzlv8JSs9vfsDsILQmGCVskWEkBGLyKeWbBMz RtMhUnyfSLGJYvlPyWO3RV1fy9QPOzlcg8P1h2anQIl4f6iP4OnW23bFAOZfA5iATyC2 rt6m+/ajsvlK1S1TR/G8bgxXZ5mhW1EgQ7WFKRtVlYXbyX/cw1qUfiP/w8tTcPsB9s4D 39aw== X-Forwarded-Encrypted: i=1; AJvYcCWUk8+0Vddsjuu60uT4NxU8Sv/IrJRz4rqETpsFTGtDLK0ZvMyV1VbXdnoN6t5v4KXCyulKn2lPmwUdsQmt8PlNh/aOQtJaL0tKAFyE X-Gm-Message-State: AOJu0YzRy+12qHV0gCzr+E4zJ2lCP21wj+3svzyOvDDXzK3UfxgNyUbt ZsDJ0G0lno5X2X27729rTk+Fht9XiuZJ9ZEppre/bXB1oaQQRf4dTJyTi7nb X-Google-Smtp-Source: AGHT+IGGQM1Y4PKRjMQP0FfL+G8Z/F1T1TCYOtknbc5RXEOw8odBVmCWxkkpQCiQmT7bu6doXsjiRw== X-Received: by 2002:a17:907:86ab:b0:a55:617a:e57f with SMTP id qa43-20020a17090786ab00b00a55617ae57fmr276091ejc.14.1713387104705; Wed, 17 Apr 2024 13:51:44 -0700 (PDT) Received: from WBEC325.dom.lan ([185.188.71.122]) by smtp.gmail.com with ESMTPSA id tx24-20020a1709078e9800b00a554177a2cdsm31752ejc.85.2024.04.17.13.51.43 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 17 Apr 2024 13:51:44 -0700 (PDT) From: Pawel Dembicki To: netdev@vger.kernel.org Cc: Pawel Dembicki , Vladimir Oltean , Linus Walleij , Florian Fainelli , Andrew Lunn , Florian Fainelli , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Russell King , linux-kernel@vger.kernel.org Subject: [PATCH net-next v2 4/5] net: dsa: vsc73xx: Add define for max num of ports Date: Wed, 17 Apr 2024 22:50:47 +0200 Message-Id: <20240417205048.3542839-5-paweldembicki@gmail.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240417205048.3542839-1-paweldembicki@gmail.com> References: <20240417205048.3542839-1-paweldembicki@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" This patch introduces a new define: VSC73XX_MAX_NUM_PORTS, which can be used in the future instead of a hardcoded value. Currently, the only hardcoded value is vsc->ds->num_ports. It is being replaced with the new define. Suggested-by: Vladimir Oltean Signed-off-by: Pawel Dembicki Reviewed-by: Vladimir Oltean Reviewed-by: Linus Walleij Reviewed-by: Florian Fainelli --- v2: - resend only drivers/net/dsa/vitesse-vsc73xx-core.c | 13 +------------ drivers/net/dsa/vitesse-vsc73xx.h | 11 +++++++++++ 2 files changed, 12 insertions(+), 12 deletions(-) diff --git a/drivers/net/dsa/vitesse-vsc73xx-core.c b/drivers/net/dsa/vites= se-vsc73xx-core.c index 09e80aac43e7..f1cd7f988561 100644 --- a/drivers/net/dsa/vitesse-vsc73xx-core.c +++ b/drivers/net/dsa/vitesse-vsc73xx-core.c @@ -1186,23 +1186,12 @@ int vsc73xx_probe(struct vsc73xx *vsc) vsc->addr[0], vsc->addr[1], vsc->addr[2], vsc->addr[3], vsc->addr[4], vsc->addr[5]); =20 - /* The VSC7395 switch chips have 5+1 ports which means 5 - * ordinary ports and a sixth CPU port facing the processor - * with an RGMII interface. These ports are numbered 0..4 - * and 6, so they leave a "hole" in the port map for port 5, - * which is invalid. - * - * The VSC7398 has 8 ports, port 7 is again the CPU port. - * - * We allocate 8 ports and avoid access to the nonexistant - * ports. - */ vsc->ds =3D devm_kzalloc(dev, sizeof(*vsc->ds), GFP_KERNEL); if (!vsc->ds) return -ENOMEM; =20 vsc->ds->dev =3D dev; - vsc->ds->num_ports =3D 8; + vsc->ds->num_ports =3D VSC73XX_MAX_NUM_PORTS; vsc->ds->priv =3D vsc; =20 vsc->ds->ops =3D &vsc73xx_ds_ops; diff --git a/drivers/net/dsa/vitesse-vsc73xx.h b/drivers/net/dsa/vitesse-vs= c73xx.h index 30b1f0a36566..fee1378508b5 100644 --- a/drivers/net/dsa/vitesse-vsc73xx.h +++ b/drivers/net/dsa/vitesse-vsc73xx.h @@ -3,6 +3,17 @@ #include #include =20 +/* The VSC7395 switch chips have 5+1 ports which means 5 ordinary ports and + * a sixth CPU port facing the processor with an RGMII interface. These po= rts + * are numbered 0..4 and 6, so they leave a "hole" in the port map for por= t 5, + * which is invalid. + * + * The VSC7398 has 8 ports, port 7 is again the CPU port. + * + * We allocate 8 ports and avoid access to the nonexistent ports. + */ +#define VSC73XX_MAX_NUM_PORTS 8 + /** * struct vsc73xx - VSC73xx state container */ --=20 2.34.1 From nobody Tue May 21 22:07:45 2024 Received: from mail-ej1-f47.google.com (mail-ej1-f47.google.com [209.85.218.47]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B375664CF2; Wed, 17 Apr 2024 20:51:48 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.218.47 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1713387110; cv=none; b=dA6d5AWtRChIBJuZObqwZIHGoEqZ7Rd1XdIsu5GBc2+FdmdUVRBmIuL6boGnzU6CLyfW1u5d1BYO7M+9Gz9navyjlHM4d8lju9l/gfk3Mp5OvsnSioVI+hHTvyjfvxbzoiFuM/VbsmHJb2d+wwDHZcwJqkMTex3Xljax5auw7oY= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1713387110; c=relaxed/simple; bh=Ry9ykynfK98Cvf3Q1pp9WYqTt5oOvS+CaaRIRxnqa2g=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=HSQelWtLoaIiqYwnlkbBe3I4VH+9QPuE7WyothqlFf8rEJ21TaZp9gAGd8l7dH3ese0Q7KefHSSkVQ48Gh66q+k5xEpBY/d1ygLS84S+/SxE/aMbWoOewZnZ6XOC6DqqKiNAuYCZ3eKIlnHl/eY76r1a/mwmne3XNy52d4xES9Q= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=FN/bVvdT; arc=none smtp.client-ip=209.85.218.47 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="FN/bVvdT" Received: by mail-ej1-f47.google.com with SMTP id a640c23a62f3a-a52aa665747so5955166b.2; Wed, 17 Apr 2024 13:51:48 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1713387107; x=1713991907; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=xG7aqADrQaHWXWSQ8K/JRNSWezg0kHHHITZ1GehyH4E=; b=FN/bVvdTd4RVaBIWzBgtZYdNYV9lsTA0yLTXckB1nr9xlNPfR7Qt6xr3x/ghwaqvPT JhiE6WSv2nTJJoaju8CHAM566jiZSvK8expMsWdFbsjFw43RcYcTjDzbiIINaYMRoDNg lJHqmlQAp9wmcEx+AKepb0nWhdkUHJu8kyujJcSE2E77nK6RylU64HAOqPFEOgfplUqM ebSHBaz8XY6834iSdEDwgq6NEPAYBqnp9ovU8a6dJrKHdd5DHz2b+T5sDZ2wYt5hm5Q6 tU1D/yF+OheDEwESm/gz+wd6FllNoEFDTRXQGI9Q0T95Xn5+3BN15q0gi1TXkz/tFjfz rzdQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1713387107; x=1713991907; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=xG7aqADrQaHWXWSQ8K/JRNSWezg0kHHHITZ1GehyH4E=; b=npvGmkFW1srZ/DHOzNB5FYQ9D5Qqu5vcGafOCA6bZMQiuZBCpVs6qkLA/CggJy/wXG 5AFP9JM+44WlnDQsgQtXp4+gB2ZSNnf2ahflWCiqEvBHPr1ln13g4RhnrDDuBDhmG+kT tJA8CRF4AHDx/AV2opIiE6ck/dWvJ7Uf4jLARAdF4tBJPqg/Fpxot/V6GTpRVjrg6LGP N8lQPZPuIotQSC0m24p1cQRpIdB95bXHN/9ch9ss6QNijXznB9k2GJhMcyaZz2eBMqqx zr4GZzdrW8lSVDflTC70KVie21IIIAXSLxLoqDSmB6uDgLDPN5RPmxEST9Dg45NIX4B0 oOjw== X-Forwarded-Encrypted: i=1; AJvYcCU2RPpve9LsNPYVgS+crTTYAPMz+ARbiGLIUkZ7V3vofZW2kMXNnjUqNrXekVxW/Z6GqesyZZIRLX6ECDI+XCWI1vT8wwW23q6KkVvj X-Gm-Message-State: AOJu0YyhzZjk+d2TwcQj5syuVum4pwGFyWRBPwB3CiM8VICrWtoCaCvt e3kQT8YIearUSmLs8du0F24Z6aGiRXWklj+xe+frAKomO4rfnrcVWhym4wJa X-Google-Smtp-Source: AGHT+IFaGTgQQ2aUYhbgxxYsmIVbcg7oHHOnJq5fwm8d01J7Sixey9WLL/WBFXcl1gd5RmpZENrInQ== X-Received: by 2002:a17:906:66c5:b0:a52:140c:5724 with SMTP id k5-20020a17090666c500b00a52140c5724mr382349ejp.14.1713387106632; Wed, 17 Apr 2024 13:51:46 -0700 (PDT) Received: from WBEC325.dom.lan ([185.188.71.122]) by smtp.gmail.com with ESMTPSA id tx24-20020a1709078e9800b00a554177a2cdsm31752ejc.85.2024.04.17.13.51.45 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 17 Apr 2024 13:51:46 -0700 (PDT) From: Pawel Dembicki To: netdev@vger.kernel.org Cc: Pawel Dembicki , Linus Walleij , Florian Fainelli , Vladimir Oltean , Andrew Lunn , Florian Fainelli , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Russell King , linux-kernel@vger.kernel.org Subject: [PATCH net-next v2 5/5] net: dsa: vsc73xx: add structure descriptions Date: Wed, 17 Apr 2024 22:50:48 +0200 Message-Id: <20240417205048.3542839-6-paweldembicki@gmail.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240417205048.3542839-1-paweldembicki@gmail.com> References: <20240417205048.3542839-1-paweldembicki@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" This commit adds updates to the documentation describing the structures used in vsc73xx. This will help prevent kdoc-related issues in the future. Reviewed-by: Linus Walleij Reviewed-by: Florian Fainelli Reviewed-by: Vladimir Oltean Signed-off-by: Pawel Dembicki --- v2: - resend only drivers/net/dsa/vitesse-vsc73xx.h | 16 +++++++++++++++- 1 file changed, 15 insertions(+), 1 deletion(-) diff --git a/drivers/net/dsa/vitesse-vsc73xx.h b/drivers/net/dsa/vitesse-vs= c73xx.h index fee1378508b5..2997f7e108b1 100644 --- a/drivers/net/dsa/vitesse-vsc73xx.h +++ b/drivers/net/dsa/vitesse-vsc73xx.h @@ -15,7 +15,16 @@ #define VSC73XX_MAX_NUM_PORTS 8 =20 /** - * struct vsc73xx - VSC73xx state container + * struct vsc73xx - VSC73xx state container: main data structure + * @dev: The device pointer + * @reset: The descriptor for the GPIO line tied to the reset pin + * @ds: Pointer to the DSA core structure + * @gc: Main structure of the GPIO controller + * @chipid: Storage for the Chip ID value read from the CHIPID register of= the + * switch + * @addr: MAC address used in flow control frames + * @ops: Structure with hardware-dependent operations + * @priv: Pointer to the configuration interface structure */ struct vsc73xx { struct device *dev; @@ -28,6 +37,11 @@ struct vsc73xx { void *priv; }; =20 +/** + * struct vsc73xx_ops - VSC73xx methods container + * @read: Method for register reading over the hardware-dependent interface + * @write: Method for register writing over the hardware-dependent interfa= ce + */ struct vsc73xx_ops { int (*read)(struct vsc73xx *vsc, u8 block, u8 subblock, u8 reg, u32 *val); --=20 2.34.1