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Wed, 17 Apr 2024 20:08:53 +0000 Received: from pps.filterd (iadpaimrmta02.imrmtpd1.prodappiadaev1.oraclevcn.com [127.0.0.1]) by iadpaimrmta02.imrmtpd1.prodappiadaev1.oraclevcn.com (8.17.1.19/8.17.1.19) with ESMTP id 43HJ7SRb021661; Wed, 17 Apr 2024 20:08:51 GMT Received: from pps.reinject (localhost [127.0.0.1]) by iadpaimrmta02.imrmtpd1.prodappiadaev1.oraclevcn.com (PPS) with ESMTPS id 3xfggfny8t-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Wed, 17 Apr 2024 20:08:51 +0000 Received: from iadpaimrmta02.imrmtpd1.prodappiadaev1.oraclevcn.com (iadpaimrmta02.imrmtpd1.prodappiadaev1.oraclevcn.com [127.0.0.1]) by pps.reinject (8.17.1.5/8.17.1.5) with ESMTP id 43HK8oFP023405; Wed, 17 Apr 2024 20:08:51 GMT Received: from alaljime-dev-e4flex-vm.osdevelopmeniad.oraclevcn.com (alaljime-dev-e4flex-vm.allregionaliads.osdevelopmeniad.oraclevcn.com [100.100.249.106]) by iadpaimrmta02.imrmtpd1.prodappiadaev1.oraclevcn.com (PPS) with ESMTP id 3xfggfny84-2; Wed, 17 Apr 2024 20:08:51 +0000 From: Alejandro Jimenez To: kvm@vger.kernel.org Cc: seanjc@google.com, pbonzini@redhat.com, linux-kernel@vger.kernel.org, joao.m.martins@oracle.com, boris.ostrovsky@oracle.com, suravee.suthikulpanit@amd.com, mlevitsk@redhat.com, alejandro.j.jimenez@oracle.com Subject: [PATCH 1/2] KVM: x86: Only set APICV_INHIBIT_REASON_ABSENT if APICv is enabled Date: Wed, 17 Apr 2024 20:08:48 +0000 Message-Id: <20240417200849.971433-2-alejandro.j.jimenez@oracle.com> X-Mailer: git-send-email 2.39.3 In-Reply-To: <20240417200849.971433-1-alejandro.j.jimenez@oracle.com> References: <20240417200849.971433-1-alejandro.j.jimenez@oracle.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.272,Aquarius:18.0.1011,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2024-04-17_17,2024-04-17_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=notspam policy=default score=0 spamscore=0 mlxscore=0 mlxlogscore=999 suspectscore=0 adultscore=0 phishscore=0 bulkscore=0 malwarescore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2404010000 definitions=main-2404170141 X-Proofpoint-ORIG-GUID: XHRQMvcBTBOdGB8dk9KfEoSb_2IybWlv X-Proofpoint-GUID: XHRQMvcBTBOdGB8dk9KfEoSb_2IybWlv Content-Type: text/plain; charset="utf-8" Use the APICv enablement status to determine if APICV_INHIBIT_REASON_ABSENT needs to be set, instead of unconditionally setting the reason during initialization. Specifically, in cases where AVIC is disabled via module parameter or lack of hardware support, unconditionally setting an inhibit reason due to the absence of an in-kernel local APIC can lead to a scenario where the reason incorrectly remains set after a local APIC has been created by either KVM_CREATE_IRQCHIP or the enabling of KVM_CAP_IRQCHIP_SPLIT. This is because the helpers in charge of removing the inhibit return early if enable_apicv is not true, and therefore the bit remains set. This leads to confusion as to the cause why APICv is not active, since an incorrect reason will be reported by tracepoints and/or a debugging tool that examines the currently set inhibit reasons. Fixes: ef8b4b720368 ("KVM: ensure APICv is considered inactive if there is = no APIC") Signed-off-by: Alejandro Jimenez --- arch/x86/kvm/x86.c | 15 ++++++++++++++- 1 file changed, 14 insertions(+), 1 deletion(-) diff --git a/arch/x86/kvm/x86.c b/arch/x86/kvm/x86.c index 26288ca05364..eadd88fabadc 100644 --- a/arch/x86/kvm/x86.c +++ b/arch/x86/kvm/x86.c @@ -9999,7 +9999,20 @@ static void kvm_apicv_init(struct kvm *kvm) =20 init_rwsem(&kvm->arch.apicv_update_lock); =20 - set_or_clear_apicv_inhibit(inhibits, APICV_INHIBIT_REASON_ABSENT, true); + /* + * Unconditionally inhibiting APICv due to the absence of in-kernel + * local APIC can lead to a scenario where APICV_INHIBIT_REASON_ABSENT + * remains set in the apicv_inhibit_reasons after a local APIC has been + * created by either KVM_CREATE_IRQCHIP or the enabling of + * KVM_CAP_IRQCHIP_SPLIT. + * Hardware support and module parameters governing APICv enablement + * have already been evaluated and the initial status is available in + * enable_apicv, so it can be used here to determine if an inhibit needs + * to be set. + */ + if (enable_apicv) + set_or_clear_apicv_inhibit(inhibits, + APICV_INHIBIT_REASON_ABSENT, true); =20 if (!enable_apicv) set_or_clear_apicv_inhibit(inhibits, --=20 2.39.3 From nobody Tue May 21 09:19:47 2024 Received: from mx0a-00069f02.pphosted.com (mx0a-00069f02.pphosted.com [205.220.165.32]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 9BBF236126; Wed, 17 Apr 2024 20:08:58 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.165.32 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1713384540; cv=none; b=jpm0yH2lctjy2sv1wrNwrhzspBgqfpD0797k2bE3dkRRoZ/tKQvrJEt5dOxFmD3VrHuc+DA0iyVv8ouYtE76+/NPZoUZbQ2b+jE8KTKWcgqXcieGyqWks0q3emk4itA5Ov+BGL80kox6rzQW9IEfDZM+4f2DSQxTHwV129iPuzw= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1713384540; c=relaxed/simple; bh=oQpiWnJBZrZr5K7EFvEe+HixtI3es0yTeL+0nXlBB3k=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=rDds/KWCq8xNvRIoaW7DTqNReA+3dbqnThgDnaz3H+WJeiXiGtcGVjpzrlkYpmNAEy4dW17bvdIYuPd1IZ76J3V5GElsgw0nnSj6GPI8X04vbcjn6JkxZNU/miJplPxqKuZ13Bga9ANEtpvyyp9ds7fmIplSa5+zr6SE+w2MvHM= ARC-Authentication-Results: i=1; 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charset="utf-8" The kvm_pi_irte_update tracepoint is called from both SVM and VMX vendor code, and while the "posted interrupt" naming is also adopted by SVM in several places, VT-d specifically refers to Intel's "Virtualization Technology for Directed I/O". Signed-off-by: Alejandro Jimenez --- arch/x86/kvm/trace.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/x86/kvm/trace.h b/arch/x86/kvm/trace.h index c6b4b1728006..9d0b02ef307e 100644 --- a/arch/x86/kvm/trace.h +++ b/arch/x86/kvm/trace.h @@ -1074,7 +1074,7 @@ TRACE_EVENT(kvm_smm_transition, ); =20 /* - * Tracepoint for VT-d posted-interrupts. + * Tracepoint for VT-d posted-interrupts and AMD-Vi Guest Virtual APIC. */ TRACE_EVENT(kvm_pi_irte_update, TP_PROTO(unsigned int host_irq, unsigned int vcpu_id, @@ -1100,7 +1100,7 @@ TRACE_EVENT(kvm_pi_irte_update, __entry->set =3D set; ), =20 - TP_printk("VT-d PI is %s for irq %u, vcpu %u, gsi: 0x%x, " + TP_printk("PI is %s for irq %u, vcpu %u, gsi: 0x%x, " "gvec: 0x%x, pi_desc_addr: 0x%llx", __entry->set ? "enabled and being updated" : "disabled", __entry->host_irq, --=20 2.39.3