From nobody Fri May 17 01:43:36 2024 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id D2D8D13AA46 for ; Wed, 17 Apr 2024 09:39:02 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1713346744; cv=none; b=OmUMKVYsDHxCTyBWFv3tsiF8l01XMeEistoL2GgBqFjzf5G/4z5MPwycrMiHLg1J6KgDvyBJaj6XAxXHNH4bQNqWl3Z5ZZoB3C4YDxOxQ0k0mmkVex+3E/KpweBDW4NR6qmv8eXwso4m7Xe1HtETjP2dVuFsDkmQh4hcvguMNjk= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1713346744; c=relaxed/simple; bh=LE515nvwvBtP8gvCOVvIKqxcZH+UImq3DBTaJCX47A4=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=udXTDRX0JJTNDCmpbtA5gOWGUX+Tdsq+uB2lMudJSZ1iXUPulplgckiyYaGJWJZn987P3CiOM4NeDqVdcNMCQep7slcH8jmu0I3dI8y43bLlpcWI/qNhMn05XEGUP0MBMqA16dwaqIXCKVMjFGHzML7PX9SJT50VzoyhUXnjuEA= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com; spf=pass smtp.mailfrom=arm.com; arc=none smtp.client-ip=217.140.110.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 20C32DA7; Wed, 17 Apr 2024 02:39:30 -0700 (PDT) Received: from e125905.cambridge.arm.com (e125905.cambridge.arm.com [10.1.194.73]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 71D283F64C; Wed, 17 Apr 2024 02:39:00 -0700 (PDT) From: Beata Michalska To: linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, ionela.voinescu@arm.com, vanshikonda@os.amperecomputing.com Cc: sudeep.holla@arm.com, will@kernel.org, catalin.marinas@arm.com, vincent.guittot@linaro.org, sumitg@nvidia.com, yang@os.amperecomputing.com, lihuisong@huawei.com, viresh.kumar@linaro.org Subject: [PATCH v5 1/5] arch_topology: init capacity_freq_ref to 0 Date: Wed, 17 Apr 2024 10:38:44 +0100 Message-Id: <20240417093848.1555462-2-beata.michalska@arm.com> In-Reply-To: <20240417093848.1555462-1-beata.michalska@arm.com> References: <20240417093848.1555462-1-beata.michalska@arm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Ionela Voinescu It's useful to have capacity_freq_ref initialized to 0 for users of arch_scale_freq_ref() to detect when capacity_freq_ref was not yet set. The only scenario affected by this change in the init value is when a cpufreq driver is never loaded. As a result, the only setter of a cpu scale factor remains the call of topology_normalize_cpu_scale() from parse_dt_topology(). There we cannot use the value 0 of capacity_freq_ref so we have to compensate for its uninitialized state. Signed-off-by: Ionela Voinescu Signed-off-by: Beata Michalska Reviewed-by: Vincent Guittot Reviewed-by: Sudeep Holla --- drivers/base/arch_topology.c | 8 +++++--- 1 file changed, 5 insertions(+), 3 deletions(-) diff --git a/drivers/base/arch_topology.c b/drivers/base/arch_topology.c index 024b78a0cfc1..7d4c92cd2bad 100644 --- a/drivers/base/arch_topology.c +++ b/drivers/base/arch_topology.c @@ -27,7 +27,7 @@ static DEFINE_PER_CPU(struct scale_freq_data __rcu *, sft_data); static struct cpumask scale_freq_counters_mask; static bool scale_freq_invariant; -DEFINE_PER_CPU(unsigned long, capacity_freq_ref) =3D 1; +DEFINE_PER_CPU(unsigned long, capacity_freq_ref) =3D 0; EXPORT_PER_CPU_SYMBOL_GPL(capacity_freq_ref); =20 static bool supports_scale_freq_counters(const struct cpumask *cpus) @@ -292,13 +292,15 @@ void topology_normalize_cpu_scale(void) =20 capacity_scale =3D 1; for_each_possible_cpu(cpu) { - capacity =3D raw_capacity[cpu] * per_cpu(capacity_freq_ref, cpu); + capacity =3D raw_capacity[cpu] * + (per_cpu(capacity_freq_ref, cpu) ?: 1); capacity_scale =3D max(capacity, capacity_scale); } =20 pr_debug("cpu_capacity: capacity_scale=3D%llu\n", capacity_scale); for_each_possible_cpu(cpu) { - capacity =3D raw_capacity[cpu] * per_cpu(capacity_freq_ref, cpu); + capacity =3D raw_capacity[cpu] * + (per_cpu(capacity_freq_ref, cpu) ?: 1); capacity =3D div64_u64(capacity << SCHED_CAPACITY_SHIFT, capacity_scale); topology_set_cpu_scale(cpu, capacity); --=20 2.25.1 From nobody Fri May 17 01:43:36 2024 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id A6DAE13B2AD for ; Wed, 17 Apr 2024 09:39:04 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1713346746; cv=none; b=QXJt33mahXNB5FD8zy5K5DfzWztPRUqhXdip4/BjT/QSzI6GLgHilXXIAbfiKXHMLQ/SljGO7LlAhtFH/I3mJlrE3NVvaRuQGOD6qBDPoAsohORHa8UsAJ3PuI8JllSImG5OEQFzpnSGqeh3YaN0J9ZlLQjh5OFYP7M9KkgqVTo= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1713346746; c=relaxed/simple; bh=rm5gnrW6WxA+AIgPz7xS8aswy3kAdWUF9mo+gESmArA=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=PmHrPql0qB/pcQZoEkzQvgVCKUYy+sV5B1QYqFgBrG84QQCiiwZWGJTRcG8T41MB/fPbYKpikjTu3qDHjmbTlz+y3dfNypPDuEQQI9V4Uxn2yR06xs00pi1ebadChQF3y/383jyH3pu1B8taFXU6YDJ5E7uNX/Vw1Zx7fn+dObY= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com; spf=pass smtp.mailfrom=arm.com; arc=none smtp.client-ip=217.140.110.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 3870B1477; Wed, 17 Apr 2024 02:39:32 -0700 (PDT) Received: from e125905.cambridge.arm.com (e125905.cambridge.arm.com [10.1.194.73]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 808E13F64C; Wed, 17 Apr 2024 02:39:02 -0700 (PDT) From: Beata Michalska To: linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, ionela.voinescu@arm.com, vanshikonda@os.amperecomputing.com Cc: sudeep.holla@arm.com, will@kernel.org, catalin.marinas@arm.com, vincent.guittot@linaro.org, sumitg@nvidia.com, yang@os.amperecomputing.com, lihuisong@huawei.com, viresh.kumar@linaro.org Subject: [PATCH v5 2/5] arm64: amu: Rule out potential use after free Date: Wed, 17 Apr 2024 10:38:45 +0100 Message-Id: <20240417093848.1555462-3-beata.michalska@arm.com> In-Reply-To: <20240417093848.1555462-1-beata.michalska@arm.com> References: <20240417093848.1555462-1-beata.michalska@arm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" For the time being, the amu_fie_cpus cpumask is being exclusively used by the AMU-related internals of FIE support and is guaranteed to be valid on every access currently made. Still the mask is not being invalidated on one of the error handling code paths, which leaves a soft spot with potential risk of uaf for CPUMASK_OFFSTACK cases. To make things sound, set the cpumaks pointer explicitly to NULL upon failing to register the cpufreq notifier. Note that, due to the quirks of CPUMASK_OFFSTACK, this change needs to be wrapped with grim ifdefing (it would be better served by incorporating this into free_cpumask_var ...) Signed-off-by: Beata Michalska --- arch/arm64/kernel/topology.c | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/arch/arm64/kernel/topology.c b/arch/arm64/kernel/topology.c index 1a2c72f3e7f8..3c814a278534 100644 --- a/arch/arm64/kernel/topology.c +++ b/arch/arm64/kernel/topology.c @@ -244,8 +244,12 @@ static int __init init_amu_fie(void) =20 ret =3D cpufreq_register_notifier(&init_amu_fie_notifier, CPUFREQ_POLICY_NOTIFIER); - if (ret) + if (ret) { free_cpumask_var(amu_fie_cpus); +#ifdef CONFIG_CPUMASK_OFFSTACK + amu_fie_cpus =3D NULL; +#endif + } =20 return ret; } --=20 2.25.1 From nobody Fri May 17 01:43:36 2024 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id EE12113BC27 for ; Wed, 17 Apr 2024 09:39:06 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1713346748; cv=none; b=F+FaCq9ZHqAe1nXr0ZUigc4hFXQRcmnPQHeVg534ZrTBj9i5YbeGCwqqhB7EolFVmXBdrOMwmiuAVqf98EcOoVaNpqTilt9dhwHWAQ18rnYv//08M4Z67nwAZCotiwlFrMAGADTLgvtgHlVJS30cuHyV9pWy1ORTjkkmprCF+ns= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1713346748; c=relaxed/simple; bh=6Kf4TEq0xo+qbeDKaHo21g+8plqDAFb2M+va4OvXqcY=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=EUh4VruzSt47uDbCKTjzmGE+B0yfzl+ZPoBfYKE02K7nyUIrvQC3Kx1OIy21gZYywugItqriG+pBXdns2Idmn+YTaJeYIbNAhK6Pd7/cc3RcWMSqtuy7xAdZFsDiSNSTQmARqEOrO2wOcehgxecICEFEzcmW5iCCOLYAiFUTOxg= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com; spf=pass smtp.mailfrom=arm.com; arc=none smtp.client-ip=217.140.110.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 47314339; Wed, 17 Apr 2024 02:39:34 -0700 (PDT) Received: from e125905.cambridge.arm.com (e125905.cambridge.arm.com [10.1.194.73]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 9881C3F64C; Wed, 17 Apr 2024 02:39:04 -0700 (PDT) From: Beata Michalska To: linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, ionela.voinescu@arm.com, vanshikonda@os.amperecomputing.com Cc: sudeep.holla@arm.com, will@kernel.org, catalin.marinas@arm.com, vincent.guittot@linaro.org, sumitg@nvidia.com, yang@os.amperecomputing.com, lihuisong@huawei.com, viresh.kumar@linaro.org Subject: [PATCH v5 3/5] arm64: Provide an AMU-based version of arch_freq_get_on_cpu Date: Wed, 17 Apr 2024 10:38:46 +0100 Message-Id: <20240417093848.1555462-4-beata.michalska@arm.com> In-Reply-To: <20240417093848.1555462-1-beata.michalska@arm.com> References: <20240417093848.1555462-1-beata.michalska@arm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" With the Frequency Invariance Engine (FIE) being already wired up with sched tick and making use of relevant (core counter and constant counter) AMU counters, getting the current frequency for a given CPU, can be achieved by utilizing the frequency scale factor which reflects an average CPU frequency for the last tick period length. The solution is partially based on APERF/MPERF implementation of arch_freq_get_on_cpu. Suggested-by: Ionela Voinescu Signed-off-by: Beata Michalska --- arch/arm64/kernel/topology.c | 110 +++++++++++++++++++++++++++++++---- 1 file changed, 100 insertions(+), 10 deletions(-) diff --git a/arch/arm64/kernel/topology.c b/arch/arm64/kernel/topology.c index 3c814a278534..475fdbf3032a 100644 --- a/arch/arm64/kernel/topology.c +++ b/arch/arm64/kernel/topology.c @@ -17,6 +17,7 @@ #include #include #include +#include =20 #include #include @@ -88,18 +89,28 @@ int __init parse_acpi_topology(void) * initialized. */ static DEFINE_PER_CPU_READ_MOSTLY(unsigned long, arch_max_freq_scale) =3D = 1UL << (2 * SCHED_CAPACITY_SHIFT); -static DEFINE_PER_CPU(u64, arch_const_cycles_prev); -static DEFINE_PER_CPU(u64, arch_core_cycles_prev); static cpumask_var_t amu_fie_cpus; =20 +struct amu_cntr_sample { + u64 arch_const_cycles_prev; + u64 arch_core_cycles_prev; + unsigned long last_update; +}; + +static DEFINE_PER_CPU_SHARED_ALIGNED(struct amu_cntr_sample, cpu_amu_sampl= es); + void update_freq_counters_refs(void) { - this_cpu_write(arch_core_cycles_prev, read_corecnt()); - this_cpu_write(arch_const_cycles_prev, read_constcnt()); + struct amu_cntr_sample *amu_sample =3D this_cpu_ptr(&cpu_amu_samples); + + amu_sample->arch_core_cycles_prev =3D read_corecnt(); + amu_sample->arch_const_cycles_prev =3D read_constcnt(); } =20 static inline bool freq_counters_valid(int cpu) { + struct amu_cntr_sample *amu_sample =3D per_cpu_ptr(&cpu_amu_samples, cpu); + if ((cpu >=3D nr_cpu_ids) || !cpumask_test_cpu(cpu, cpu_present_mask)) return false; =20 @@ -108,8 +119,8 @@ static inline bool freq_counters_valid(int cpu) return false; } =20 - if (unlikely(!per_cpu(arch_const_cycles_prev, cpu) || - !per_cpu(arch_core_cycles_prev, cpu))) { + if (unlikely(!amu_sample->arch_const_cycles_prev || + !amu_sample->arch_core_cycles_prev)) { pr_debug("CPU%d: cycle counters are not enabled.\n", cpu); return false; } @@ -152,17 +163,22 @@ void freq_inv_set_max_ratio(int cpu, u64 max_rate) =20 static void amu_scale_freq_tick(void) { + struct amu_cntr_sample *amu_sample =3D this_cpu_ptr(&cpu_amu_samples); u64 prev_core_cnt, prev_const_cnt; u64 core_cnt, const_cnt, scale; =20 - prev_const_cnt =3D this_cpu_read(arch_const_cycles_prev); - prev_core_cnt =3D this_cpu_read(arch_core_cycles_prev); + prev_const_cnt =3D amu_sample->arch_const_cycles_prev; + prev_core_cnt =3D amu_sample->arch_core_cycles_prev; =20 update_freq_counters_refs(); =20 - const_cnt =3D this_cpu_read(arch_const_cycles_prev); - core_cnt =3D this_cpu_read(arch_core_cycles_prev); + const_cnt =3D amu_sample->arch_const_cycles_prev; + core_cnt =3D amu_sample->arch_core_cycles_prev; =20 + /* + * This should not happen unless the AMUs have been reset and the + * counter values have not been restored - unlikely + */ if (unlikely(core_cnt <=3D prev_core_cnt || const_cnt <=3D prev_const_cnt)) return; @@ -182,6 +198,8 @@ static void amu_scale_freq_tick(void) =20 scale =3D min_t(unsigned long, scale, SCHED_CAPACITY_SCALE); this_cpu_write(arch_freq_scale, (unsigned long)scale); + + amu_sample->last_update =3D jiffies; } =20 static struct scale_freq_data amu_sfd =3D { @@ -189,6 +207,78 @@ static struct scale_freq_data amu_sfd =3D { .set_freq_scale =3D amu_scale_freq_tick, }; =20 +static __always_inline bool amu_fie_cpu_supported(unsigned int cpu) +{ + return cpumask_available(amu_fie_cpus) && + cpumask_test_cpu(cpu, amu_fie_cpus); +} + +#define AMU_SAMPLE_EXP_MS 20 + +unsigned int arch_freq_get_on_cpu(int cpu) +{ + struct amu_cntr_sample *amu_sample; + unsigned int start_cpu =3D cpu; + unsigned long last_update; + unsigned int freq =3D 0; + u64 scale; + + if (!amu_fie_cpu_supported(cpu) || !arch_scale_freq_ref(cpu)) + return 0; + +retry: + amu_sample =3D per_cpu_ptr(&cpu_amu_samples, cpu); + + last_update =3D amu_sample->last_update; + + /* + * For those CPUs that are in full dynticks mode, + * and those that have not seen tick for a while + * try an alternative source for the counters (and thus freq scale), + * if available, for given policy: + * this boils down to identifying an active cpu within the same freq + * domain, if any. + */ + if (!housekeeping_cpu(cpu, HK_TYPE_TICK) || + time_is_before_jiffies(last_update + msecs_to_jiffies(AMU_SAMPLE_EXP_= MS))) { + struct cpufreq_policy *policy =3D cpufreq_cpu_get(cpu); + int ref_cpu =3D cpu; + + if (!policy) + goto leave; + + if (!policy_is_shared(policy)) { + cpufreq_cpu_put(policy); + goto leave; + } + + do { + ref_cpu =3D cpumask_next_wrap(ref_cpu, policy->cpus, + start_cpu, false); + + } while (ref_cpu < nr_cpu_ids && idle_cpu(ref_cpu)); + + cpufreq_cpu_put(policy); + + if (ref_cpu >=3D nr_cpu_ids) + /* No alternative to pull info from */ + goto leave; + + cpu =3D ref_cpu; + goto retry; + } + /* + * Reversed computation to the one used to determine + * the arch_freq_scale value + * (see amu_scale_freq_tick for details) + */ + scale =3D arch_scale_freq_capacity(cpu); + freq =3D scale * arch_scale_freq_ref(cpu); + freq >>=3D SCHED_CAPACITY_SHIFT; +leave: + return freq; +} + static void amu_fie_setup(const struct cpumask *cpus) { int cpu; --=20 2.25.1 From nobody Fri May 17 01:43:36 2024 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 0863913C3D4 for ; Wed, 17 Apr 2024 09:39:08 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; 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spf=pass smtp.mailfrom=arm.com Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 55EA7DA7; Wed, 17 Apr 2024 02:39:36 -0700 (PDT) Received: from e125905.cambridge.arm.com (e125905.cambridge.arm.com [10.1.194.73]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id A741E3F64C; Wed, 17 Apr 2024 02:39:06 -0700 (PDT) From: Beata Michalska To: linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, ionela.voinescu@arm.com, vanshikonda@os.amperecomputing.com Cc: sudeep.holla@arm.com, will@kernel.org, catalin.marinas@arm.com, vincent.guittot@linaro.org, sumitg@nvidia.com, yang@os.amperecomputing.com, lihuisong@huawei.com, viresh.kumar@linaro.org Subject: [PATCH v5 4/5] arm64: Update AMU-based frequency scale factor on entering idle Date: Wed, 17 Apr 2024 10:38:47 +0100 Message-Id: <20240417093848.1555462-5-beata.michalska@arm.com> In-Reply-To: <20240417093848.1555462-1-beata.michalska@arm.com> References: <20240417093848.1555462-1-beata.michalska@arm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Now that the frequency scale factor has been activated for retrieving current frequency on a given CPU, trigger its update upon entering idle. This will, to an extent, allow querying last known frequency in a non-invasive way. It will also improve the frequency scale factor accuracy when a CPU entering idle did not receive a tick for a while. As a consequence, for idle cores, the reported frequency will be the last one observed before entering the idle state. Suggested-by: Vanshidhar Konda Signed-off-by: Beata Michalska --- arch/arm64/kernel/topology.c | 17 +++++++++++++++-- 1 file changed, 15 insertions(+), 2 deletions(-) diff --git a/arch/arm64/kernel/topology.c b/arch/arm64/kernel/topology.c index 475fdbf3032a..3110863ee18c 100644 --- a/arch/arm64/kernel/topology.c +++ b/arch/arm64/kernel/topology.c @@ -213,6 +213,19 @@ static __always_inline bool amu_fie_cpu_supported(unsi= gned int cpu) cpumask_test_cpu(cpu, amu_fie_cpus); } =20 +void arch_cpu_idle_enter(void) +{ + unsigned int cpu =3D smp_processor_id(); + + if (!amu_fie_cpu_supported(cpu)) + return; + + /* Kick in AMU update but only if one has not happened already */ + if (housekeeping_cpu(cpu, HK_TYPE_TICK) && + time_is_before_jiffies(per_cpu(cpu_amu_samples.last_update, cpu))) + amu_scale_freq_tick(); +} + #define AMU_SAMPLE_EXP_MS 20 =20 unsigned int arch_freq_get_on_cpu(int cpu) @@ -239,8 +252,8 @@ unsigned int arch_freq_get_on_cpu(int cpu) * this boils down to identifying an active cpu within the same freq * domain, if any. */ - if (!housekeeping_cpu(cpu, HK_TYPE_TICK) || - time_is_before_jiffies(last_update + msecs_to_jiffies(AMU_SAMPLE_EXP_= MS))) { + if (!housekeeping_cpu(cpu, HK_TYPE_TICK) || (!idle_cpu(cpu) && + time_is_before_jiffies(last_update + msecs_to_jiffies(AMU_SAMPLE_EXP_= MS)))) { struct cpufreq_policy *policy =3D cpufreq_cpu_get(cpu); int ref_cpu =3D cpu; =20 --=20 2.25.1 From nobody Fri May 17 01:43:36 2024 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id DABB313C3FF for ; Wed, 17 Apr 2024 09:39:10 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1713346752; cv=none; b=Y5UqMilRpob1xrk6HvXjM+OAc7C9LvpTsrHKH5GoDcyF/jK2HPkGfyvOacC60bQ/hO0uk2pMuVXVyagLuwD62KtLg6yovBUfAMlnx0CPpC35/2MLcbhvXYXWcobfRRaawbdjrP48A+2Y6cMbTHo61y5RMwxeWKCU5OrHZjwvlDE= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1713346752; c=relaxed/simple; bh=zVISUDfH5Und8B2M0/FRkHymAWK9FfVIOHuACS05Y0w=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=iKCPXaLFTySGi5FPQ91TMSEw7Ual9ur04VY5+7+UaUKpauy++qmo1zMouDDyK6GgcQIKw5tW+lKBR2TZ5DVilNso9wQtK2IkZG6Q56cexAVdZpVw2SvJhO/kbTuovY/oPOIzXavapLs/sbyhH0Qy/O1YCJdfWkf3qVuABnRgi0g= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com; spf=pass smtp.mailfrom=arm.com; arc=none smtp.client-ip=217.140.110.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 6D3A21477; Wed, 17 Apr 2024 02:39:38 -0700 (PDT) Received: from e125905.cambridge.arm.com (e125905.cambridge.arm.com [10.1.194.73]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id B5D333F64C; Wed, 17 Apr 2024 02:39:08 -0700 (PDT) From: Beata Michalska To: linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, ionela.voinescu@arm.com, vanshikonda@os.amperecomputing.com Cc: sudeep.holla@arm.com, will@kernel.org, catalin.marinas@arm.com, vincent.guittot@linaro.org, sumitg@nvidia.com, yang@os.amperecomputing.com, lihuisong@huawei.com, viresh.kumar@linaro.org Subject: [PATCH v5 5/5] cpufreq: Use arch specific feedback for cpuinfo_cur_freq Date: Wed, 17 Apr 2024 10:38:48 +0100 Message-Id: <20240417093848.1555462-6-beata.michalska@arm.com> In-Reply-To: <20240417093848.1555462-1-beata.michalska@arm.com> References: <20240417093848.1555462-1-beata.michalska@arm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Some architectures provide a way to determine an average frequency over a certain period of time based on available performance monitors (AMU on ARM or APERF/MPERf on x86). With those at hand, enroll arch_freq_get_on_cpu into cpuinfo_cur_freq policy sysfs attribute handler, which is expected to represent the current frequency of a given CPU,as obtained by the hardware. This is the type of feedback that counters do provide. Signed-off-by: Beata Michalska --- drivers/cpufreq/cpufreq.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/drivers/cpufreq/cpufreq.c b/drivers/cpufreq/cpufreq.c index f6f8d7f450e7..89118406ec68 100644 --- a/drivers/cpufreq/cpufreq.c +++ b/drivers/cpufreq/cpufreq.c @@ -793,8 +793,10 @@ store_one(scaling_max_freq, max); static ssize_t show_cpuinfo_cur_freq(struct cpufreq_policy *policy, char *buf) { - unsigned int cur_freq =3D __cpufreq_get(policy); + unsigned int cur_freq =3D arch_freq_get_on_cpu(policy->cpu); =20 + if (!cur_freq) + cur_freq =3D __cpufreq_get(policy); if (cur_freq) return sprintf(buf, "%u\n", cur_freq); =20 --=20 2.25.1