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a=openpgp; fpr=6AFF162D57F4223A8770EF5AF7BF214136F41FAE Add dedicated schema for X1E80100 PMIC ARB. This is not the first platform to introduce multiple buses. In fact, all platforms that implement the version 7 for the SPMI PMIC arbiter have multiple buses. Since the compatible should not be version based, the platform specific one is used. The X1E80100 platform is the first platform to really need the second master, as all the available boards have the PMICs that provide the eUSB2 repeater on the second bus. Reviewed-by: Krzysztof Kozlowski Signed-off-by: Abel Vesa --- .../bindings/spmi/qcom,x1e80100-spmi-pmic-arb.yaml | 136 +++++++++++++++++= ++++ 1 file changed, 136 insertions(+) diff --git a/Documentation/devicetree/bindings/spmi/qcom,x1e80100-spmi-pmic= -arb.yaml b/Documentation/devicetree/bindings/spmi/qcom,x1e80100-spmi-pmic-= arb.yaml new file mode 100644 index 000000000000..a28b70fb330a --- /dev/null +++ b/Documentation/devicetree/bindings/spmi/qcom,x1e80100-spmi-pmic-arb.ya= ml @@ -0,0 +1,136 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/spmi/qcom,x1e80100-spmi-pmic-arb.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm X1E80100 SPMI Controller (PMIC Arbiter v7) + +maintainers: + - Stephen Boyd + +description: | + The X1E80100 SPMI PMIC Arbiter implements HW version 7 and it's an SPMI + controller with wrapping arbitration logic to allow for multiple on-chip + devices to control up to 2 SPMI separate buses. + + The PMIC Arbiter can also act as an interrupt controller, providing inte= rrupts + to slave devices. + +properties: + compatible: + const: qcom,x1e80100-spmi-pmic-arb + + reg: + items: + - description: core registers + - description: tx-channel per virtual slave registers + - description: rx-channel (called observer) per virtual slave regist= ers + + reg-names: + items: + - const: core + - const: chnls + - const: obsrvr + + ranges: true + + '#address-cells': + const: 2 + + '#size-cells': + const: 2 + + qcom,ee: + $ref: /schemas/types.yaml#/definitions/uint32 + minimum: 0 + maximum: 5 + description: > + indicates the active Execution Environment identifier + + qcom,channel: + $ref: /schemas/types.yaml#/definitions/uint32 + minimum: 0 + maximum: 5 + description: > + which of the PMIC Arb provided channels to use for accesses + +patternProperties: + "^spmi@[a-f0-9]+$": + type: object + $ref: /schemas/spmi/spmi.yaml + unevaluatedProperties: false + + properties: + reg: + items: + - description: configuration registers + - description: interrupt controller registers + + reg-names: + items: + - const: cnfg + - const: intr + + interrupts: + maxItems: 1 + + interrupt-names: + const: periph_irq + + interrupt-controller: true + + '#interrupt-cells': + const: 4 + description: | + cell 1: slave ID for the requested interrupt (0-15) + cell 2: peripheral ID for requested interrupt (0-255) + cell 3: the requested peripheral interrupt (0-7) + cell 4: interrupt flags indicating level-sense information, + as defined in dt-bindings/interrupt-controller/irq.h + +required: + - compatible + - reg-names + - qcom,ee + - qcom,channel + +additionalProperties: false + +examples: + - | + #include + + soc { + #address-cells =3D <2>; + #size-cells =3D <2>; + + spmi: arbiter@c400000 { + compatible =3D "qcom,x1e80100-spmi-pmic-arb"; + reg =3D <0 0x0c400000 0 0x3000>, + <0 0x0c500000 0 0x4000000>, + <0 0x0c440000 0 0x80000>; + reg-names =3D "core", "chnls", "obsrvr"; + + qcom,ee =3D <0>; + qcom,channel =3D <0>; + + #address-cells =3D <2>; + #size-cells =3D <2>; + ranges; + + spmi_bus0: spmi@c42d000 { + reg =3D <0 0x0c42d000 0 0x4000>, + <0 0x0c4c0000 0 0x10000>; + reg-names =3D "cnfg", "intr"; + + interrupt-names =3D "periph_irq"; + interrupts-extended =3D <&pdc 1 IRQ_TYPE_LEVEL_HIGH>; + interrupt-controller; + #interrupt-cells =3D <4>; + + #address-cells =3D <2>; + #size-cells =3D <0>; + }; + }; + }; --=20 2.34.1 From nobody Thu Nov 14 04:39:58 2024 Received: from mail-lj1-f174.google.com (mail-lj1-f174.google.com [209.85.208.174]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 1696438F94 for ; Wed, 17 Apr 2024 20:01:25 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; 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a=openpgp; fpr=6AFF162D57F4223A8770EF5AF7BF214136F41FAE As it is optional and no platform is actually using the secondary bus, deprecate the qcom,bus-id property. For newer platforms that implement SPMI PMIC ARB v7 in HW, the X1E80100 approach should be used. Reviewed-by: Krzysztof Kozlowski Signed-off-by: Abel Vesa --- Documentation/devicetree/bindings/spmi/qcom,spmi-pmic-arb.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/spmi/qcom,spmi-pmic-arb.yaml= b/Documentation/devicetree/bindings/spmi/qcom,spmi-pmic-arb.yaml index f983b4af6db9..51daf1b847a9 100644 --- a/Documentation/devicetree/bindings/spmi/qcom,spmi-pmic-arb.yaml +++ b/Documentation/devicetree/bindings/spmi/qcom,spmi-pmic-arb.yaml @@ -92,6 +92,7 @@ properties: description: > SPMI bus instance. only applicable to PMIC arbiter version 7 and bey= ond. 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a=openpgp; fpr=6AFF162D57F4223A8770EF5AF7BF214136F41FAE Fix the following compile warnings: warning: Function parameter or struct member 'core' not described in 'spmi= _pmic_arb' warning: Function parameter or struct member 'core_size' not described in = 'spmi_pmic_arb' warning: Function parameter or struct member 'mapping_table_valid' not des= cribed in 'spmi_pmic_arb' warning: Function parameter or struct member 'pmic_arb' not described in '= pmic_arb_read_data' warning: Function parameter or struct member 'pmic_arb' not described in '= pmic_arb_write_data' Reviewed-by: Neil Armstrong Signed-off-by: Abel Vesa --- drivers/spmi/spmi-pmic-arb.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/drivers/spmi/spmi-pmic-arb.c b/drivers/spmi/spmi-pmic-arb.c index 937c15324513..12c0efd744c2 100644 --- a/drivers/spmi/spmi-pmic-arb.c +++ b/drivers/spmi/spmi-pmic-arb.c @@ -132,6 +132,8 @@ struct apid_data { * @wr_base: on v1 "core", on v2 "chnls" register base off DT. * @intr: address of the SPMI interrupt control registers. * @cnfg: address of the PMIC Arbiter configuration registers. + * @core: core register base for v2 and above only (see above) + * @core_size: core register base size * @lock: lock to synchronize accesses. * @channel: execution environment channel to use for accesses. * @irq: PMIC ARB interrupt. @@ -144,6 +146,7 @@ struct apid_data { * @apid_count: on v5 and v7: number of APIDs associated with the * particular SPMI bus instance * @mapping_table: in-memory copy of PPID -> APID mapping table. + * @mapping_table_valid:bitmap containing valid-only periphs * @domain: irq domain object for PMIC IRQ domain * @spmic: SPMI controller object * @ver_ops: version dependent operations. @@ -232,6 +235,7 @@ static inline void pmic_arb_set_rd_cmd(struct spmi_pmic= _arb *pmic_arb, =20 /** * pmic_arb_read_data: reads pmic-arb's register and copy 1..4 bytes to buf + * @pmic_arb: the SPMI PMIC arbiter * @bc: byte count -1. range: 0..3 * @reg: register's address * @buf: output parameter, length must be bc + 1 @@ -246,6 +250,7 @@ pmic_arb_read_data(struct spmi_pmic_arb *pmic_arb, u8 *= buf, u32 reg, u8 bc) =20 /** * pmic_arb_write_data: write 1..4 bytes from buf to pmic-arb's register + * @pmic_arb: the SPMI PMIC arbiter * @bc: byte-count -1. range: 0..3. * @reg: register's address. * @buf: buffer to write. length must be bc + 1. --=20 2.34.1 From nobody Thu Nov 14 04:39:58 2024 Received: from mail-ed1-f43.google.com (mail-ed1-f43.google.com [209.85.208.43]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 26CCB3C6AC for ; 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a=openpgp; fpr=6AFF162D57F4223A8770EF5AF7BF214136F41FAE Rather than using conditionals in probe function, add the APID init as a version specific operation. Due to v7, which supports multiple buses, pass on the bus index to be used for sorting out the apid base and count. Reviewed-by: Neil Armstrong Signed-off-by: Abel Vesa --- drivers/spmi/spmi-pmic-arb.c | 144 +++++++++++++++++++++------------------= ---- 1 file changed, 69 insertions(+), 75 deletions(-) diff --git a/drivers/spmi/spmi-pmic-arb.c b/drivers/spmi/spmi-pmic-arb.c index 12c0efd744c2..fe45d62a42e2 100644 --- a/drivers/spmi/spmi-pmic-arb.c +++ b/drivers/spmi/spmi-pmic-arb.c @@ -186,6 +186,7 @@ struct spmi_pmic_arb { * struct pmic_arb_ver_ops - version dependent functionality. * * @ver_str: version string. + * @init_apid: finds the apid base and count * @ppid_to_apid: finds the apid for a given ppid. * @non_data_cmd: on v1 issues an spmi non-data command. * on v2 no HW support, returns -EOPNOTSUPP. @@ -205,6 +206,7 @@ struct spmi_pmic_arb { */ struct pmic_arb_ver_ops { const char *ver_str; + int (*init_apid)(struct spmi_pmic_arb *pmic_arb); int (*ppid_to_apid)(struct spmi_pmic_arb *pmic_arb, u16 ppid); /* spmi commands (read_cmd, write_cmd, cmd) functionality */ int (*offset)(struct spmi_pmic_arb *pmic_arb, u8 sid, u16 addr, @@ -947,6 +949,32 @@ static int qpnpint_irq_domain_alloc(struct irq_domain = *domain, return 0; } =20 +static int pmic_arb_init_apid_min_max(struct spmi_pmic_arb *pmic_arb) +{ + /* + * Initialize max_apid/min_apid to the opposite bounds, during + * the irq domain translation, we are sure to update these + */ + pmic_arb->max_apid =3D 0; + pmic_arb->min_apid =3D pmic_arb->max_periphs - 1; + + return 0; +} + +static int pmic_arb_init_apid_v1(struct spmi_pmic_arb *pmic_arb) +{ + u32 *mapping_table; + + mapping_table =3D devm_kcalloc(&pmic_arb->spmic->dev, pmic_arb->max_perip= hs, + sizeof(*mapping_table), GFP_KERNEL); + if (!mapping_table) + return -ENOMEM; + + pmic_arb->mapping_table =3D mapping_table; + + return pmic_arb_init_apid_min_max(pmic_arb); +} + static int pmic_arb_ppid_to_apid_v1(struct spmi_pmic_arb *pmic_arb, u16 pp= id) { u32 *mapping_table =3D pmic_arb->mapping_table; @@ -1149,6 +1177,34 @@ static int pmic_arb_offset_v2(struct spmi_pmic_arb *= pmic_arb, u8 sid, u16 addr, return 0x1000 * pmic_arb->ee + 0x8000 * apid; } =20 +static int pmic_arb_init_apid_v5(struct spmi_pmic_arb *pmic_arb) +{ + int ret; + + pmic_arb->base_apid =3D 0; + pmic_arb->apid_count =3D readl_relaxed(pmic_arb->core + PMIC_ARB_FEATURES= ) & + PMIC_ARB_FEATURES_PERIPH_MASK; + + if (pmic_arb->base_apid + pmic_arb->apid_count > pmic_arb->max_periphs) { + dev_err(&pmic_arb->spmic->dev, "Unsupported APID count %d detected\n", + pmic_arb->base_apid + pmic_arb->apid_count); + return -EINVAL; + } + + ret =3D pmic_arb_init_apid_min_max(pmic_arb); + if (ret) + return ret; + + ret =3D pmic_arb_read_apid_map_v5(pmic_arb); + if (ret) { + dev_err(&pmic_arb->spmic->dev, "could not read APID->PPID mapping table,= rc=3D %d\n", + ret); + return ret; + } + + return 0; +} + /* * v5 offset per ee and per apid for observer channels and per apid for * read/write channels. @@ -1363,6 +1419,7 @@ pmic_arb_apid_owner_v7(struct spmi_pmic_arb *pmic_arb= , u16 n) =20 static const struct pmic_arb_ver_ops pmic_arb_v1 =3D { .ver_str =3D "v1", + .init_apid =3D pmic_arb_init_apid_v1, .ppid_to_apid =3D pmic_arb_ppid_to_apid_v1, .non_data_cmd =3D pmic_arb_non_data_cmd_v1, .offset =3D pmic_arb_offset_v1, @@ -1377,6 +1434,7 @@ static const struct pmic_arb_ver_ops pmic_arb_v1 =3D { =20 static const struct pmic_arb_ver_ops pmic_arb_v2 =3D { .ver_str =3D "v2", + .init_apid =3D pmic_arb_init_apid_v1, .ppid_to_apid =3D pmic_arb_ppid_to_apid_v2, .non_data_cmd =3D pmic_arb_non_data_cmd_v2, .offset =3D pmic_arb_offset_v2, @@ -1391,6 +1449,7 @@ static const struct pmic_arb_ver_ops pmic_arb_v2 =3D { =20 static const struct pmic_arb_ver_ops pmic_arb_v3 =3D { .ver_str =3D "v3", + .init_apid =3D pmic_arb_init_apid_v1, .ppid_to_apid =3D pmic_arb_ppid_to_apid_v2, .non_data_cmd =3D pmic_arb_non_data_cmd_v2, .offset =3D pmic_arb_offset_v2, @@ -1405,6 +1464,7 @@ static const struct pmic_arb_ver_ops pmic_arb_v3 =3D { =20 static const struct pmic_arb_ver_ops pmic_arb_v5 =3D { .ver_str =3D "v5", + .init_apid =3D pmic_arb_init_apid_v5, .ppid_to_apid =3D pmic_arb_ppid_to_apid_v5, .non_data_cmd =3D pmic_arb_non_data_cmd_v2, .offset =3D pmic_arb_offset_v5, @@ -1419,6 +1479,7 @@ static const struct pmic_arb_ver_ops pmic_arb_v5 =3D { =20 static const struct pmic_arb_ver_ops pmic_arb_v7 =3D { .ver_str =3D "v7", + .init_apid =3D pmic_arb_init_apid_v5, .ppid_to_apid =3D pmic_arb_ppid_to_apid_v5, .non_data_cmd =3D pmic_arb_non_data_cmd_v2, .offset =3D pmic_arb_offset_v7, @@ -1444,7 +1505,6 @@ static int spmi_pmic_arb_probe(struct platform_device= *pdev) struct spmi_controller *ctrl; struct resource *res; void __iomem *core; - u32 *mapping_table; u32 channel, ee, hw_ver; int err; =20 @@ -1472,12 +1532,6 @@ static int spmi_pmic_arb_probe(struct platform_devic= e *pdev) =20 pmic_arb->core_size =3D resource_size(res); =20 - pmic_arb->ppid_to_apid =3D devm_kcalloc(&ctrl->dev, PMIC_ARB_MAX_PPID, - sizeof(*pmic_arb->ppid_to_apid), - GFP_KERNEL); - if (!pmic_arb->ppid_to_apid) - return -ENOMEM; - hw_ver =3D readl_relaxed(core + PMIC_ARB_VERSION); =20 if (hw_ver < PMIC_ARB_VERSION_V2_MIN) { @@ -1511,58 +1565,17 @@ static int spmi_pmic_arb_probe(struct platform_devi= ce *pdev) return -ENOMEM; } =20 - pmic_arb->max_periphs =3D PMIC_ARB_MAX_PERIPHS; + dev_info(&ctrl->dev, "PMIC arbiter version %s (0x%x)\n", + pmic_arb->ver_ops->ver_str, hw_ver); =20 - if (hw_ver >=3D PMIC_ARB_VERSION_V7_MIN) { + if (hw_ver < PMIC_ARB_VERSION_V7_MIN) + pmic_arb->max_periphs =3D PMIC_ARB_MAX_PERIPHS; + else pmic_arb->max_periphs =3D PMIC_ARB_MAX_PERIPHS_V7; - /* Optional property for v7: */ - of_property_read_u32(pdev->dev.of_node, "qcom,bus-id", - &pmic_arb->bus_instance); - if (pmic_arb->bus_instance > 1) { - dev_err(&pdev->dev, "invalid bus instance (%u) specified\n", - pmic_arb->bus_instance); - return -EINVAL; - } =20 - if (pmic_arb->bus_instance =3D=3D 0) { - pmic_arb->base_apid =3D 0; - pmic_arb->apid_count =3D - readl_relaxed(core + PMIC_ARB_FEATURES) & - PMIC_ARB_FEATURES_PERIPH_MASK; - } else { - pmic_arb->base_apid =3D - readl_relaxed(core + PMIC_ARB_FEATURES) & - PMIC_ARB_FEATURES_PERIPH_MASK; - pmic_arb->apid_count =3D - readl_relaxed(core + PMIC_ARB_FEATURES1) & - PMIC_ARB_FEATURES_PERIPH_MASK; - } - - if (pmic_arb->base_apid + pmic_arb->apid_count > pmic_arb->max_periphs) { - dev_err(&pdev->dev, "Unsupported APID count %d detected\n", - pmic_arb->base_apid + pmic_arb->apid_count); - return -EINVAL; - } - } else if (hw_ver >=3D PMIC_ARB_VERSION_V5_MIN) { - pmic_arb->base_apid =3D 0; - pmic_arb->apid_count =3D readl_relaxed(core + PMIC_ARB_FEATURES) & - PMIC_ARB_FEATURES_PERIPH_MASK; - - if (pmic_arb->apid_count > pmic_arb->max_periphs) { - dev_err(&pdev->dev, "Unsupported APID count %d detected\n", - pmic_arb->apid_count); - return -EINVAL; - } - } - - pmic_arb->apid_data =3D devm_kcalloc(&ctrl->dev, pmic_arb->max_periphs, - sizeof(*pmic_arb->apid_data), - GFP_KERNEL); - if (!pmic_arb->apid_data) - return -ENOMEM; - - dev_info(&ctrl->dev, "PMIC arbiter version %s (0x%x)\n", - pmic_arb->ver_ops->ver_str, hw_ver); + err =3D pmic_arb->ver_ops->init_apid(pmic_arb); + if (err) + return err; =20 res =3D platform_get_resource_byname(pdev, IORESOURCE_MEM, "intr"); pmic_arb->intr =3D devm_ioremap_resource(&ctrl->dev, res); @@ -1604,16 +1617,6 @@ static int spmi_pmic_arb_probe(struct platform_devic= e *pdev) } =20 pmic_arb->ee =3D ee; - mapping_table =3D devm_kcalloc(&ctrl->dev, pmic_arb->max_periphs, - sizeof(*mapping_table), GFP_KERNEL); - if (!mapping_table) - return -ENOMEM; - - pmic_arb->mapping_table =3D mapping_table; - /* Initialize max_apid/min_apid to the opposite bounds, during - * the irq domain translation, we are sure to update these */ - pmic_arb->max_apid =3D 0; - pmic_arb->min_apid =3D pmic_arb->max_periphs - 1; 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a=openpgp; fpr=6AFF162D57F4223A8770EF5AF7BF214136F41FAE Rather than setting up the core, obsrv and chnls in probe by using version specific conditionals, add a dedicated "get_core_resources" version specific op and move the acquiring in there. Since there are no current users of the second bus yet, drop the comment about why devm_platform_ioremap_resource can't be used in case of "core", as it is not applicable anymore. Don't switch to devm_platform_ioremap_resource though as we need to keep track of core size. Reviewed-by: Neil Armstrong Signed-off-by: Abel Vesa --- drivers/spmi/spmi-pmic-arb.c | 114 +++++++++++++++++++++++++++------------= ---- 1 file changed, 71 insertions(+), 43 deletions(-) diff --git a/drivers/spmi/spmi-pmic-arb.c b/drivers/spmi/spmi-pmic-arb.c index fe45d62a42e2..db33ca0e11b8 100644 --- a/drivers/spmi/spmi-pmic-arb.c +++ b/drivers/spmi/spmi-pmic-arb.c @@ -186,6 +186,7 @@ struct spmi_pmic_arb { * struct pmic_arb_ver_ops - version dependent functionality. * * @ver_str: version string. + * @get_core_resources: initializes the core, observer and channels * @init_apid: finds the apid base and count * @ppid_to_apid: finds the apid for a given ppid. * @non_data_cmd: on v1 issues an spmi non-data command. @@ -206,6 +207,7 @@ struct spmi_pmic_arb { */ struct pmic_arb_ver_ops { const char *ver_str; + int (*get_core_resources)(struct platform_device *pdev, void __iomem *cor= e); int (*init_apid)(struct spmi_pmic_arb *pmic_arb); int (*ppid_to_apid)(struct spmi_pmic_arb *pmic_arb, u16 ppid); /* spmi commands (read_cmd, write_cmd, cmd) functionality */ @@ -961,6 +963,19 @@ static int pmic_arb_init_apid_min_max(struct spmi_pmic= _arb *pmic_arb) return 0; } =20 +static int pmic_arb_get_core_resources_v1(struct platform_device *pdev, + void __iomem *core) +{ + struct spmi_pmic_arb *pmic_arb =3D platform_get_drvdata(pdev); + + pmic_arb->wr_base =3D core; + pmic_arb->rd_base =3D core; + + pmic_arb->max_periphs =3D PMIC_ARB_MAX_PERIPHS; + + return 0; +} + static int pmic_arb_init_apid_v1(struct spmi_pmic_arb *pmic_arb) { u32 *mapping_table; @@ -1062,6 +1077,33 @@ static u16 pmic_arb_find_apid(struct spmi_pmic_arb *= pmic_arb, u16 ppid) return apid; } =20 +static int pmic_arb_get_obsrvr_chnls_v2(struct platform_device *pdev) +{ + struct spmi_pmic_arb *pmic_arb =3D platform_get_drvdata(pdev); + + pmic_arb->rd_base =3D devm_platform_ioremap_resource_byname(pdev, "obsrvr= "); + if (IS_ERR(pmic_arb->rd_base)) + return PTR_ERR(pmic_arb->rd_base); + + pmic_arb->wr_base =3D devm_platform_ioremap_resource_byname(pdev, "chnls"= ); + if (IS_ERR(pmic_arb->wr_base)) + return PTR_ERR(pmic_arb->wr_base); + + return 0; +} + +static int pmic_arb_get_core_resources_v2(struct platform_device *pdev, + void __iomem *core) +{ + struct spmi_pmic_arb *pmic_arb =3D platform_get_drvdata(pdev); + + pmic_arb->core =3D core; + + pmic_arb->max_periphs =3D PMIC_ARB_MAX_PERIPHS; + + return pmic_arb_get_obsrvr_chnls_v2(pdev); +} + static int pmic_arb_ppid_to_apid_v2(struct spmi_pmic_arb *pmic_arb, u16 pp= id) { u16 apid_valid; @@ -1239,6 +1281,18 @@ static int pmic_arb_offset_v5(struct spmi_pmic_arb *= pmic_arb, u8 sid, u16 addr, return offset; } =20 +static int pmic_arb_get_core_resources_v7(struct platform_device *pdev, + void __iomem *core) +{ + struct spmi_pmic_arb *pmic_arb =3D platform_get_drvdata(pdev); + + pmic_arb->core =3D core; + + pmic_arb->max_periphs =3D PMIC_ARB_MAX_PERIPHS_V7; + + return pmic_arb_get_obsrvr_chnls_v2(pdev); +} + /* * v7 offset per ee and per apid for observer channels and per apid for * read/write channels. @@ -1419,6 +1473,7 @@ pmic_arb_apid_owner_v7(struct spmi_pmic_arb *pmic_arb= , u16 n) =20 static const struct pmic_arb_ver_ops pmic_arb_v1 =3D { .ver_str =3D "v1", + .get_core_resources =3D pmic_arb_get_core_resources_v1, .init_apid =3D pmic_arb_init_apid_v1, .ppid_to_apid =3D pmic_arb_ppid_to_apid_v1, .non_data_cmd =3D pmic_arb_non_data_cmd_v1, @@ -1434,6 +1489,7 @@ static const struct pmic_arb_ver_ops pmic_arb_v1 =3D { =20 static const struct pmic_arb_ver_ops pmic_arb_v2 =3D { .ver_str =3D "v2", + .get_core_resources =3D pmic_arb_get_core_resources_v2, .init_apid =3D pmic_arb_init_apid_v1, .ppid_to_apid =3D pmic_arb_ppid_to_apid_v2, .non_data_cmd =3D pmic_arb_non_data_cmd_v2, @@ -1449,6 +1505,7 @@ static const struct pmic_arb_ver_ops pmic_arb_v2 =3D { =20 static const struct pmic_arb_ver_ops pmic_arb_v3 =3D { .ver_str =3D "v3", + .get_core_resources =3D pmic_arb_get_core_resources_v2, .init_apid =3D pmic_arb_init_apid_v1, .ppid_to_apid =3D pmic_arb_ppid_to_apid_v2, .non_data_cmd =3D pmic_arb_non_data_cmd_v2, @@ -1464,6 +1521,7 @@ static const struct pmic_arb_ver_ops pmic_arb_v3 =3D { =20 static const struct pmic_arb_ver_ops pmic_arb_v5 =3D { .ver_str =3D "v5", + .get_core_resources =3D pmic_arb_get_core_resources_v2, .init_apid =3D pmic_arb_init_apid_v5, .ppid_to_apid =3D pmic_arb_ppid_to_apid_v5, .non_data_cmd =3D pmic_arb_non_data_cmd_v2, @@ -1479,6 +1537,7 @@ static const struct pmic_arb_ver_ops pmic_arb_v5 =3D { =20 static const struct pmic_arb_ver_ops pmic_arb_v7 =3D { .ver_str =3D "v7", + .get_core_resources =3D pmic_arb_get_core_resources_v7, .init_apid =3D pmic_arb_init_apid_v5, .ppid_to_apid =3D pmic_arb_ppid_to_apid_v5, .non_data_cmd =3D pmic_arb_non_data_cmd_v2, @@ -1515,16 +1574,6 @@ static int spmi_pmic_arb_probe(struct platform_devic= e *pdev) pmic_arb =3D spmi_controller_get_drvdata(ctrl); pmic_arb->spmic =3D ctrl; =20 - /* - * Please don't replace this with devm_platform_ioremap_resource() or - * devm_ioremap_resource(). These both result in a call to - * devm_request_mem_region() which prevents multiple mappings of this - * register address range. SoCs with PMIC arbiter v7 may define two - * arbiter devices, for the two physical SPMI interfaces, which share - * some register address ranges (i.e. "core", "obsrvr", and "chnls"). - * Ensure that both devices probe successfully by calling devm_ioremap() - * which does not result in a devm_request_mem_region() call. - */ res =3D platform_get_resource_byname(pdev, IORESOURCE_MEM, "core"); core =3D devm_ioremap(&ctrl->dev, res->start, resource_size(res)); if (!core) @@ -1534,44 +1583,23 @@ static int spmi_pmic_arb_probe(struct platform_devi= ce *pdev) =20 hw_ver =3D readl_relaxed(core + PMIC_ARB_VERSION); =20 - if (hw_ver < PMIC_ARB_VERSION_V2_MIN) { + if (hw_ver < PMIC_ARB_VERSION_V2_MIN) pmic_arb->ver_ops =3D &pmic_arb_v1; - pmic_arb->wr_base =3D core; - pmic_arb->rd_base =3D core; - } else { - pmic_arb->core =3D core; - - if (hw_ver < PMIC_ARB_VERSION_V3_MIN) - pmic_arb->ver_ops =3D &pmic_arb_v2; - else if (hw_ver < PMIC_ARB_VERSION_V5_MIN) - pmic_arb->ver_ops =3D &pmic_arb_v3; - else if (hw_ver < PMIC_ARB_VERSION_V7_MIN) - pmic_arb->ver_ops =3D &pmic_arb_v5; - else - pmic_arb->ver_ops =3D &pmic_arb_v7; - - res =3D platform_get_resource_byname(pdev, IORESOURCE_MEM, - "obsrvr"); - pmic_arb->rd_base =3D devm_ioremap(&ctrl->dev, res->start, - resource_size(res)); - if (!pmic_arb->rd_base) - return -ENOMEM; - - res =3D platform_get_resource_byname(pdev, IORESOURCE_MEM, - "chnls"); - pmic_arb->wr_base =3D devm_ioremap(&ctrl->dev, res->start, - resource_size(res)); - if (!pmic_arb->wr_base) - return -ENOMEM; - } + else if (hw_ver < PMIC_ARB_VERSION_V3_MIN) + pmic_arb->ver_ops =3D &pmic_arb_v2; + else if (hw_ver < PMIC_ARB_VERSION_V5_MIN) + pmic_arb->ver_ops =3D &pmic_arb_v3; + else if (hw_ver < PMIC_ARB_VERSION_V7_MIN) + pmic_arb->ver_ops =3D &pmic_arb_v5; + else + pmic_arb->ver_ops =3D &pmic_arb_v7; =20 dev_info(&ctrl->dev, "PMIC arbiter version %s (0x%x)\n", pmic_arb->ver_ops->ver_str, hw_ver); =20 - if (hw_ver < PMIC_ARB_VERSION_V7_MIN) - pmic_arb->max_periphs =3D PMIC_ARB_MAX_PERIPHS; - else - pmic_arb->max_periphs =3D PMIC_ARB_MAX_PERIPHS_V7; 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charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20240417-spmi-multi-master-support-v10-6-5bc6d322e266@linaro.org> References: <20240417-spmi-multi-master-support-v10-0-5bc6d322e266@linaro.org> In-Reply-To: <20240417-spmi-multi-master-support-v10-0-5bc6d322e266@linaro.org> To: Stephen Boyd , Matthias Brugger , Bjorn Andersson , Konrad Dybcio , Dmitry Baryshkov , Neil Armstrong , AngeloGioacchino Del Regno , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: Srini Kandagatla , Johan Hovold , David Collins , linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-arm-msm@vger.kernel.org, linux-mediatek@lists.infradead.org, devicetree@vger.kernel.org, Abel Vesa X-Mailer: b4 0.13.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=51440; i=abel.vesa@linaro.org; h=from:subject:message-id; bh=Rj711lEjucwGUWeCyDlEvNXQIJ7UbiyrNmXghy+Tqy0=; b=owEBbQKS/ZANAwAKARtfRMkAlRVWAcsmYgBmICqKt9NJbq1gxmPPKvfEqxaumpFotDA92TAIl l2gtRi7RIeJAjMEAAEKAB0WIQRO8+4RTnqPKsqn0bgbX0TJAJUVVgUCZiAqigAKCRAbX0TJAJUV VpH1EADNBu3a+zNxWzzYSgIvv5hQcedgPkbQcQhiRxx3oyUNIvJCcS3iXUEOUp0BkamTNxD/2IC ZJa6qNNIGWAroJ0POLx0LXHKUDZBCa1gkKT1zHG9PKWtlnASXr2Iz+fgcUgk3k/Qd6P/ojHtvVg /Q54DqQQ+SpXrDtOU+vJGtDXPa5w64H3jMA37xwjLDXnRgLbxKtBLJk3tFvCD61j9/QWa1C/rui 3RHcZ6oQCOSxVsHoe7jVrJWWM8UlZPd3wgGlscdqf9TRlpnfA7hOupekeDXuPQNDKJgYWFGj2i1 7uxopAyxLC5K0wMieXB3JZBzCJ2rPGU4zS0xSKWdPeqqx0Es+6E8rmJgqAm49Ei29ipRCaXATc0 76EZ4yeaCp+BuUEswWwvjPdRR+5J/naPssB3jLCHj229WVn614DO6vwp2DynoRx8/VBtFWuK0XB qhVclfdnjE5ywzxKknoo5BC+I2kKJ1PhuYhWSakGbPrkbmr0PBCJeoYIoUR1kKpvDcMGN+LbxnS 7gzgsgSA0MCEhi5uo9AK7oHa/p2EqmrMvOgGqeU01wg7Ev9x4nPYLopJCBzUMhh7/nnqmjvWVG7 pNFcpgOSn2Q7ue02TRB3cOWqExP4h6NwTB+DIU2NTT4GY0oJ4BNCA8e7ECRktElUHi0noOy6L9K Zf5xcMZBRZVkpIg== X-Developer-Key: i=abel.vesa@linaro.org; a=openpgp; fpr=6AFF162D57F4223A8770EF5AF7BF214136F41FAE Introduce the bus object in order to decouple the resources that are bus specific from the arbiter. This way the SPMI controller is registered with the generic framework at a bus level rather than arbiter. This is needed in order to prepare for multi bus support. Reviewed-by: Neil Armstrong Signed-off-by: Abel Vesa --- drivers/spmi/spmi-pmic-arb.c | 659 ++++++++++++++++++++++++---------------= ---- 1 file changed, 374 insertions(+), 285 deletions(-) diff --git a/drivers/spmi/spmi-pmic-arb.c b/drivers/spmi/spmi-pmic-arb.c index db33ca0e11b8..36599e952599 100644 --- a/drivers/spmi/spmi-pmic-arb.c +++ b/drivers/spmi/spmi-pmic-arb.c @@ -13,6 +13,7 @@ #include #include #include +#include #include #include #include @@ -125,61 +126,72 @@ struct apid_data { u8 irq_ee; }; =20 +struct spmi_pmic_arb; + /** - * struct spmi_pmic_arb - SPMI PMIC Arbiter object + * struct spmi_pmic_arb_bus - SPMI PMIC Arbiter Bus object * - * @rd_base: on v1 "core", on v2 "observer" register base off DT. - * @wr_base: on v1 "core", on v2 "chnls" register base off DT. + * @pmic_arb: the SPMI PMIC Arbiter the bus belongs to. + * @domain: irq domain object for PMIC IRQ domain * @intr: address of the SPMI interrupt control registers. * @cnfg: address of the PMIC Arbiter configuration registers. - * @core: core register base for v2 and above only (see above) - * @core_size: core register base size + * @spmic: spmi controller registered for this bus * @lock: lock to synchronize accesses. - * @channel: execution environment channel to use for accesses. - * @irq: PMIC ARB interrupt. - * @ee: the current Execution Environment - * @bus_instance: on v7: 0 =3D primary SPMI bus, 1 =3D secondary SPMI bus - * @min_apid: minimum APID (used for bounding IRQ search) - * @max_apid: maximum APID * @base_apid: on v7: minimum APID associated with the particular SPMI * bus instance * @apid_count: on v5 and v7: number of APIDs associated with the * particular SPMI bus instance * @mapping_table: in-memory copy of PPID -> APID mapping table. * @mapping_table_valid:bitmap containing valid-only periphs - * @domain: irq domain object for PMIC IRQ domain - * @spmic: SPMI controller object - * @ver_ops: version dependent operations. * @ppid_to_apid: in-memory copy of PPID -> APID mapping table. * @last_apid: Highest value APID in use * @apid_data: Table of data for all APIDs - * @max_periphs: Number of elements in apid_data[] + * @min_apid: minimum APID (used for bounding IRQ search) + * @max_apid: maximum APID + * @irq: PMIC ARB interrupt. */ -struct spmi_pmic_arb { - void __iomem *rd_base; - void __iomem *wr_base; +struct spmi_pmic_arb_bus { + struct spmi_pmic_arb *pmic_arb; + struct irq_domain *domain; void __iomem *intr; void __iomem *cnfg; - void __iomem *core; - resource_size_t core_size; + struct spmi_controller *spmic; raw_spinlock_t lock; - u8 channel; - int irq; - u8 ee; - u32 bus_instance; - u16 min_apid; - u16 max_apid; u16 base_apid; int apid_count; u32 *mapping_table; DECLARE_BITMAP(mapping_table_valid, PMIC_ARB_MAX_PERIPHS); - struct irq_domain *domain; - struct spmi_controller *spmic; - const struct pmic_arb_ver_ops *ver_ops; u16 *ppid_to_apid; u16 last_apid; struct apid_data *apid_data; + u16 min_apid; + u16 max_apid; + int irq; +}; + +/** + * struct spmi_pmic_arb - SPMI PMIC Arbiter object + * + * @rd_base: on v1 "core", on v2 "observer" register base off DT. + * @wr_base: on v1 "core", on v2 "chnls" register base off DT. + * @core: core register base for v2 and above only (see above) + * @core_size: core register base size + * @channel: execution environment channel to use for accesses. + * @ee: the current Execution Environment + * @ver_ops: version dependent operations. + * @max_periphs: Number of elements in apid_data[] + * @bus: per arbiter bus instance + */ +struct spmi_pmic_arb { + void __iomem *rd_base; + void __iomem *wr_base; + void __iomem *core; + resource_size_t core_size; + u8 channel; + u8 ee; + const struct pmic_arb_ver_ops *ver_ops; int max_periphs; + struct spmi_pmic_arb_bus *bus; }; =20 /** @@ -208,21 +220,21 @@ struct spmi_pmic_arb { struct pmic_arb_ver_ops { const char *ver_str; int (*get_core_resources)(struct platform_device *pdev, void __iomem *cor= e); - int (*init_apid)(struct spmi_pmic_arb *pmic_arb); - int (*ppid_to_apid)(struct spmi_pmic_arb *pmic_arb, u16 ppid); + int (*init_apid)(struct spmi_pmic_arb_bus *bus); + int (*ppid_to_apid)(struct spmi_pmic_arb_bus *bus, u16 ppid); /* spmi commands (read_cmd, write_cmd, cmd) functionality */ - int (*offset)(struct spmi_pmic_arb *pmic_arb, u8 sid, u16 addr, - enum pmic_arb_channel ch_type); + int (*offset)(struct spmi_pmic_arb_bus *bus, u8 sid, u16 addr, + enum pmic_arb_channel ch_type); u32 (*fmt_cmd)(u8 opc, u8 sid, u16 addr, u8 bc); int (*non_data_cmd)(struct spmi_controller *ctrl, u8 opc, u8 sid); /* Interrupts controller functionality (offset of PIC registers) */ - void __iomem *(*owner_acc_status)(struct spmi_pmic_arb *pmic_arb, u8 m, + void __iomem *(*owner_acc_status)(struct spmi_pmic_arb_bus *bus, u8 m, u16 n); - void __iomem *(*acc_enable)(struct spmi_pmic_arb *pmic_arb, u16 n); - void __iomem *(*irq_status)(struct spmi_pmic_arb *pmic_arb, u16 n); - void __iomem *(*irq_clear)(struct spmi_pmic_arb *pmic_arb, u16 n); + void __iomem *(*acc_enable)(struct spmi_pmic_arb_bus *bus, u16 n); + void __iomem *(*irq_status)(struct spmi_pmic_arb_bus *bus, u16 n); + void __iomem *(*irq_clear)(struct spmi_pmic_arb_bus *bus, u16 n); u32 (*apid_map_offset)(u16 n); - void __iomem *(*apid_owner)(struct spmi_pmic_arb *pmic_arb, u16 n); + void __iomem *(*apid_owner)(struct spmi_pmic_arb_bus *bus, u16 n); }; =20 static inline void pmic_arb_base_write(struct spmi_pmic_arb *pmic_arb, @@ -272,13 +284,14 @@ static int pmic_arb_wait_for_done(struct spmi_control= ler *ctrl, void __iomem *base, u8 sid, u16 addr, enum pmic_arb_channel ch_type) { - struct spmi_pmic_arb *pmic_arb =3D spmi_controller_get_drvdata(ctrl); + struct spmi_pmic_arb_bus *bus =3D spmi_controller_get_drvdata(ctrl); + struct spmi_pmic_arb *pmic_arb =3D bus->pmic_arb; u32 status =3D 0; u32 timeout =3D PMIC_ARB_TIMEOUT_US; u32 offset; int rc; =20 - rc =3D pmic_arb->ver_ops->offset(pmic_arb, sid, addr, ch_type); + rc =3D pmic_arb->ver_ops->offset(bus, sid, addr, ch_type); if (rc < 0) return rc; =20 @@ -321,24 +334,25 @@ static int pmic_arb_wait_for_done(struct spmi_control= ler *ctrl, static int pmic_arb_non_data_cmd_v1(struct spmi_controller *ctrl, u8 opc, u8 sid) { - struct spmi_pmic_arb *pmic_arb =3D spmi_controller_get_drvdata(ctrl); + struct spmi_pmic_arb_bus *bus =3D spmi_controller_get_drvdata(ctrl); + struct spmi_pmic_arb *pmic_arb =3D bus->pmic_arb; unsigned long flags; u32 cmd; int rc; u32 offset; =20 - rc =3D pmic_arb->ver_ops->offset(pmic_arb, sid, 0, PMIC_ARB_CHANNEL_RW); + rc =3D pmic_arb->ver_ops->offset(bus, sid, 0, PMIC_ARB_CHANNEL_RW); if (rc < 0) return rc; =20 offset =3D rc; cmd =3D ((opc | 0x40) << 27) | ((sid & 0xf) << 20); =20 - raw_spin_lock_irqsave(&pmic_arb->lock, flags); + raw_spin_lock_irqsave(&bus->lock, flags); pmic_arb_base_write(pmic_arb, offset + PMIC_ARB_CMD, cmd); rc =3D pmic_arb_wait_for_done(ctrl, pmic_arb->wr_base, sid, 0, PMIC_ARB_CHANNEL_RW); - raw_spin_unlock_irqrestore(&pmic_arb->lock, flags); + raw_spin_unlock_irqrestore(&bus->lock, flags); =20 return rc; } @@ -363,20 +377,21 @@ static int pmic_arb_cmd(struct spmi_controller *ctrl,= u8 opc, u8 sid) return pmic_arb->ver_ops->non_data_cmd(ctrl, opc, sid); } =20 -static int pmic_arb_fmt_read_cmd(struct spmi_pmic_arb *pmic_arb, u8 opc, u= 8 sid, +static int pmic_arb_fmt_read_cmd(struct spmi_pmic_arb_bus *bus, u8 opc, u8= sid, u16 addr, size_t len, u32 *cmd, u32 *offset) { + struct spmi_pmic_arb *pmic_arb =3D bus->pmic_arb; u8 bc =3D len - 1; int rc; =20 - rc =3D pmic_arb->ver_ops->offset(pmic_arb, sid, addr, + rc =3D pmic_arb->ver_ops->offset(bus, sid, addr, PMIC_ARB_CHANNEL_OBS); if (rc < 0) return rc; =20 *offset =3D rc; if (bc >=3D PMIC_ARB_MAX_TRANS_BYTES) { - dev_err(&pmic_arb->spmic->dev, "pmic-arb supports 1..%d bytes per trans,= but:%zu requested", + dev_err(&bus->spmic->dev, "pmic-arb supports 1..%d bytes per trans, but:= %zu requested", PMIC_ARB_MAX_TRANS_BYTES, len); return -EINVAL; } @@ -400,7 +415,8 @@ static int pmic_arb_read_cmd_unlocked(struct spmi_contr= oller *ctrl, u32 cmd, u32 offset, u8 sid, u16 addr, u8 *buf, size_t len) { - struct spmi_pmic_arb *pmic_arb =3D spmi_controller_get_drvdata(ctrl); + struct spmi_pmic_arb_bus *bus =3D spmi_controller_get_drvdata(ctrl); + struct spmi_pmic_arb *pmic_arb =3D bus->pmic_arb; u8 bc =3D len - 1; int rc; =20 @@ -422,38 +438,39 @@ static int pmic_arb_read_cmd_unlocked(struct spmi_con= troller *ctrl, u32 cmd, static int pmic_arb_read_cmd(struct spmi_controller *ctrl, u8 opc, u8 sid, u16 addr, u8 *buf, size_t len) { - struct spmi_pmic_arb *pmic_arb =3D spmi_controller_get_drvdata(ctrl); + struct spmi_pmic_arb_bus *bus =3D spmi_controller_get_drvdata(ctrl); unsigned long flags; u32 cmd, offset; int rc; =20 - rc =3D pmic_arb_fmt_read_cmd(pmic_arb, opc, sid, addr, len, &cmd, + rc =3D pmic_arb_fmt_read_cmd(bus, opc, sid, addr, len, &cmd, &offset); if (rc) return rc; =20 - raw_spin_lock_irqsave(&pmic_arb->lock, flags); + raw_spin_lock_irqsave(&bus->lock, flags); rc =3D pmic_arb_read_cmd_unlocked(ctrl, cmd, offset, sid, addr, buf, len); - raw_spin_unlock_irqrestore(&pmic_arb->lock, flags); + raw_spin_unlock_irqrestore(&bus->lock, flags); =20 return rc; } =20 -static int pmic_arb_fmt_write_cmd(struct spmi_pmic_arb *pmic_arb, u8 opc, +static int pmic_arb_fmt_write_cmd(struct spmi_pmic_arb_bus *bus, u8 opc, u8 sid, u16 addr, size_t len, u32 *cmd, u32 *offset) { + struct spmi_pmic_arb *pmic_arb =3D bus->pmic_arb; u8 bc =3D len - 1; int rc; =20 - rc =3D pmic_arb->ver_ops->offset(pmic_arb, sid, addr, + rc =3D pmic_arb->ver_ops->offset(bus, sid, addr, PMIC_ARB_CHANNEL_RW); if (rc < 0) return rc; =20 *offset =3D rc; if (bc >=3D PMIC_ARB_MAX_TRANS_BYTES) { - dev_err(&pmic_arb->spmic->dev, "pmic-arb supports 1..%d bytes per trans,= but:%zu requested", + dev_err(&bus->spmic->dev, "pmic-arb supports 1..%d bytes per trans, but:= %zu requested", PMIC_ARB_MAX_TRANS_BYTES, len); return -EINVAL; } @@ -479,7 +496,8 @@ static int pmic_arb_write_cmd_unlocked(struct spmi_cont= roller *ctrl, u32 cmd, u32 offset, u8 sid, u16 addr, const u8 *buf, size_t len) { - struct spmi_pmic_arb *pmic_arb =3D spmi_controller_get_drvdata(ctrl); + struct spmi_pmic_arb_bus *bus =3D spmi_controller_get_drvdata(ctrl); + struct spmi_pmic_arb *pmic_arb =3D bus->pmic_arb; u8 bc =3D len - 1; =20 /* Write data to FIFOs */ @@ -498,20 +516,20 @@ static int pmic_arb_write_cmd_unlocked(struct spmi_co= ntroller *ctrl, u32 cmd, static int pmic_arb_write_cmd(struct spmi_controller *ctrl, u8 opc, u8 sid, u16 addr, const u8 *buf, size_t len) { - struct spmi_pmic_arb *pmic_arb =3D spmi_controller_get_drvdata(ctrl); + struct spmi_pmic_arb_bus *bus =3D spmi_controller_get_drvdata(ctrl); unsigned long flags; u32 cmd, offset; int rc; =20 - rc =3D pmic_arb_fmt_write_cmd(pmic_arb, opc, sid, addr, len, &cmd, + rc =3D pmic_arb_fmt_write_cmd(bus, opc, sid, addr, len, &cmd, &offset); if (rc) return rc; =20 - raw_spin_lock_irqsave(&pmic_arb->lock, flags); + raw_spin_lock_irqsave(&bus->lock, flags); rc =3D pmic_arb_write_cmd_unlocked(ctrl, cmd, offset, sid, addr, buf, len); - raw_spin_unlock_irqrestore(&pmic_arb->lock, flags); + raw_spin_unlock_irqrestore(&bus->lock, flags); =20 return rc; } @@ -519,23 +537,23 @@ static int pmic_arb_write_cmd(struct spmi_controller = *ctrl, u8 opc, u8 sid, static int pmic_arb_masked_write(struct spmi_controller *ctrl, u8 sid, u16= addr, const u8 *buf, const u8 *mask, size_t len) { - struct spmi_pmic_arb *pmic_arb =3D spmi_controller_get_drvdata(ctrl); + struct spmi_pmic_arb_bus *bus =3D spmi_controller_get_drvdata(ctrl); u32 read_cmd, read_offset, write_cmd, write_offset; u8 temp[PMIC_ARB_MAX_TRANS_BYTES]; unsigned long flags; int rc, i; =20 - rc =3D pmic_arb_fmt_read_cmd(pmic_arb, SPMI_CMD_EXT_READL, sid, addr, len, + rc =3D pmic_arb_fmt_read_cmd(bus, SPMI_CMD_EXT_READL, sid, addr, len, &read_cmd, &read_offset); if (rc) return rc; =20 - rc =3D pmic_arb_fmt_write_cmd(pmic_arb, SPMI_CMD_EXT_WRITEL, sid, addr, + rc =3D pmic_arb_fmt_write_cmd(bus, SPMI_CMD_EXT_WRITEL, sid, addr, len, &write_cmd, &write_offset); if (rc) return rc; =20 - raw_spin_lock_irqsave(&pmic_arb->lock, flags); + raw_spin_lock_irqsave(&bus->lock, flags); rc =3D pmic_arb_read_cmd_unlocked(ctrl, read_cmd, read_offset, sid, addr, temp, len); if (rc) @@ -547,7 +565,7 @@ static int pmic_arb_masked_write(struct spmi_controller= *ctrl, u8 sid, u16 addr, rc =3D pmic_arb_write_cmd_unlocked(ctrl, write_cmd, write_offset, sid, addr, temp, len); done: - raw_spin_unlock_irqrestore(&pmic_arb->lock, flags); + raw_spin_unlock_irqrestore(&bus->lock, flags); =20 return rc; } @@ -573,25 +591,25 @@ struct spmi_pmic_arb_qpnpint_type { static void qpnpint_spmi_write(struct irq_data *d, u8 reg, void *buf, size_t len) { - struct spmi_pmic_arb *pmic_arb =3D irq_data_get_irq_chip_data(d); + struct spmi_pmic_arb_bus *bus =3D irq_data_get_irq_chip_data(d); u8 sid =3D hwirq_to_sid(d->hwirq); u8 per =3D hwirq_to_per(d->hwirq); =20 - if (pmic_arb_write_cmd(pmic_arb->spmic, SPMI_CMD_EXT_WRITEL, sid, + if (pmic_arb_write_cmd(bus->spmic, SPMI_CMD_EXT_WRITEL, sid, (per << 8) + reg, buf, len)) - dev_err_ratelimited(&pmic_arb->spmic->dev, "failed irqchip transaction o= n %x\n", + dev_err_ratelimited(&bus->spmic->dev, "failed irqchip transaction on %x\= n", d->irq); } =20 static void qpnpint_spmi_read(struct irq_data *d, u8 reg, void *buf, size_= t len) { - struct spmi_pmic_arb *pmic_arb =3D irq_data_get_irq_chip_data(d); + struct spmi_pmic_arb_bus *bus =3D irq_data_get_irq_chip_data(d); u8 sid =3D hwirq_to_sid(d->hwirq); u8 per =3D hwirq_to_per(d->hwirq); =20 - if (pmic_arb_read_cmd(pmic_arb->spmic, SPMI_CMD_EXT_READL, sid, + if (pmic_arb_read_cmd(bus->spmic, SPMI_CMD_EXT_READL, sid, (per << 8) + reg, buf, len)) - dev_err_ratelimited(&pmic_arb->spmic->dev, "failed irqchip transaction o= n %x\n", + dev_err_ratelimited(&bus->spmic->dev, "failed irqchip transaction on %x\= n", d->irq); } =20 @@ -599,47 +617,49 @@ static int qpnpint_spmi_masked_write(struct irq_data = *d, u8 reg, const void *buf, const void *mask, size_t len) { - struct spmi_pmic_arb *pmic_arb =3D irq_data_get_irq_chip_data(d); + struct spmi_pmic_arb_bus *bus =3D irq_data_get_irq_chip_data(d); u8 sid =3D hwirq_to_sid(d->hwirq); u8 per =3D hwirq_to_per(d->hwirq); int rc; =20 - rc =3D pmic_arb_masked_write(pmic_arb->spmic, sid, (per << 8) + reg, buf, + rc =3D pmic_arb_masked_write(bus->spmic, sid, (per << 8) + reg, buf, mask, len); if (rc) - dev_err_ratelimited(&pmic_arb->spmic->dev, "failed irqchip transaction o= n %x rc=3D%d\n", + dev_err_ratelimited(&bus->spmic->dev, "failed irqchip transaction on %x = rc=3D%d\n", d->irq, rc); return rc; } =20 -static void cleanup_irq(struct spmi_pmic_arb *pmic_arb, u16 apid, int id) +static void cleanup_irq(struct spmi_pmic_arb_bus *bus, u16 apid, int id) { - u16 ppid =3D pmic_arb->apid_data[apid].ppid; + struct spmi_pmic_arb *pmic_arb =3D bus->pmic_arb; + u16 ppid =3D bus->apid_data[apid].ppid; u8 sid =3D ppid >> 8; u8 per =3D ppid & 0xFF; u8 irq_mask =3D BIT(id); =20 - dev_err_ratelimited(&pmic_arb->spmic->dev, "%s apid=3D%d sid=3D0x%x per= =3D0x%x irq=3D%d\n", - __func__, apid, sid, per, id); - writel_relaxed(irq_mask, pmic_arb->ver_ops->irq_clear(pmic_arb, apid)); + dev_err_ratelimited(&bus->spmic->dev, "%s apid=3D%d sid=3D0x%x per=3D0x%x= irq=3D%d\n", + __func__, apid, sid, per, id); + writel_relaxed(irq_mask, pmic_arb->ver_ops->irq_clear(bus, apid)); } =20 -static int periph_interrupt(struct spmi_pmic_arb *pmic_arb, u16 apid) +static int periph_interrupt(struct spmi_pmic_arb_bus *bus, u16 apid) { + struct spmi_pmic_arb *pmic_arb =3D bus->pmic_arb; unsigned int irq; u32 status, id; int handled =3D 0; - u8 sid =3D (pmic_arb->apid_data[apid].ppid >> 8) & 0xF; - u8 per =3D pmic_arb->apid_data[apid].ppid & 0xFF; + u8 sid =3D (bus->apid_data[apid].ppid >> 8) & 0xF; + u8 per =3D bus->apid_data[apid].ppid & 0xFF; =20 - status =3D readl_relaxed(pmic_arb->ver_ops->irq_status(pmic_arb, apid)); + status =3D readl_relaxed(pmic_arb->ver_ops->irq_status(bus, apid)); while (status) { id =3D ffs(status) - 1; status &=3D ~BIT(id); - irq =3D irq_find_mapping(pmic_arb->domain, - spec_to_hwirq(sid, per, id, apid)); + irq =3D irq_find_mapping(bus->domain, + spec_to_hwirq(sid, per, id, apid)); if (irq =3D=3D 0) { - cleanup_irq(pmic_arb, apid, id); + cleanup_irq(bus, apid, id); continue; } generic_handle_irq(irq); @@ -651,16 +671,17 @@ static int periph_interrupt(struct spmi_pmic_arb *pmi= c_arb, u16 apid) =20 static void pmic_arb_chained_irq(struct irq_desc *desc) { - struct spmi_pmic_arb *pmic_arb =3D irq_desc_get_handler_data(desc); + struct spmi_pmic_arb_bus *bus =3D irq_desc_get_handler_data(desc); + struct spmi_pmic_arb *pmic_arb =3D bus->pmic_arb; const struct pmic_arb_ver_ops *ver_ops =3D pmic_arb->ver_ops; struct irq_chip *chip =3D irq_desc_get_chip(desc); - int first =3D pmic_arb->min_apid; - int last =3D pmic_arb->max_apid; + int first =3D bus->min_apid; + int last =3D bus->max_apid; /* * acc_offset will be non-zero for the secondary SPMI bus instance on * v7 controllers. */ - int acc_offset =3D pmic_arb->base_apid >> 5; + int acc_offset =3D bus->base_apid >> 5; u8 ee =3D pmic_arb->ee; u32 status, enable, handled =3D 0; int i, id, apid; @@ -671,7 +692,7 @@ static void pmic_arb_chained_irq(struct irq_desc *desc) chained_irq_enter(chip, desc); =20 for (i =3D first >> 5; i <=3D last >> 5; ++i) { - status =3D readl_relaxed(ver_ops->owner_acc_status(pmic_arb, ee, i - acc= _offset)); + status =3D readl_relaxed(ver_ops->owner_acc_status(bus, ee, i - acc_offs= et)); if (status) acc_valid =3D true; =20 @@ -685,9 +706,9 @@ static void pmic_arb_chained_irq(struct irq_desc *desc) continue; } enable =3D readl_relaxed( - ver_ops->acc_enable(pmic_arb, apid)); + ver_ops->acc_enable(bus, apid)); if (enable & SPMI_PIC_ACC_ENABLE_BIT) - if (periph_interrupt(pmic_arb, apid) !=3D 0) + if (periph_interrupt(bus, apid) !=3D 0) handled++; } } @@ -696,19 +717,19 @@ static void pmic_arb_chained_irq(struct irq_desc *des= c) if (!acc_valid) { for (i =3D first; i <=3D last; i++) { /* skip if APPS is not irq owner */ - if (pmic_arb->apid_data[i].irq_ee !=3D pmic_arb->ee) + if (bus->apid_data[i].irq_ee !=3D pmic_arb->ee) continue; =20 irq_status =3D readl_relaxed( - ver_ops->irq_status(pmic_arb, i)); + ver_ops->irq_status(bus, i)); if (irq_status) { enable =3D readl_relaxed( - ver_ops->acc_enable(pmic_arb, i)); + ver_ops->acc_enable(bus, i)); if (enable & SPMI_PIC_ACC_ENABLE_BIT) { - dev_dbg(&pmic_arb->spmic->dev, + dev_dbg(&bus->spmic->dev, "Dispatching IRQ for apid=3D%d status=3D%x\n", i, irq_status); - if (periph_interrupt(pmic_arb, i) !=3D 0) + if (periph_interrupt(bus, i) !=3D 0) handled++; } } @@ -723,12 +744,13 @@ static void pmic_arb_chained_irq(struct irq_desc *des= c) =20 static void qpnpint_irq_ack(struct irq_data *d) { - struct spmi_pmic_arb *pmic_arb =3D irq_data_get_irq_chip_data(d); + struct spmi_pmic_arb_bus *bus =3D irq_data_get_irq_chip_data(d); + struct spmi_pmic_arb *pmic_arb =3D bus->pmic_arb; u8 irq =3D hwirq_to_irq(d->hwirq); u16 apid =3D hwirq_to_apid(d->hwirq); u8 data; =20 - writel_relaxed(BIT(irq), pmic_arb->ver_ops->irq_clear(pmic_arb, apid)); + writel_relaxed(BIT(irq), pmic_arb->ver_ops->irq_clear(bus, apid)); =20 data =3D BIT(irq); qpnpint_spmi_write(d, QPNPINT_REG_LATCHED_CLR, &data, 1); @@ -744,14 +766,15 @@ static void qpnpint_irq_mask(struct irq_data *d) =20 static void qpnpint_irq_unmask(struct irq_data *d) { - struct spmi_pmic_arb *pmic_arb =3D irq_data_get_irq_chip_data(d); + struct spmi_pmic_arb_bus *bus =3D irq_data_get_irq_chip_data(d); + struct spmi_pmic_arb *pmic_arb =3D bus->pmic_arb; const struct pmic_arb_ver_ops *ver_ops =3D pmic_arb->ver_ops; u8 irq =3D hwirq_to_irq(d->hwirq); u16 apid =3D hwirq_to_apid(d->hwirq); u8 buf[2]; =20 writel_relaxed(SPMI_PIC_ACC_ENABLE_BIT, - ver_ops->acc_enable(pmic_arb, apid)); + ver_ops->acc_enable(bus, apid)); =20 qpnpint_spmi_read(d, QPNPINT_REG_EN_SET, &buf[0], 1); if (!(buf[0] & BIT(irq))) { @@ -808,9 +831,9 @@ static int qpnpint_irq_set_type(struct irq_data *d, uns= igned int flow_type) =20 static int qpnpint_irq_set_wake(struct irq_data *d, unsigned int on) { - struct spmi_pmic_arb *pmic_arb =3D irq_data_get_irq_chip_data(d); + struct spmi_pmic_arb_bus *bus =3D irq_data_get_irq_chip_data(d); =20 - return irq_set_irq_wake(pmic_arb->irq, on); + return irq_set_irq_wake(bus->irq, on); } =20 static int qpnpint_get_irqchip_state(struct irq_data *d, @@ -832,17 +855,18 @@ static int qpnpint_get_irqchip_state(struct irq_data = *d, static int qpnpint_irq_domain_activate(struct irq_domain *domain, struct irq_data *d, bool reserve) { - struct spmi_pmic_arb *pmic_arb =3D irq_data_get_irq_chip_data(d); + struct spmi_pmic_arb_bus *bus =3D irq_data_get_irq_chip_data(d); + struct spmi_pmic_arb *pmic_arb =3D bus->pmic_arb; u16 periph =3D hwirq_to_per(d->hwirq); u16 apid =3D hwirq_to_apid(d->hwirq); u16 sid =3D hwirq_to_sid(d->hwirq); u16 irq =3D hwirq_to_irq(d->hwirq); u8 buf; =20 - if (pmic_arb->apid_data[apid].irq_ee !=3D pmic_arb->ee) { - dev_err(&pmic_arb->spmic->dev, "failed to xlate sid =3D %#x, periph =3D = %#x, irq =3D %u: ee=3D%u but owner=3D%u\n", + if (bus->apid_data[apid].irq_ee !=3D pmic_arb->ee) { + dev_err(&bus->spmic->dev, "failed to xlate sid =3D %#x, periph =3D %#x, = irq =3D %u: ee=3D%u but owner=3D%u\n", sid, periph, irq, pmic_arb->ee, - pmic_arb->apid_data[apid].irq_ee); + bus->apid_data[apid].irq_ee); return -ENODEV; } =20 @@ -869,15 +893,16 @@ static int qpnpint_irq_domain_translate(struct irq_do= main *d, unsigned long *out_hwirq, unsigned int *out_type) { - struct spmi_pmic_arb *pmic_arb =3D d->host_data; + struct spmi_pmic_arb_bus *bus =3D d->host_data; + struct spmi_pmic_arb *pmic_arb =3D bus->pmic_arb; u32 *intspec =3D fwspec->param; u16 apid, ppid; int rc; =20 - dev_dbg(&pmic_arb->spmic->dev, "intspec[0] 0x%1x intspec[1] 0x%02x intspe= c[2] 0x%02x\n", + dev_dbg(&bus->spmic->dev, "intspec[0] 0x%1x intspec[1] 0x%02x intspec[2] = 0x%02x\n", intspec[0], intspec[1], intspec[2]); =20 - if (irq_domain_get_of_node(d) !=3D pmic_arb->spmic->dev.of_node) + if (irq_domain_get_of_node(d) !=3D bus->spmic->dev.of_node) return -EINVAL; if (fwspec->param_count !=3D 4) return -EINVAL; @@ -885,37 +910,37 @@ static int qpnpint_irq_domain_translate(struct irq_do= main *d, return -EINVAL; =20 ppid =3D intspec[0] << 8 | intspec[1]; - rc =3D pmic_arb->ver_ops->ppid_to_apid(pmic_arb, ppid); + rc =3D pmic_arb->ver_ops->ppid_to_apid(bus, ppid); if (rc < 0) { - dev_err(&pmic_arb->spmic->dev, "failed to xlate sid =3D %#x, periph =3D = %#x, irq =3D %u rc =3D %d\n", - intspec[0], intspec[1], intspec[2], rc); + dev_err(&bus->spmic->dev, "failed to xlate sid =3D %#x, periph =3D %#x, = irq =3D %u rc =3D %d\n", + intspec[0], intspec[1], intspec[2], rc); return rc; } =20 apid =3D rc; /* Keep track of {max,min}_apid for bounding search during interrupt */ - if (apid > pmic_arb->max_apid) - pmic_arb->max_apid =3D apid; - if (apid < pmic_arb->min_apid) - pmic_arb->min_apid =3D apid; + if (apid > bus->max_apid) + bus->max_apid =3D apid; + if (apid < bus->min_apid) + bus->min_apid =3D apid; =20 *out_hwirq =3D spec_to_hwirq(intspec[0], intspec[1], intspec[2], apid); *out_type =3D intspec[3] & IRQ_TYPE_SENSE_MASK; =20 - dev_dbg(&pmic_arb->spmic->dev, "out_hwirq =3D %lu\n", *out_hwirq); + dev_dbg(&bus->spmic->dev, "out_hwirq =3D %lu\n", *out_hwirq); =20 return 0; } =20 static struct lock_class_key qpnpint_irq_lock_class, qpnpint_irq_request_c= lass; =20 -static void qpnpint_irq_domain_map(struct spmi_pmic_arb *pmic_arb, +static void qpnpint_irq_domain_map(struct spmi_pmic_arb_bus *bus, struct irq_domain *domain, unsigned int virq, irq_hw_number_t hwirq, unsigned int type) { irq_flow_handler_t handler; =20 - dev_dbg(&pmic_arb->spmic->dev, "virq =3D %u, hwirq =3D %lu, type =3D %u\n= ", + dev_dbg(&bus->spmic->dev, "virq =3D %u, hwirq =3D %lu, type =3D %u\n", virq, hwirq, type); =20 if (type & IRQ_TYPE_EDGE_BOTH) @@ -926,7 +951,7 @@ static void qpnpint_irq_domain_map(struct spmi_pmic_arb= *pmic_arb, =20 irq_set_lockdep_class(virq, &qpnpint_irq_lock_class, &qpnpint_irq_request_class); - irq_domain_set_info(domain, virq, hwirq, &pmic_arb_irqchip, pmic_arb, + irq_domain_set_info(domain, virq, hwirq, &pmic_arb_irqchip, bus, handler, NULL, NULL); } =20 @@ -934,7 +959,7 @@ static int qpnpint_irq_domain_alloc(struct irq_domain *= domain, unsigned int virq, unsigned int nr_irqs, void *data) { - struct spmi_pmic_arb *pmic_arb =3D domain->host_data; + struct spmi_pmic_arb_bus *bus =3D domain->host_data; struct irq_fwspec *fwspec =3D data; irq_hw_number_t hwirq; unsigned int type; @@ -945,20 +970,22 @@ static int qpnpint_irq_domain_alloc(struct irq_domain= *domain, return ret; =20 for (i =3D 0; i < nr_irqs; i++) - qpnpint_irq_domain_map(pmic_arb, domain, virq + i, hwirq + i, + qpnpint_irq_domain_map(bus, domain, virq + i, hwirq + i, type); =20 return 0; } =20 -static int pmic_arb_init_apid_min_max(struct spmi_pmic_arb *pmic_arb) +static int pmic_arb_init_apid_min_max(struct spmi_pmic_arb_bus *bus) { + struct spmi_pmic_arb *pmic_arb =3D bus->pmic_arb; + /* * Initialize max_apid/min_apid to the opposite bounds, during * the irq domain translation, we are sure to update these */ - pmic_arb->max_apid =3D 0; - pmic_arb->min_apid =3D pmic_arb->max_periphs - 1; + bus->max_apid =3D 0; + bus->min_apid =3D pmic_arb->max_periphs - 1; =20 return 0; } @@ -976,37 +1003,38 @@ static int pmic_arb_get_core_resources_v1(struct pla= tform_device *pdev, return 0; } =20 -static int pmic_arb_init_apid_v1(struct spmi_pmic_arb *pmic_arb) +static int pmic_arb_init_apid_v1(struct spmi_pmic_arb_bus *bus) { + struct spmi_pmic_arb *pmic_arb =3D bus->pmic_arb; u32 *mapping_table; =20 - mapping_table =3D devm_kcalloc(&pmic_arb->spmic->dev, pmic_arb->max_perip= hs, + mapping_table =3D devm_kcalloc(&bus->spmic->dev, pmic_arb->max_periphs, sizeof(*mapping_table), GFP_KERNEL); if (!mapping_table) return -ENOMEM; =20 - pmic_arb->mapping_table =3D mapping_table; + bus->mapping_table =3D mapping_table; =20 - return pmic_arb_init_apid_min_max(pmic_arb); + return pmic_arb_init_apid_min_max(bus); } =20 -static int pmic_arb_ppid_to_apid_v1(struct spmi_pmic_arb *pmic_arb, u16 pp= id) +static int pmic_arb_ppid_to_apid_v1(struct spmi_pmic_arb_bus *bus, u16 ppi= d) { - u32 *mapping_table =3D pmic_arb->mapping_table; + u32 *mapping_table =3D bus->mapping_table; int index =3D 0, i; u16 apid_valid; u16 apid; u32 data; =20 - apid_valid =3D pmic_arb->ppid_to_apid[ppid]; + apid_valid =3D bus->ppid_to_apid[ppid]; if (apid_valid & PMIC_ARB_APID_VALID) { apid =3D apid_valid & ~PMIC_ARB_APID_VALID; return apid; } =20 for (i =3D 0; i < SPMI_MAPPING_TABLE_TREE_DEPTH; ++i) { - if (!test_and_set_bit(index, pmic_arb->mapping_table_valid)) - mapping_table[index] =3D readl_relaxed(pmic_arb->cnfg + + if (!test_and_set_bit(index, bus->mapping_table_valid)) + mapping_table[index] =3D readl_relaxed(bus->cnfg + SPMI_MAPPING_TABLE_REG(index)); =20 data =3D mapping_table[index]; @@ -1016,9 +1044,9 @@ static int pmic_arb_ppid_to_apid_v1(struct spmi_pmic_= arb *pmic_arb, u16 ppid) index =3D SPMI_MAPPING_BIT_IS_1_RESULT(data); } else { apid =3D SPMI_MAPPING_BIT_IS_1_RESULT(data); - pmic_arb->ppid_to_apid[ppid] + bus->ppid_to_apid[ppid] =3D apid | PMIC_ARB_APID_VALID; - pmic_arb->apid_data[apid].ppid =3D ppid; + bus->apid_data[apid].ppid =3D ppid; return apid; } } else { @@ -1026,9 +1054,9 @@ static int pmic_arb_ppid_to_apid_v1(struct spmi_pmic_= arb *pmic_arb, u16 ppid) index =3D SPMI_MAPPING_BIT_IS_0_RESULT(data); } else { apid =3D SPMI_MAPPING_BIT_IS_0_RESULT(data); - pmic_arb->ppid_to_apid[ppid] + bus->ppid_to_apid[ppid] =3D apid | PMIC_ARB_APID_VALID; - pmic_arb->apid_data[apid].ppid =3D ppid; + bus->apid_data[apid].ppid =3D ppid; return apid; } } @@ -1038,24 +1066,26 @@ static int pmic_arb_ppid_to_apid_v1(struct spmi_pmi= c_arb *pmic_arb, u16 ppid) } =20 /* v1 offset per ee */ -static int pmic_arb_offset_v1(struct spmi_pmic_arb *pmic_arb, u8 sid, u16 = addr, - enum pmic_arb_channel ch_type) +static int pmic_arb_offset_v1(struct spmi_pmic_arb_bus *bus, u8 sid, u16 a= ddr, + enum pmic_arb_channel ch_type) { + struct spmi_pmic_arb *pmic_arb =3D bus->pmic_arb; return 0x800 + 0x80 * pmic_arb->channel; } =20 -static u16 pmic_arb_find_apid(struct spmi_pmic_arb *pmic_arb, u16 ppid) +static u16 pmic_arb_find_apid(struct spmi_pmic_arb_bus *bus, u16 ppid) { - struct apid_data *apidd =3D &pmic_arb->apid_data[pmic_arb->last_apid]; + struct spmi_pmic_arb *pmic_arb =3D bus->pmic_arb; + struct apid_data *apidd =3D &bus->apid_data[bus->last_apid]; u32 regval, offset; u16 id, apid; =20 - for (apid =3D pmic_arb->last_apid; ; apid++, apidd++) { + for (apid =3D bus->last_apid; ; apid++, apidd++) { offset =3D pmic_arb->ver_ops->apid_map_offset(apid); if (offset >=3D pmic_arb->core_size) break; =20 - regval =3D readl_relaxed(pmic_arb->ver_ops->apid_owner(pmic_arb, + regval =3D readl_relaxed(pmic_arb->ver_ops->apid_owner(bus, apid)); apidd->irq_ee =3D SPMI_OWNERSHIP_PERIPH2OWNER(regval); apidd->write_ee =3D apidd->irq_ee; @@ -1065,14 +1095,14 @@ static u16 pmic_arb_find_apid(struct spmi_pmic_arb = *pmic_arb, u16 ppid) continue; =20 id =3D (regval >> 8) & PMIC_ARB_PPID_MASK; - pmic_arb->ppid_to_apid[id] =3D apid | PMIC_ARB_APID_VALID; + bus->ppid_to_apid[id] =3D apid | PMIC_ARB_APID_VALID; apidd->ppid =3D id; if (id =3D=3D ppid) { apid |=3D PMIC_ARB_APID_VALID; break; } } - pmic_arb->last_apid =3D apid & ~PMIC_ARB_APID_VALID; + bus->last_apid =3D apid & ~PMIC_ARB_APID_VALID; =20 return apid; } @@ -1104,21 +1134,22 @@ static int pmic_arb_get_core_resources_v2(struct pl= atform_device *pdev, return pmic_arb_get_obsrvr_chnls_v2(pdev); } =20 -static int pmic_arb_ppid_to_apid_v2(struct spmi_pmic_arb *pmic_arb, u16 pp= id) +static int pmic_arb_ppid_to_apid_v2(struct spmi_pmic_arb_bus *bus, u16 ppi= d) { u16 apid_valid; =20 - apid_valid =3D pmic_arb->ppid_to_apid[ppid]; + apid_valid =3D bus->ppid_to_apid[ppid]; if (!(apid_valid & PMIC_ARB_APID_VALID)) - apid_valid =3D pmic_arb_find_apid(pmic_arb, ppid); + apid_valid =3D pmic_arb_find_apid(bus, ppid); if (!(apid_valid & PMIC_ARB_APID_VALID)) return -ENODEV; =20 return apid_valid & ~PMIC_ARB_APID_VALID; } =20 -static int pmic_arb_read_apid_map_v5(struct spmi_pmic_arb *pmic_arb) +static int pmic_arb_read_apid_map_v5(struct spmi_pmic_arb_bus *bus) { + struct spmi_pmic_arb *pmic_arb =3D bus->pmic_arb; struct apid_data *apidd; struct apid_data *prev_apidd; u16 i, apid, ppid, apid_max; @@ -1140,9 +1171,9 @@ static int pmic_arb_read_apid_map_v5(struct spmi_pmic= _arb *pmic_arb) * where N =3D number of APIDs supported by the primary bus and * M =3D number of APIDs supported by the secondary bus */ - apidd =3D &pmic_arb->apid_data[pmic_arb->base_apid]; - apid_max =3D pmic_arb->base_apid + pmic_arb->apid_count; - for (i =3D pmic_arb->base_apid; i < apid_max; i++, apidd++) { + apidd =3D &bus->apid_data[bus->base_apid]; + apid_max =3D bus->base_apid + bus->apid_count; + for (i =3D bus->base_apid; i < apid_max; i++, apidd++) { offset =3D pmic_arb->ver_ops->apid_map_offset(i); if (offset >=3D pmic_arb->core_size) break; @@ -1153,19 +1184,18 @@ static int pmic_arb_read_apid_map_v5(struct spmi_pm= ic_arb *pmic_arb) ppid =3D (regval >> 8) & PMIC_ARB_PPID_MASK; is_irq_ee =3D PMIC_ARB_CHAN_IS_IRQ_OWNER(regval); =20 - regval =3D readl_relaxed(pmic_arb->ver_ops->apid_owner(pmic_arb, - i)); + regval =3D readl_relaxed(pmic_arb->ver_ops->apid_owner(bus, i)); apidd->write_ee =3D SPMI_OWNERSHIP_PERIPH2OWNER(regval); =20 apidd->irq_ee =3D is_irq_ee ? apidd->write_ee : INVALID_EE; =20 - valid =3D pmic_arb->ppid_to_apid[ppid] & PMIC_ARB_APID_VALID; - apid =3D pmic_arb->ppid_to_apid[ppid] & ~PMIC_ARB_APID_VALID; - prev_apidd =3D &pmic_arb->apid_data[apid]; + valid =3D bus->ppid_to_apid[ppid] & PMIC_ARB_APID_VALID; + apid =3D bus->ppid_to_apid[ppid] & ~PMIC_ARB_APID_VALID; + prev_apidd =3D &bus->apid_data[apid]; =20 if (!valid || apidd->write_ee =3D=3D pmic_arb->ee) { /* First PPID mapping or one for this EE */ - pmic_arb->ppid_to_apid[ppid] =3D i | PMIC_ARB_APID_VALID; + bus->ppid_to_apid[ppid] =3D i | PMIC_ARB_APID_VALID; } else if (valid && is_irq_ee && prev_apidd->write_ee =3D=3D pmic_arb->ee) { /* @@ -1176,42 +1206,43 @@ static int pmic_arb_read_apid_map_v5(struct spmi_pm= ic_arb *pmic_arb) } =20 apidd->ppid =3D ppid; - pmic_arb->last_apid =3D i; + bus->last_apid =3D i; } =20 /* Dump the mapping table for debug purposes. */ - dev_dbg(&pmic_arb->spmic->dev, "PPID APID Write-EE IRQ-EE\n"); + dev_dbg(&bus->spmic->dev, "PPID APID Write-EE IRQ-EE\n"); for (ppid =3D 0; ppid < PMIC_ARB_MAX_PPID; ppid++) { - apid =3D pmic_arb->ppid_to_apid[ppid]; + apid =3D bus->ppid_to_apid[ppid]; if (apid & PMIC_ARB_APID_VALID) { apid &=3D ~PMIC_ARB_APID_VALID; - apidd =3D &pmic_arb->apid_data[apid]; - dev_dbg(&pmic_arb->spmic->dev, "%#03X %3u %2u %2u\n", - ppid, apid, apidd->write_ee, apidd->irq_ee); + apidd =3D &bus->apid_data[apid]; + dev_dbg(&bus->spmic->dev, "%#03X %3u %2u %2u\n", + ppid, apid, apidd->write_ee, apidd->irq_ee); } } =20 return 0; } =20 -static int pmic_arb_ppid_to_apid_v5(struct spmi_pmic_arb *pmic_arb, u16 pp= id) +static int pmic_arb_ppid_to_apid_v5(struct spmi_pmic_arb_bus *bus, u16 ppi= d) { - if (!(pmic_arb->ppid_to_apid[ppid] & PMIC_ARB_APID_VALID)) + if (!(bus->ppid_to_apid[ppid] & PMIC_ARB_APID_VALID)) return -ENODEV; =20 - return pmic_arb->ppid_to_apid[ppid] & ~PMIC_ARB_APID_VALID; + return bus->ppid_to_apid[ppid] & ~PMIC_ARB_APID_VALID; } =20 /* v2 offset per ppid and per ee */ -static int pmic_arb_offset_v2(struct spmi_pmic_arb *pmic_arb, u8 sid, u16 = addr, - enum pmic_arb_channel ch_type) +static int pmic_arb_offset_v2(struct spmi_pmic_arb_bus *bus, u8 sid, u16 a= ddr, + enum pmic_arb_channel ch_type) { + struct spmi_pmic_arb *pmic_arb =3D bus->pmic_arb; u16 apid; u16 ppid; int rc; =20 ppid =3D sid << 8 | ((addr >> 8) & 0xFF); - rc =3D pmic_arb_ppid_to_apid_v2(pmic_arb, ppid); + rc =3D pmic_arb_ppid_to_apid_v2(bus, ppid); if (rc < 0) return rc; =20 @@ -1219,27 +1250,28 @@ static int pmic_arb_offset_v2(struct spmi_pmic_arb = *pmic_arb, u8 sid, u16 addr, return 0x1000 * pmic_arb->ee + 0x8000 * apid; } =20 -static int pmic_arb_init_apid_v5(struct spmi_pmic_arb *pmic_arb) +static int pmic_arb_init_apid_v5(struct spmi_pmic_arb_bus *bus) { + struct spmi_pmic_arb *pmic_arb =3D bus->pmic_arb; int ret; =20 - pmic_arb->base_apid =3D 0; - pmic_arb->apid_count =3D readl_relaxed(pmic_arb->core + PMIC_ARB_FEATURES= ) & - PMIC_ARB_FEATURES_PERIPH_MASK; + bus->base_apid =3D 0; + bus->apid_count =3D readl_relaxed(pmic_arb->core + PMIC_ARB_FEATURES) & + PMIC_ARB_FEATURES_PERIPH_MASK; =20 - if (pmic_arb->base_apid + pmic_arb->apid_count > pmic_arb->max_periphs) { - dev_err(&pmic_arb->spmic->dev, "Unsupported APID count %d detected\n", - pmic_arb->base_apid + pmic_arb->apid_count); + if (bus->base_apid + bus->apid_count > pmic_arb->max_periphs) { + dev_err(&bus->spmic->dev, "Unsupported APID count %d detected\n", + bus->base_apid + bus->apid_count); return -EINVAL; } =20 - ret =3D pmic_arb_init_apid_min_max(pmic_arb); + ret =3D pmic_arb_init_apid_min_max(bus); if (ret) return ret; =20 - ret =3D pmic_arb_read_apid_map_v5(pmic_arb); + ret =3D pmic_arb_read_apid_map_v5(bus); if (ret) { - dev_err(&pmic_arb->spmic->dev, "could not read APID->PPID mapping table,= rc=3D %d\n", + dev_err(&bus->spmic->dev, "could not read APID->PPID mapping table, rc= =3D %d\n", ret); return ret; } @@ -1251,15 +1283,16 @@ static int pmic_arb_init_apid_v5(struct spmi_pmic_a= rb *pmic_arb) * v5 offset per ee and per apid for observer channels and per apid for * read/write channels. */ -static int pmic_arb_offset_v5(struct spmi_pmic_arb *pmic_arb, u8 sid, u16 = addr, - enum pmic_arb_channel ch_type) +static int pmic_arb_offset_v5(struct spmi_pmic_arb_bus *bus, u8 sid, u16 a= ddr, + enum pmic_arb_channel ch_type) { + struct spmi_pmic_arb *pmic_arb =3D bus->pmic_arb; u16 apid; int rc; u32 offset =3D 0; u16 ppid =3D (sid << 8) | (addr >> 8); =20 - rc =3D pmic_arb_ppid_to_apid_v5(pmic_arb, ppid); + rc =3D pmic_arb_ppid_to_apid_v5(bus, ppid); if (rc < 0) return rc; =20 @@ -1269,8 +1302,8 @@ static int pmic_arb_offset_v5(struct spmi_pmic_arb *p= mic_arb, u8 sid, u16 addr, offset =3D 0x10000 * pmic_arb->ee + 0x80 * apid; break; case PMIC_ARB_CHANNEL_RW: - if (pmic_arb->apid_data[apid].write_ee !=3D pmic_arb->ee) { - dev_err(&pmic_arb->spmic->dev, "disallowed SPMI write to sid=3D%u, addr= =3D0x%04X\n", + if (bus->apid_data[apid].write_ee !=3D pmic_arb->ee) { + dev_err(&bus->spmic->dev, "disallowed SPMI write to sid=3D%u, addr=3D0x= %04X\n", sid, addr); return -EPERM; } @@ -1297,15 +1330,16 @@ static int pmic_arb_get_core_resources_v7(struct pl= atform_device *pdev, * v7 offset per ee and per apid for observer channels and per apid for * read/write channels. */ -static int pmic_arb_offset_v7(struct spmi_pmic_arb *pmic_arb, u8 sid, u16 = addr, - enum pmic_arb_channel ch_type) +static int pmic_arb_offset_v7(struct spmi_pmic_arb_bus *bus, u8 sid, u16 a= ddr, + enum pmic_arb_channel ch_type) { + struct spmi_pmic_arb *pmic_arb =3D bus->pmic_arb; u16 apid; int rc; u32 offset =3D 0; u16 ppid =3D (sid << 8) | (addr >> 8); =20 - rc =3D pmic_arb->ver_ops->ppid_to_apid(pmic_arb, ppid); + rc =3D pmic_arb->ver_ops->ppid_to_apid(bus, ppid); if (rc < 0) return rc; =20 @@ -1315,8 +1349,8 @@ static int pmic_arb_offset_v7(struct spmi_pmic_arb *p= mic_arb, u8 sid, u16 addr, offset =3D 0x8000 * pmic_arb->ee + 0x20 * apid; break; case PMIC_ARB_CHANNEL_RW: - if (pmic_arb->apid_data[apid].write_ee !=3D pmic_arb->ee) { - dev_err(&pmic_arb->spmic->dev, "disallowed SPMI write to sid=3D%u, addr= =3D0x%04X\n", + if (bus->apid_data[apid].write_ee !=3D pmic_arb->ee) { + dev_err(&bus->spmic->dev, "disallowed SPMI write to sid=3D%u, addr=3D0x= %04X\n", sid, addr); return -EPERM; } @@ -1338,104 +1372,110 @@ static u32 pmic_arb_fmt_cmd_v2(u8 opc, u8 sid, u1= 6 addr, u8 bc) } =20 static void __iomem * -pmic_arb_owner_acc_status_v1(struct spmi_pmic_arb *pmic_arb, u8 m, u16 n) +pmic_arb_owner_acc_status_v1(struct spmi_pmic_arb_bus *bus, u8 m, u16 n) { - return pmic_arb->intr + 0x20 * m + 0x4 * n; + return bus->intr + 0x20 * m + 0x4 * n; } =20 static void __iomem * -pmic_arb_owner_acc_status_v2(struct spmi_pmic_arb *pmic_arb, u8 m, u16 n) +pmic_arb_owner_acc_status_v2(struct spmi_pmic_arb_bus *bus, u8 m, u16 n) { - return pmic_arb->intr + 0x100000 + 0x1000 * m + 0x4 * n; + return bus->intr + 0x100000 + 0x1000 * m + 0x4 * n; } =20 static void __iomem * -pmic_arb_owner_acc_status_v3(struct spmi_pmic_arb *pmic_arb, u8 m, u16 n) +pmic_arb_owner_acc_status_v3(struct spmi_pmic_arb_bus *bus, u8 m, u16 n) { - return pmic_arb->intr + 0x200000 + 0x1000 * m + 0x4 * n; + return bus->intr + 0x200000 + 0x1000 * m + 0x4 * n; } =20 static void __iomem * -pmic_arb_owner_acc_status_v5(struct spmi_pmic_arb *pmic_arb, u8 m, u16 n) +pmic_arb_owner_acc_status_v5(struct spmi_pmic_arb_bus *bus, u8 m, u16 n) { - return pmic_arb->intr + 0x10000 * m + 0x4 * n; + return bus->intr + 0x10000 * m + 0x4 * n; } =20 static void __iomem * -pmic_arb_owner_acc_status_v7(struct spmi_pmic_arb *pmic_arb, u8 m, u16 n) +pmic_arb_owner_acc_status_v7(struct spmi_pmic_arb_bus *bus, u8 m, u16 n) { - return pmic_arb->intr + 0x1000 * m + 0x4 * n; + return bus->intr + 0x1000 * m + 0x4 * n; } =20 static void __iomem * -pmic_arb_acc_enable_v1(struct spmi_pmic_arb *pmic_arb, u16 n) +pmic_arb_acc_enable_v1(struct spmi_pmic_arb_bus *bus, u16 n) { - return pmic_arb->intr + 0x200 + 0x4 * n; + return bus->intr + 0x200 + 0x4 * n; } =20 static void __iomem * -pmic_arb_acc_enable_v2(struct spmi_pmic_arb *pmic_arb, u16 n) +pmic_arb_acc_enable_v2(struct spmi_pmic_arb_bus *bus, u16 n) { - return pmic_arb->intr + 0x1000 * n; + return bus->intr + 0x1000 * n; } =20 static void __iomem * -pmic_arb_acc_enable_v5(struct spmi_pmic_arb *pmic_arb, u16 n) +pmic_arb_acc_enable_v5(struct spmi_pmic_arb_bus *bus, u16 n) { + struct spmi_pmic_arb *pmic_arb =3D bus->pmic_arb; return pmic_arb->wr_base + 0x100 + 0x10000 * n; } =20 static void __iomem * -pmic_arb_acc_enable_v7(struct spmi_pmic_arb *pmic_arb, u16 n) +pmic_arb_acc_enable_v7(struct spmi_pmic_arb_bus *bus, u16 n) { + struct spmi_pmic_arb *pmic_arb =3D bus->pmic_arb; return pmic_arb->wr_base + 0x100 + 0x1000 * n; } =20 static void __iomem * -pmic_arb_irq_status_v1(struct spmi_pmic_arb *pmic_arb, u16 n) +pmic_arb_irq_status_v1(struct spmi_pmic_arb_bus *bus, u16 n) { - return pmic_arb->intr + 0x600 + 0x4 * n; + return bus->intr + 0x600 + 0x4 * n; } =20 static void __iomem * -pmic_arb_irq_status_v2(struct spmi_pmic_arb *pmic_arb, u16 n) +pmic_arb_irq_status_v2(struct spmi_pmic_arb_bus *bus, u16 n) { - return pmic_arb->intr + 0x4 + 0x1000 * n; + return bus->intr + 0x4 + 0x1000 * n; } =20 static void __iomem * -pmic_arb_irq_status_v5(struct spmi_pmic_arb *pmic_arb, u16 n) +pmic_arb_irq_status_v5(struct spmi_pmic_arb_bus *bus, u16 n) { + struct spmi_pmic_arb *pmic_arb =3D bus->pmic_arb; return pmic_arb->wr_base + 0x104 + 0x10000 * n; } =20 static void __iomem * -pmic_arb_irq_status_v7(struct spmi_pmic_arb *pmic_arb, u16 n) +pmic_arb_irq_status_v7(struct spmi_pmic_arb_bus *bus, u16 n) { + struct spmi_pmic_arb *pmic_arb =3D bus->pmic_arb; return pmic_arb->wr_base + 0x104 + 0x1000 * n; } =20 static void __iomem * -pmic_arb_irq_clear_v1(struct spmi_pmic_arb *pmic_arb, u16 n) +pmic_arb_irq_clear_v1(struct spmi_pmic_arb_bus *bus, u16 n) { - return pmic_arb->intr + 0xA00 + 0x4 * n; + return bus->intr + 0xA00 + 0x4 * n; } =20 static void __iomem * -pmic_arb_irq_clear_v2(struct spmi_pmic_arb *pmic_arb, u16 n) +pmic_arb_irq_clear_v2(struct spmi_pmic_arb_bus *bus, u16 n) { - return pmic_arb->intr + 0x8 + 0x1000 * n; + return bus->intr + 0x8 + 0x1000 * n; } =20 static void __iomem * -pmic_arb_irq_clear_v5(struct spmi_pmic_arb *pmic_arb, u16 n) +pmic_arb_irq_clear_v5(struct spmi_pmic_arb_bus *bus, u16 n) { + struct spmi_pmic_arb *pmic_arb =3D bus->pmic_arb; return pmic_arb->wr_base + 0x108 + 0x10000 * n; } =20 static void __iomem * -pmic_arb_irq_clear_v7(struct spmi_pmic_arb *pmic_arb, u16 n) +pmic_arb_irq_clear_v7(struct spmi_pmic_arb_bus *bus, u16 n) { + struct spmi_pmic_arb *pmic_arb =3D bus->pmic_arb; return pmic_arb->wr_base + 0x108 + 0x1000 * n; } =20 @@ -1455,9 +1495,9 @@ static u32 pmic_arb_apid_map_offset_v7(u16 n) } =20 static void __iomem * -pmic_arb_apid_owner_v2(struct spmi_pmic_arb *pmic_arb, u16 n) +pmic_arb_apid_owner_v2(struct spmi_pmic_arb_bus *bus, u16 n) { - return pmic_arb->cnfg + 0x700 + 0x4 * n; + return bus->cnfg + 0x700 + 0x4 * n; } =20 /* @@ -1466,9 +1506,9 @@ pmic_arb_apid_owner_v2(struct spmi_pmic_arb *pmic_arb= , u16 n) * 0. */ static void __iomem * -pmic_arb_apid_owner_v7(struct spmi_pmic_arb *pmic_arb, u16 n) +pmic_arb_apid_owner_v7(struct spmi_pmic_arb_bus *bus, u16 n) { - return pmic_arb->cnfg + 0x4 * (n - pmic_arb->base_apid); + return bus->cnfg + 0x4 * (n - bus->base_apid); } =20 static const struct pmic_arb_ver_ops pmic_arb_v1 =3D { @@ -1558,29 +1598,121 @@ static const struct irq_domain_ops pmic_arb_irq_do= main_ops =3D { .translate =3D qpnpint_irq_domain_translate, }; =20 +static int spmi_pmic_arb_bus_init(struct platform_device *pdev, + struct device_node *node, + struct spmi_pmic_arb *pmic_arb) +{ + struct spmi_pmic_arb_bus *bus; + struct device *dev =3D &pdev->dev; + struct spmi_controller *ctrl; + void __iomem *intr; + void __iomem *cnfg; + int index, ret; + u32 irq; + + ctrl =3D devm_spmi_controller_alloc(dev, sizeof(*bus)); + if (IS_ERR(ctrl)) + return PTR_ERR(ctrl); + + ctrl->cmd =3D pmic_arb_cmd; + ctrl->read_cmd =3D pmic_arb_read_cmd; + ctrl->write_cmd =3D pmic_arb_write_cmd; + + bus =3D spmi_controller_get_drvdata(ctrl); + + pmic_arb->bus =3D bus; + + raw_spin_lock_init(&bus->lock); + + bus->ppid_to_apid =3D devm_kcalloc(dev, PMIC_ARB_MAX_PPID, + sizeof(*bus->ppid_to_apid), + GFP_KERNEL); + if (!bus->ppid_to_apid) + return -ENOMEM; + + bus->apid_data =3D devm_kcalloc(dev, pmic_arb->max_periphs, + sizeof(*bus->apid_data), + GFP_KERNEL); + if (!bus->apid_data) + return -ENOMEM; + + index =3D of_property_match_string(node, "reg-names", "cnfg"); + if (index < 0) { + dev_err(dev, "cnfg reg region missing"); + return -EINVAL; + } + + cnfg =3D devm_of_iomap(dev, node, index, NULL); + if (IS_ERR(cnfg)) + return PTR_ERR(cnfg); + + index =3D of_property_match_string(node, "reg-names", "intr"); + if (index < 0) { + dev_err(dev, "intr reg region missing"); + return -EINVAL; + } + + intr =3D devm_of_iomap(dev, node, index, NULL); + if (IS_ERR(intr)) + return PTR_ERR(intr); + + irq =3D of_irq_get_byname(node, "periph_irq"); + if (irq < 0) + return irq; + + bus->pmic_arb =3D pmic_arb; + bus->intr =3D intr; + bus->cnfg =3D cnfg; + bus->irq =3D irq; + bus->spmic =3D ctrl; + + ret =3D pmic_arb->ver_ops->init_apid(bus); + if (ret) + return ret; + + dev_dbg(&pdev->dev, "adding irq domain\n"); + + bus->domain =3D irq_domain_add_tree(dev->of_node, + &pmic_arb_irq_domain_ops, bus); + if (!bus->domain) { + dev_err(&pdev->dev, "unable to create irq_domain\n"); + return -ENOMEM; + } + + irq_set_chained_handler_and_data(bus->irq, + pmic_arb_chained_irq, bus); + + ctrl->dev.of_node =3D node; + + ret =3D devm_spmi_controller_add(dev, ctrl); + if (ret) + return ret; + + return 0; +} + static int spmi_pmic_arb_probe(struct platform_device *pdev) { struct spmi_pmic_arb *pmic_arb; - struct spmi_controller *ctrl; + struct device *dev =3D &pdev->dev; struct resource *res; void __iomem *core; u32 channel, ee, hw_ver; int err; =20 - ctrl =3D devm_spmi_controller_alloc(&pdev->dev, sizeof(*pmic_arb)); - if (IS_ERR(ctrl)) - return PTR_ERR(ctrl); - - pmic_arb =3D spmi_controller_get_drvdata(ctrl); - pmic_arb->spmic =3D ctrl; + pmic_arb =3D devm_kzalloc(dev, sizeof(*pmic_arb), GFP_KERNEL); + if (!pmic_arb) + return -ENOMEM; =20 res =3D platform_get_resource_byname(pdev, IORESOURCE_MEM, "core"); - core =3D devm_ioremap(&ctrl->dev, res->start, resource_size(res)); + core =3D devm_ioremap(dev, res->start, resource_size(res)); if (!core) return -ENOMEM; =20 pmic_arb->core_size =3D resource_size(res); =20 + platform_set_drvdata(pdev, pmic_arb); + hw_ver =3D readl_relaxed(core + PMIC_ARB_VERSION); =20 if (hw_ver < PMIC_ARB_VERSION_V2_MIN) @@ -1594,30 +1726,12 @@ static int spmi_pmic_arb_probe(struct platform_devi= ce *pdev) else pmic_arb->ver_ops =3D &pmic_arb_v7; =20 - dev_info(&ctrl->dev, "PMIC arbiter version %s (0x%x)\n", - pmic_arb->ver_ops->ver_str, hw_ver); - err =3D pmic_arb->ver_ops->get_core_resources(pdev, core); if (err) return err; =20 - err =3D pmic_arb->ver_ops->init_apid(pmic_arb); - if (err) - return err; - - res =3D platform_get_resource_byname(pdev, IORESOURCE_MEM, "intr"); - pmic_arb->intr =3D devm_ioremap_resource(&ctrl->dev, res); - if (IS_ERR(pmic_arb->intr)) - return PTR_ERR(pmic_arb->intr); - - res =3D platform_get_resource_byname(pdev, IORESOURCE_MEM, "cnfg"); - pmic_arb->cnfg =3D devm_ioremap_resource(&ctrl->dev, res); - if (IS_ERR(pmic_arb->cnfg)) - return PTR_ERR(pmic_arb->cnfg); - - pmic_arb->irq =3D platform_get_irq_byname(pdev, "periph_irq"); - if (pmic_arb->irq < 0) - return pmic_arb->irq; + dev_info(dev, "PMIC arbiter version %s (0x%x)\n", + pmic_arb->ver_ops->ver_str, hw_ver); =20 err =3D of_property_read_u32(pdev->dev.of_node, "qcom,channel", &channel); if (err) { @@ -1646,42 +1760,17 @@ static int spmi_pmic_arb_probe(struct platform_devi= ce *pdev) =20 pmic_arb->ee =3D ee; =20 - platform_set_drvdata(pdev, ctrl); - raw_spin_lock_init(&pmic_arb->lock); - - ctrl->cmd =3D pmic_arb_cmd; - ctrl->read_cmd =3D pmic_arb_read_cmd; - ctrl->write_cmd =3D pmic_arb_write_cmd; - - dev_dbg(&pdev->dev, "adding irq domain\n"); - pmic_arb->domain =3D irq_domain_add_tree(pdev->dev.of_node, - &pmic_arb_irq_domain_ops, pmic_arb); - if (!pmic_arb->domain) { - dev_err(&pdev->dev, "unable to create irq_domain\n"); - return -ENOMEM; - } - - irq_set_chained_handler_and_data(pmic_arb->irq, pmic_arb_chained_irq, - pmic_arb); - err =3D spmi_controller_add(ctrl); - if (err) - goto err_domain_remove; - - return 0; - -err_domain_remove: - irq_set_chained_handler_and_data(pmic_arb->irq, NULL, NULL); - irq_domain_remove(pmic_arb->domain); - return err; + return spmi_pmic_arb_bus_init(pdev, dev->of_node, pmic_arb); } =20 static void spmi_pmic_arb_remove(struct platform_device *pdev) { - struct spmi_controller *ctrl =3D platform_get_drvdata(pdev); - struct spmi_pmic_arb *pmic_arb =3D spmi_controller_get_drvdata(ctrl); - spmi_controller_remove(ctrl); - irq_set_chained_handler_and_data(pmic_arb->irq, NULL, NULL); - irq_domain_remove(pmic_arb->domain); + struct spmi_pmic_arb *pmic_arb =3D platform_get_drvdata(pdev); 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Wed, 17 Apr 2024 13:01:32 -0700 (PDT) From: Abel Vesa Date: Wed, 17 Apr 2024 23:00:59 +0300 Subject: [PATCH v10 7/7] spmi: pmic-arb: Add multi bus support Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20240417-spmi-multi-master-support-v10-7-5bc6d322e266@linaro.org> References: <20240417-spmi-multi-master-support-v10-0-5bc6d322e266@linaro.org> In-Reply-To: <20240417-spmi-multi-master-support-v10-0-5bc6d322e266@linaro.org> To: Stephen Boyd , Matthias Brugger , Bjorn Andersson , Konrad Dybcio , Dmitry Baryshkov , Neil Armstrong , AngeloGioacchino Del Regno , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: Srini Kandagatla , Johan Hovold , David Collins , linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-arm-msm@vger.kernel.org, linux-mediatek@lists.infradead.org, devicetree@vger.kernel.org, Abel Vesa X-Mailer: b4 0.13.0 X-Developer-Signature: v=1; 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a=openpgp; fpr=6AFF162D57F4223A8770EF5AF7BF214136F41FAE Starting with HW version 7, there are actually two separate buses (with two separate sets of wires). So add support for the second bus. The first platform that needs this support for the second bus is the Qualcomm X1 Elite, so add the compatible for it as well. Reviewed-by: Neil Armstrong Signed-off-by: Abel Vesa --- drivers/spmi/spmi-pmic-arb.c | 138 +++++++++++++++++++++++++++++++++++++--= ---- 1 file changed, 120 insertions(+), 18 deletions(-) diff --git a/drivers/spmi/spmi-pmic-arb.c b/drivers/spmi/spmi-pmic-arb.c index 36599e952599..0a17ff02c827 100644 --- a/drivers/spmi/spmi-pmic-arb.c +++ b/drivers/spmi/spmi-pmic-arb.c @@ -13,6 +13,7 @@ #include #include #include +#include #include #include #include @@ -95,6 +96,8 @@ enum pmic_arb_channel { PMIC_ARB_CHANNEL_OBS, }; =20 +#define PMIC_ARB_MAX_BUSES 2 + /* Maximum number of support PMIC peripherals */ #define PMIC_ARB_MAX_PERIPHS 512 #define PMIC_ARB_MAX_PERIPHS_V7 1024 @@ -149,6 +152,7 @@ struct spmi_pmic_arb; * @min_apid: minimum APID (used for bounding IRQ search) * @max_apid: maximum APID * @irq: PMIC ARB interrupt. + * @id: unique ID of the bus */ struct spmi_pmic_arb_bus { struct spmi_pmic_arb *pmic_arb; @@ -167,6 +171,7 @@ struct spmi_pmic_arb_bus { u16 min_apid; u16 max_apid; int irq; + u8 id; }; =20 /** @@ -180,7 +185,8 @@ struct spmi_pmic_arb_bus { * @ee: the current Execution Environment * @ver_ops: version dependent operations. * @max_periphs: Number of elements in apid_data[] - * @bus: per arbiter bus instance + * @buses: per arbiter buses instances + * @buses_available: number of buses registered */ struct spmi_pmic_arb { void __iomem *rd_base; @@ -191,7 +197,8 @@ struct spmi_pmic_arb { u8 ee; const struct pmic_arb_ver_ops *ver_ops; int max_periphs; - struct spmi_pmic_arb_bus *bus; + struct spmi_pmic_arb_bus *buses[PMIC_ARB_MAX_BUSES]; + int buses_available; }; =20 /** @@ -220,7 +227,7 @@ struct spmi_pmic_arb { struct pmic_arb_ver_ops { const char *ver_str; int (*get_core_resources)(struct platform_device *pdev, void __iomem *cor= e); - int (*init_apid)(struct spmi_pmic_arb_bus *bus); + int (*init_apid)(struct spmi_pmic_arb_bus *bus, int index); int (*ppid_to_apid)(struct spmi_pmic_arb_bus *bus, u16 ppid); /* spmi commands (read_cmd, write_cmd, cmd) functionality */ int (*offset)(struct spmi_pmic_arb_bus *bus, u8 sid, u16 addr, @@ -309,8 +316,8 @@ static int pmic_arb_wait_for_done(struct spmi_controlle= r *ctrl, } =20 if (status & PMIC_ARB_STATUS_FAILURE) { - dev_err(&ctrl->dev, "%s: %#x %#x: transaction failed (%#x)\n", - __func__, sid, addr, status); + dev_err(&ctrl->dev, "%s: %#x %#x: transaction failed (%#x) reg: 0x%x\n= ", + __func__, sid, addr, status, offset); WARN_ON(1); return -EIO; } @@ -326,8 +333,8 @@ static int pmic_arb_wait_for_done(struct spmi_controlle= r *ctrl, udelay(1); } =20 - dev_err(&ctrl->dev, "%s: %#x %#x: timeout, status %#x\n", - __func__, sid, addr, status); + dev_err(&ctrl->dev, "%s: %#x %#x %#x: timeout, status %#x\n", + __func__, bus->id, sid, addr, status); return -ETIMEDOUT; } =20 @@ -1003,11 +1010,17 @@ static int pmic_arb_get_core_resources_v1(struct pl= atform_device *pdev, return 0; } =20 -static int pmic_arb_init_apid_v1(struct spmi_pmic_arb_bus *bus) +static int pmic_arb_init_apid_v1(struct spmi_pmic_arb_bus *bus, int index) { struct spmi_pmic_arb *pmic_arb =3D bus->pmic_arb; u32 *mapping_table; =20 + if (index) { + dev_err(&bus->spmic->dev, "Unsupported buses count %d detected\n", + index); + return -EINVAL; + } + mapping_table =3D devm_kcalloc(&bus->spmic->dev, pmic_arb->max_periphs, sizeof(*mapping_table), GFP_KERNEL); if (!mapping_table) @@ -1250,11 +1263,17 @@ static int pmic_arb_offset_v2(struct spmi_pmic_arb_= bus *bus, u8 sid, u16 addr, return 0x1000 * pmic_arb->ee + 0x8000 * apid; } =20 -static int pmic_arb_init_apid_v5(struct spmi_pmic_arb_bus *bus) +static int pmic_arb_init_apid_v5(struct spmi_pmic_arb_bus *bus, int index) { struct spmi_pmic_arb *pmic_arb =3D bus->pmic_arb; int ret; =20 + if (index) { + dev_err(&bus->spmic->dev, "Unsupported buses count %d detected\n", + index); + return -EINVAL; + } + bus->base_apid =3D 0; bus->apid_count =3D readl_relaxed(pmic_arb->core + PMIC_ARB_FEATURES) & PMIC_ARB_FEATURES_PERIPH_MASK; @@ -1326,6 +1345,50 @@ static int pmic_arb_get_core_resources_v7(struct pla= tform_device *pdev, return pmic_arb_get_obsrvr_chnls_v2(pdev); } =20 +/* + * Only v7 supports 2 buses. Each bus will get a different apid count, read + * from different registers. + */ +static int pmic_arb_init_apid_v7(struct spmi_pmic_arb_bus *bus, int index) +{ + struct spmi_pmic_arb *pmic_arb =3D bus->pmic_arb; + int ret; + + if (index =3D=3D 0) { + bus->base_apid =3D 0; + bus->apid_count =3D readl_relaxed(pmic_arb->core + PMIC_ARB_FEATURES) & + PMIC_ARB_FEATURES_PERIPH_MASK; + } else if (index =3D=3D 1) { + bus->base_apid =3D readl_relaxed(pmic_arb->core + PMIC_ARB_FEATURES) & + PMIC_ARB_FEATURES_PERIPH_MASK; + bus->apid_count =3D readl_relaxed(pmic_arb->core + PMIC_ARB_FEATURES1) & + PMIC_ARB_FEATURES_PERIPH_MASK; + } else { + dev_err(&bus->spmic->dev, "Unsupported buses count %d detected\n", + bus->id); + return -EINVAL; + } + + if (bus->base_apid + bus->apid_count > pmic_arb->max_periphs) { + dev_err(&bus->spmic->dev, "Unsupported APID count %d detected\n", + bus->base_apid + bus->apid_count); + return -EINVAL; + } + + ret =3D pmic_arb_init_apid_min_max(bus); + if (ret) + return ret; + + ret =3D pmic_arb_read_apid_map_v5(bus); + if (ret) { + dev_err(&bus->spmic->dev, "could not read APID->PPID mapping table, rc= =3D %d\n", + ret); + return ret; + } + + return 0; +} + /* * v7 offset per ee and per apid for observer channels and per apid for * read/write channels. @@ -1578,7 +1641,7 @@ static const struct pmic_arb_ver_ops pmic_arb_v5 =3D { static const struct pmic_arb_ver_ops pmic_arb_v7 =3D { .ver_str =3D "v7", .get_core_resources =3D pmic_arb_get_core_resources_v7, - .init_apid =3D pmic_arb_init_apid_v5, + .init_apid =3D pmic_arb_init_apid_v7, .ppid_to_apid =3D pmic_arb_ppid_to_apid_v5, .non_data_cmd =3D pmic_arb_non_data_cmd_v2, .offset =3D pmic_arb_offset_v7, @@ -1602,6 +1665,7 @@ static int spmi_pmic_arb_bus_init(struct platform_dev= ice *pdev, struct device_node *node, struct spmi_pmic_arb *pmic_arb) { + int bus_index =3D pmic_arb->buses_available; struct spmi_pmic_arb_bus *bus; struct device *dev =3D &pdev->dev; struct spmi_controller *ctrl; @@ -1620,7 +1684,7 @@ static int spmi_pmic_arb_bus_init(struct platform_dev= ice *pdev, =20 bus =3D spmi_controller_get_drvdata(ctrl); =20 - pmic_arb->bus =3D bus; + pmic_arb->buses[bus_index] =3D bus; =20 raw_spin_lock_init(&bus->lock); =20 @@ -1665,12 +1729,13 @@ static int spmi_pmic_arb_bus_init(struct platform_d= evice *pdev, bus->cnfg =3D cnfg; bus->irq =3D irq; bus->spmic =3D ctrl; + bus->id =3D bus_index; =20 - ret =3D pmic_arb->ver_ops->init_apid(bus); + ret =3D pmic_arb->ver_ops->init_apid(bus, bus_index); if (ret) return ret; =20 - dev_dbg(&pdev->dev, "adding irq domain\n"); + dev_dbg(&pdev->dev, "adding irq domain for bus %d\n", bus_index); =20 bus->domain =3D irq_domain_add_tree(dev->of_node, &pmic_arb_irq_domain_ops, bus); @@ -1683,14 +1748,53 @@ static int spmi_pmic_arb_bus_init(struct platform_d= evice *pdev, pmic_arb_chained_irq, bus); =20 ctrl->dev.of_node =3D node; + dev_set_name(&ctrl->dev, "spmi-%d", bus_index); =20 ret =3D devm_spmi_controller_add(dev, ctrl); if (ret) return ret; =20 + pmic_arb->buses_available++; + return 0; } =20 +static int spmi_pmic_arb_register_buses(struct spmi_pmic_arb *pmic_arb, + struct platform_device *pdev) +{ + struct device *dev =3D &pdev->dev; + struct device_node *node =3D dev->of_node; + struct device_node *child; + int ret; + + /* legacy mode doesn't provide child node for the bus */ + if (of_device_is_compatible(node, "qcom,spmi-pmic-arb")) + return spmi_pmic_arb_bus_init(pdev, node, pmic_arb); + + for_each_available_child_of_node(node, child) { + if (of_node_name_eq(child, "spmi")) { + ret =3D spmi_pmic_arb_bus_init(pdev, child, pmic_arb); + if (ret) + return ret; + } + } + + return ret; +} + +static void spmi_pmic_arb_deregister_buses(struct spmi_pmic_arb *pmic_arb) +{ + int i; + + for (i =3D 0; i < pmic_arb->buses_available; i++) { + struct spmi_pmic_arb_bus *bus =3D pmic_arb->buses[i]; + + irq_set_chained_handler_and_data(bus->irq, + NULL, NULL); + irq_domain_remove(bus->domain); + } +} + static int spmi_pmic_arb_probe(struct platform_device *pdev) { struct spmi_pmic_arb *pmic_arb; @@ -1760,21 +1864,19 @@ static int spmi_pmic_arb_probe(struct platform_devi= ce *pdev) =20 pmic_arb->ee =3D ee; =20 - return spmi_pmic_arb_bus_init(pdev, dev->of_node, pmic_arb); + return spmi_pmic_arb_register_buses(pmic_arb, pdev); } =20 static void spmi_pmic_arb_remove(struct platform_device *pdev) { struct spmi_pmic_arb *pmic_arb =3D platform_get_drvdata(pdev); - struct spmi_pmic_arb_bus *bus =3D pmic_arb->bus; =20 - irq_set_chained_handler_and_data(bus->irq, - NULL, NULL); - irq_domain_remove(bus->domain); + spmi_pmic_arb_deregister_buses(pmic_arb); } =20 static const struct of_device_id spmi_pmic_arb_match_table[] =3D { { .compatible =3D "qcom,spmi-pmic-arb", }, + { .compatible =3D "qcom,x1e80100-spmi-pmic-arb", }, {}, }; MODULE_DEVICE_TABLE(of, spmi_pmic_arb_match_table); --=20 2.34.1