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Wed, 17 Apr 2024 00:03:15 -0700 (PDT) Received: from [127.0.1.1] ([120.60.54.9]) by smtp.gmail.com with ESMTPSA id ga22-20020a056a00621600b006ecf56cb55fsm10349771pfb.96.2024.04.17.00.03.12 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 17 Apr 2024 00:03:14 -0700 (PDT) From: Manivannan Sadhasivam Date: Wed, 17 Apr 2024 12:32:53 +0530 Subject: [PATCH] PCI: qcom: Switch to devm_clk_bulk_get_all() API to get the clocks from Devicetree Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20240417-pci-qcom-clk-bulk-v1-1-52ca19b3d6b2@linaro.org> X-B4-Tracking: v=1; b=H4sIABx0H2YC/x2MQQ5AMBAAvyJ7tgklob4iDrUWG7S0IRLxd43LJ HOYeSCwFw7QJA94viSIs1HyNAGajZ0YZYgOKlNlVuYV7iR4kNuQ1gX7M6Ko9agrZVgrA7HbPY9 y/8+2e98P++V/rGMAAAA= To: Bjorn Andersson , Konrad Dybcio , Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy=C5=84ski?= , Rob Herring , Bjorn Helgaas Cc: linux-pci@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, Manivannan Sadhasivam X-Mailer: b4 0.12.4 X-Developer-Signature: v=1; a=openpgp-sha256; l=12747; i=manivannan.sadhasivam@linaro.org; h=from:subject:message-id; bh=+Szd0m7hc5ADliFv9J2r/gh6GKw8SfbHVeninK/Duxk=; b=owEBbQGS/pANAwAKAVWfEeb+kc71AcsmYgBmH3Qv25M05uztUbVZD0RxoawN8s9Osy/JH3tpw Hr7KxW7bhiJATMEAAEKAB0WIQRnpUMqgUjL2KRYJ5dVnxHm/pHO9QUCZh90LwAKCRBVnxHm/pHO 9TUdB/0T2Il1+zxUpOwNsMnPickdbfCAfszUY6sSonbPDPJTku6Ili0iSGhjYk5sx6W7GdK4zeJ VUmMTI8MKq8Ftw9IhLpduhKJ3LNagqFNBhhs06BXIhbWAES0OIrS/pV+HId6eqInZ0Yu91ueePP O/g06iNvXuCetW+iRh7fMK6XEldnjk/qJTHJnDZy5EUBlxocAIfN98u7uK7CFF/bUqjBQvVgstc w3P0nMR4mmDPNHdOChWVbEw7BOnq1oJIvpbFvTj5UiEbGensFciZ5fSgKVYmY6gVVUhIVAfi0QX TkyuqjomyHtgpxWUERq7/uVK7/vj2TLH1hl4xF4WcPYcwb0X X-Developer-Key: i=manivannan.sadhasivam@linaro.org; a=openpgp; fpr=C668AEC3C3188E4C611465E7488550E901166008 There is no need for the device drivers to validate the clocks defined in Devicetree. The validation should be performed by the DT schema and the drivers should just get all the clocks from DT. Right now the driver hardcodes the clock info and validates them against DT which is redundant. So use devm_clk_bulk_get_all() that just gets all the clocks defined in DT and get rid of all static clocks info from the driver. This simplifies the driver. Signed-off-by: Manivannan Sadhasivam --- drivers/pci/controller/dwc/pcie-qcom.c | 177 +++++++++++------------------= ---- 1 file changed, 58 insertions(+), 119 deletions(-) diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controlle= r/dwc/pcie-qcom.c index 14772edcf0d3..3d2eeff9a876 100644 --- a/drivers/pci/controller/dwc/pcie-qcom.c +++ b/drivers/pci/controller/dwc/pcie-qcom.c @@ -154,58 +154,56 @@ #define QCOM_PCIE_LINK_SPEED_TO_BW(speed) \ Mbps_to_icc(PCIE_SPEED2MBS_ENC(pcie_link_speed[speed])) =20 -#define QCOM_PCIE_1_0_0_MAX_CLOCKS 4 struct qcom_pcie_resources_1_0_0 { - struct clk_bulk_data clks[QCOM_PCIE_1_0_0_MAX_CLOCKS]; + struct clk_bulk_data *clks; + int num_clks; struct reset_control *core; struct regulator *vdda; }; =20 -#define QCOM_PCIE_2_1_0_MAX_CLOCKS 5 #define QCOM_PCIE_2_1_0_MAX_RESETS 6 #define QCOM_PCIE_2_1_0_MAX_SUPPLY 3 struct qcom_pcie_resources_2_1_0 { - struct clk_bulk_data clks[QCOM_PCIE_2_1_0_MAX_CLOCKS]; + struct clk_bulk_data *clks; + int num_clks; struct reset_control_bulk_data resets[QCOM_PCIE_2_1_0_MAX_RESETS]; int num_resets; struct regulator_bulk_data supplies[QCOM_PCIE_2_1_0_MAX_SUPPLY]; }; =20 -#define QCOM_PCIE_2_3_2_MAX_CLOCKS 4 #define QCOM_PCIE_2_3_2_MAX_SUPPLY 2 struct qcom_pcie_resources_2_3_2 { - struct clk_bulk_data clks[QCOM_PCIE_2_3_2_MAX_CLOCKS]; + struct clk_bulk_data *clks; + int num_clks; struct regulator_bulk_data supplies[QCOM_PCIE_2_3_2_MAX_SUPPLY]; }; =20 -#define QCOM_PCIE_2_3_3_MAX_CLOCKS 5 #define QCOM_PCIE_2_3_3_MAX_RESETS 7 struct qcom_pcie_resources_2_3_3 { - struct clk_bulk_data clks[QCOM_PCIE_2_3_3_MAX_CLOCKS]; + struct clk_bulk_data *clks; + int num_clks; struct reset_control_bulk_data rst[QCOM_PCIE_2_3_3_MAX_RESETS]; }; =20 -#define QCOM_PCIE_2_4_0_MAX_CLOCKS 4 #define QCOM_PCIE_2_4_0_MAX_RESETS 12 struct qcom_pcie_resources_2_4_0 { - struct clk_bulk_data clks[QCOM_PCIE_2_4_0_MAX_CLOCKS]; + struct clk_bulk_data *clks; int num_clks; struct reset_control_bulk_data resets[QCOM_PCIE_2_4_0_MAX_RESETS]; int num_resets; }; =20 -#define QCOM_PCIE_2_7_0_MAX_CLOCKS 15 #define QCOM_PCIE_2_7_0_MAX_SUPPLIES 2 struct qcom_pcie_resources_2_7_0 { - struct clk_bulk_data clks[QCOM_PCIE_2_7_0_MAX_CLOCKS]; + struct clk_bulk_data *clks; int num_clks; struct regulator_bulk_data supplies[QCOM_PCIE_2_7_0_MAX_SUPPLIES]; struct reset_control *rst; }; =20 -#define QCOM_PCIE_2_9_0_MAX_CLOCKS 5 struct qcom_pcie_resources_2_9_0 { - struct clk_bulk_data clks[QCOM_PCIE_2_9_0_MAX_CLOCKS]; + struct clk_bulk_data *clks; + int num_clks; struct reset_control *rst; }; =20 @@ -337,21 +335,11 @@ static int qcom_pcie_get_resources_2_1_0(struct qcom_= pcie *pcie) if (ret) return ret; =20 - res->clks[0].id =3D "iface"; - res->clks[1].id =3D "core"; - res->clks[2].id =3D "phy"; - res->clks[3].id =3D "aux"; - res->clks[4].id =3D "ref"; - - /* iface, core, phy are required */ - ret =3D devm_clk_bulk_get(dev, 3, res->clks); - if (ret < 0) - return ret; - - /* aux, ref are optional */ - ret =3D devm_clk_bulk_get_optional(dev, 2, res->clks + 3); - if (ret < 0) - return ret; + res->num_clks =3D devm_clk_bulk_get_all(dev, &res->clks); + if (res->num_clks < 0) { + dev_err(dev, "Failed to get clocks\n"); + return res->num_clks; + } =20 res->resets[0].id =3D "pci"; res->resets[1].id =3D "axi"; @@ -373,7 +361,7 @@ static void qcom_pcie_deinit_2_1_0(struct qcom_pcie *pc= ie) { struct qcom_pcie_resources_2_1_0 *res =3D &pcie->res.v2_1_0; =20 - clk_bulk_disable_unprepare(ARRAY_SIZE(res->clks), res->clks); + clk_bulk_disable_unprepare(res->num_clks, res->clks); reset_control_bulk_assert(res->num_resets, res->resets); =20 writel(1, pcie->parf + PARF_PHY_CTRL); @@ -425,7 +413,7 @@ static int qcom_pcie_post_init_2_1_0(struct qcom_pcie *= pcie) val &=3D ~PHY_TEST_PWR_DOWN; writel(val, pcie->parf + PARF_PHY_CTRL); =20 - ret =3D clk_bulk_prepare_enable(ARRAY_SIZE(res->clks), res->clks); + ret =3D clk_bulk_prepare_enable(res->num_clks, res->clks); if (ret) return ret; =20 @@ -476,20 +464,16 @@ static int qcom_pcie_get_resources_1_0_0(struct qcom_= pcie *pcie) struct qcom_pcie_resources_1_0_0 *res =3D &pcie->res.v1_0_0; struct dw_pcie *pci =3D pcie->pci; struct device *dev =3D pci->dev; - int ret; =20 res->vdda =3D devm_regulator_get(dev, "vdda"); if (IS_ERR(res->vdda)) return PTR_ERR(res->vdda); =20 - res->clks[0].id =3D "iface"; - res->clks[1].id =3D "aux"; - res->clks[2].id =3D "master_bus"; - res->clks[3].id =3D "slave_bus"; - - ret =3D devm_clk_bulk_get(dev, ARRAY_SIZE(res->clks), res->clks); - if (ret < 0) - return ret; + res->num_clks =3D devm_clk_bulk_get_all(dev, &res->clks); + if (res->num_clks < 0) { + dev_err(dev, "Failed to get clocks\n"); + return res->num_clks; + } =20 res->core =3D devm_reset_control_get_exclusive(dev, "core"); return PTR_ERR_OR_ZERO(res->core); @@ -500,7 +484,7 @@ static void qcom_pcie_deinit_1_0_0(struct qcom_pcie *pc= ie) struct qcom_pcie_resources_1_0_0 *res =3D &pcie->res.v1_0_0; =20 reset_control_assert(res->core); - clk_bulk_disable_unprepare(ARRAY_SIZE(res->clks), res->clks); + clk_bulk_disable_unprepare(res->num_clks, res->clks); regulator_disable(res->vdda); } =20 @@ -517,7 +501,7 @@ static int qcom_pcie_init_1_0_0(struct qcom_pcie *pcie) return ret; } =20 - ret =3D clk_bulk_prepare_enable(ARRAY_SIZE(res->clks), res->clks); + ret =3D clk_bulk_prepare_enable(res->num_clks, res->clks); if (ret) { dev_err(dev, "cannot prepare/enable clocks\n"); goto err_assert_reset; @@ -532,7 +516,7 @@ static int qcom_pcie_init_1_0_0(struct qcom_pcie *pcie) return 0; =20 err_disable_clks: - clk_bulk_disable_unprepare(ARRAY_SIZE(res->clks), res->clks); + clk_bulk_disable_unprepare(res->num_clks, res->clks); err_assert_reset: reset_control_assert(res->core); =20 @@ -580,14 +564,11 @@ static int qcom_pcie_get_resources_2_3_2(struct qcom_= pcie *pcie) if (ret) return ret; =20 - res->clks[0].id =3D "aux"; - res->clks[1].id =3D "cfg"; - res->clks[2].id =3D "bus_master"; - res->clks[3].id =3D "bus_slave"; - - ret =3D devm_clk_bulk_get(dev, ARRAY_SIZE(res->clks), res->clks); - if (ret < 0) - return ret; + res->num_clks =3D devm_clk_bulk_get_all(dev, &res->clks); + if (res->num_clks < 0) { + dev_err(dev, "Failed to get clocks\n"); + return res->num_clks; + } =20 return 0; } @@ -596,7 +577,7 @@ static void qcom_pcie_deinit_2_3_2(struct qcom_pcie *pc= ie) { struct qcom_pcie_resources_2_3_2 *res =3D &pcie->res.v2_3_2; =20 - clk_bulk_disable_unprepare(ARRAY_SIZE(res->clks), res->clks); + clk_bulk_disable_unprepare(res->num_clks, res->clks); regulator_bulk_disable(ARRAY_SIZE(res->supplies), res->supplies); } =20 @@ -613,7 +594,7 @@ static int qcom_pcie_init_2_3_2(struct qcom_pcie *pcie) return ret; } =20 - ret =3D clk_bulk_prepare_enable(ARRAY_SIZE(res->clks), res->clks); + ret =3D clk_bulk_prepare_enable(res->num_clks, res->clks); if (ret) { dev_err(dev, "cannot prepare/enable clocks\n"); regulator_bulk_disable(ARRAY_SIZE(res->supplies), res->supplies); @@ -661,17 +642,11 @@ static int qcom_pcie_get_resources_2_4_0(struct qcom_= pcie *pcie) bool is_ipq =3D of_device_is_compatible(dev->of_node, "qcom,pcie-ipq4019"= ); int ret; =20 - res->clks[0].id =3D "aux"; - res->clks[1].id =3D "master_bus"; - res->clks[2].id =3D "slave_bus"; - res->clks[3].id =3D "iface"; - - /* qcom,pcie-ipq4019 is defined without "iface" */ - res->num_clks =3D is_ipq ? 3 : 4; - - ret =3D devm_clk_bulk_get(dev, res->num_clks, res->clks); - if (ret < 0) - return ret; + res->num_clks =3D devm_clk_bulk_get_all(dev, &res->clks); + if (res->num_clks < 0) { + dev_err(dev, "Failed to get clocks\n"); + return res->num_clks; + } =20 res->resets[0].id =3D "axi_m"; res->resets[1].id =3D "axi_s"; @@ -742,15 +717,11 @@ static int qcom_pcie_get_resources_2_3_3(struct qcom_= pcie *pcie) struct device *dev =3D pci->dev; int ret; =20 - res->clks[0].id =3D "iface"; - res->clks[1].id =3D "axi_m"; - res->clks[2].id =3D "axi_s"; - res->clks[3].id =3D "ahb"; - res->clks[4].id =3D "aux"; - - ret =3D devm_clk_bulk_get(dev, ARRAY_SIZE(res->clks), res->clks); - if (ret < 0) - return ret; + res->num_clks =3D devm_clk_bulk_get_all(dev, &res->clks); + if (res->num_clks < 0) { + dev_err(dev, "Failed to get clocks\n"); + return res->num_clks; + } =20 res->rst[0].id =3D "axi_m"; res->rst[1].id =3D "axi_s"; @@ -771,7 +742,7 @@ static void qcom_pcie_deinit_2_3_3(struct qcom_pcie *pc= ie) { struct qcom_pcie_resources_2_3_3 *res =3D &pcie->res.v2_3_3; =20 - clk_bulk_disable_unprepare(ARRAY_SIZE(res->clks), res->clks); + clk_bulk_disable_unprepare(res->num_clks, res->clks); } =20 static int qcom_pcie_init_2_3_3(struct qcom_pcie *pcie) @@ -801,7 +772,7 @@ static int qcom_pcie_init_2_3_3(struct qcom_pcie *pcie) */ usleep_range(2000, 2500); =20 - ret =3D clk_bulk_prepare_enable(ARRAY_SIZE(res->clks), res->clks); + ret =3D clk_bulk_prepare_enable(res->num_clks, res->clks); if (ret) { dev_err(dev, "cannot prepare/enable clocks\n"); goto err_assert_resets; @@ -862,8 +833,6 @@ static int qcom_pcie_get_resources_2_7_0(struct qcom_pc= ie *pcie) struct qcom_pcie_resources_2_7_0 *res =3D &pcie->res.v2_7_0; struct dw_pcie *pci =3D pcie->pci; struct device *dev =3D pci->dev; - unsigned int num_clks, num_opt_clks; - unsigned int idx; int ret; =20 res->rst =3D devm_reset_control_array_get_exclusive(dev); @@ -877,36 +846,11 @@ static int qcom_pcie_get_resources_2_7_0(struct qcom_= pcie *pcie) if (ret) return ret; =20 - idx =3D 0; - res->clks[idx++].id =3D "aux"; - res->clks[idx++].id =3D "cfg"; - res->clks[idx++].id =3D "bus_master"; - res->clks[idx++].id =3D "bus_slave"; - res->clks[idx++].id =3D "slave_q2a"; - - num_clks =3D idx; - - ret =3D devm_clk_bulk_get(dev, num_clks, res->clks); - if (ret < 0) - return ret; - - res->clks[idx++].id =3D "tbu"; - res->clks[idx++].id =3D "ddrss_sf_tbu"; - res->clks[idx++].id =3D "aggre0"; - res->clks[idx++].id =3D "aggre1"; - res->clks[idx++].id =3D "noc_aggr"; - res->clks[idx++].id =3D "noc_aggr_4"; - res->clks[idx++].id =3D "noc_aggr_south_sf"; - res->clks[idx++].id =3D "cnoc_qx"; - res->clks[idx++].id =3D "sleep"; - res->clks[idx++].id =3D "cnoc_sf_axi"; - - num_opt_clks =3D idx - num_clks; - res->num_clks =3D idx; - - ret =3D devm_clk_bulk_get_optional(dev, num_opt_clks, res->clks + num_clk= s); - if (ret < 0) - return ret; + res->num_clks =3D devm_clk_bulk_get_all(dev, &res->clks); + if (res->num_clks < 0) { + dev_err(dev, "Failed to get clocks\n"); + return res->num_clks; + } =20 return 0; } @@ -1101,17 +1045,12 @@ static int qcom_pcie_get_resources_2_9_0(struct qco= m_pcie *pcie) struct qcom_pcie_resources_2_9_0 *res =3D &pcie->res.v2_9_0; struct dw_pcie *pci =3D pcie->pci; struct device *dev =3D pci->dev; - int ret; - - res->clks[0].id =3D "iface"; - res->clks[1].id =3D "axi_m"; - res->clks[2].id =3D "axi_s"; - res->clks[3].id =3D "axi_bridge"; - res->clks[4].id =3D "rchng"; =20 - ret =3D devm_clk_bulk_get(dev, ARRAY_SIZE(res->clks), res->clks); - if (ret < 0) - return ret; + res->num_clks =3D devm_clk_bulk_get_all(dev, &res->clks); + if (res->num_clks < 0) { + dev_err(dev, "Failed to get clocks\n"); + return res->num_clks; + } =20 res->rst =3D devm_reset_control_array_get_exclusive(dev); if (IS_ERR(res->rst)) @@ -1124,7 +1063,7 @@ static void qcom_pcie_deinit_2_9_0(struct qcom_pcie *= pcie) { struct qcom_pcie_resources_2_9_0 *res =3D &pcie->res.v2_9_0; =20 - clk_bulk_disable_unprepare(ARRAY_SIZE(res->clks), res->clks); + clk_bulk_disable_unprepare(res->num_clks, res->clks); } =20 static int qcom_pcie_init_2_9_0(struct qcom_pcie *pcie) @@ -1153,7 +1092,7 @@ static int qcom_pcie_init_2_9_0(struct qcom_pcie *pci= e) =20 usleep_range(2000, 2500); =20 - return clk_bulk_prepare_enable(ARRAY_SIZE(res->clks), res->clks); + return clk_bulk_prepare_enable(res->num_clks, res->clks); } =20 static int qcom_pcie_post_init_2_9_0(struct qcom_pcie *pcie) --- base-commit: 4cece764965020c22cff7665b18a012006359095 change-id: 20240417-pci-qcom-clk-bulk-389f972ae92a Best regards, --=20 Manivannan Sadhasivam