From nobody Wed May 15 19:50:00 2024 Received: from mx1.tq-group.com (mx1.tq-group.com [93.104.207.81]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E44D113F42D; Wed, 17 Apr 2024 13:44:15 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=93.104.207.81 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1713361459; cv=none; b=K2ZHLpFjkbRJGRW/ind1fe99SOkom/b5Bgdrdf6Lgu9nBRtGT1GjgSZhvBha668DCUvLGHtlSehH7rq9jgwRjgzqzsi18ofBFcamKekTlMzOWPRG+HuUXYsbaLboJxx9A+XANeO+SsIsf7u1NGvq+918i0viylW0jrkL2fHPMyo= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1713361459; c=relaxed/simple; bh=G9CV2IDmvN9SvoNGxvVTVF4YluRtXT0j7nf86rqgr0k=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=IYlPGe/WUKd74mS6vhc3PliBKOcMvjIi4gDcsoPvlsYw3s5E2g75mTFBn0D5sNOaXM1PNRj7aROIOGzdx38ujWDJ5KgjyjqhgU8SR74InX4O1+0vWYyQFo2PDXbB4CIaVt88231df15FMw3iLKPGpsuxwt+aT8wM3mdbKIa+PWM= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=ew.tq-group.com; spf=pass smtp.mailfrom=ew.tq-group.com; dkim=pass (2048-bit key) header.d=tq-group.com header.i=@tq-group.com header.b=LCHFR0oO; dkim=fail (0-bit key) header.d=ew.tq-group.com header.i=@ew.tq-group.com header.b=qrgC8E3C reason="key not found in DNS"; arc=none smtp.client-ip=93.104.207.81 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=ew.tq-group.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=ew.tq-group.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=tq-group.com header.i=@tq-group.com header.b="LCHFR0oO"; dkim=fail reason="key not found in DNS" (0-bit key) header.d=ew.tq-group.com header.i=@ew.tq-group.com header.b="qrgC8E3C" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=tq-group.com; i=@tq-group.com; q=dns/txt; s=key1; t=1713361456; x=1744897456; h=from:date:subject:mime-version:content-transfer-encoding: message-id:references:in-reply-to:to:cc; bh=9ecwfr2jTX8nUYKdYFcFhX7DqDXFj9IkXl4aWoV6EaQ=; b=LCHFR0oOXkfXjvyIgRYA3IC0hKFCXVeEpBdZ0BqZfOIoQI6M5bErpw3i 0TqVlPWC+H/urXObLj3sej3OPIzEQSVznEc6ARyam4xnUn+XYyxNoL+90 nAB/F0GdTih49xeISMTDn+SXpnG3tJWJ27JVHFXY60sxgE/rN5T3NTdoN RZqxlDs58BDEQXAUK0SalcHgWw8SL/adfhlRTMG5n3ClG8dgxBQq1oBOe qzzyFvwvwp27TUsumZDl9vMulqU+PmSUucamD1ni8VZ5aXaUmAIaEgj4d qGOnUWMpN6+yBqGRz/mmcnEIKysxh6skN0ik/GnSLGoKTBQ3FCWjNBj1k w==; X-IronPort-AV: E=Sophos;i="6.07,209,1708383600"; d="scan'208";a="36469973" Received: from vmailcow01.tq-net.de ([10.150.86.48]) by mx1.tq-group.com with ESMTP; 17 Apr 2024 15:44:13 +0200 Received: from [127.0.0.1] (localhost [127.0.0.1]) by localhost (Mailerdaemon) with ESMTPSA id 12DD5173228; Wed, 17 Apr 2024 15:44:09 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ew.tq-group.com; s=dkim; t=1713361449; h=from:subject:date:message-id:to:cc:mime-version:content-type: content-transfer-encoding:in-reply-to:references; bh=9ecwfr2jTX8nUYKdYFcFhX7DqDXFj9IkXl4aWoV6EaQ=; b=qrgC8E3C3KTBohezvOoHHqT3Qt1x6ui2tv4Jk14J71cmnAJtGbN+sDcpt8s8T6nMNdbcBb /+eLef+Z/awypojM8WI0BjG0/06/n++CpFw7B5tJcNBTR3hxGOjP4ccbbWtKoj/rTaUlbw hCp/hW6yA6LwVe5rO0mwd0gynwF+BVsaCJrpKF+GgZpLC5k75xOI44AJA54yIvGHQZFK+R 9zMvY8MZPGnuiWUDStl0QFvxbl7PSZcBt7gSW7c0tJnoM3SodZ9DuamJeeH/7LhmjU5OvL IJR2q9XhUlLSkwzAqzoaWiRG0cIA7N2V167mYsxpiPEEfSzrXpf2ZGWaUQqRvw== From: Gregor Herburger Date: Wed, 17 Apr 2024 15:43:54 +0200 Subject: [PATCH 1/4] can: mcp251xfd: stop timestamp before sending chip to sleep Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20240417-mcp251xfd-gpio-feature-v1-1-bc0c61fd0c80@ew.tq-group.com> References: <20240417-mcp251xfd-gpio-feature-v1-0-bc0c61fd0c80@ew.tq-group.com> In-Reply-To: <20240417-mcp251xfd-gpio-feature-v1-0-bc0c61fd0c80@ew.tq-group.com> To: Marc Kleine-Budde , Manivannan Sadhasivam , Thomas Kopp , Vincent Mailhol , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: linux-can@vger.kernel.org, netdev@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux@ew.tq-group.com, gregor.herburger@ew.tq-group.com, alexander.stein@ew.tq-group.com X-Mailer: b4 0.12.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1713361443; l=1952; i=gregor.herburger@ew.tq-group.com; s=20230829; h=from:subject:message-id; bh=G9CV2IDmvN9SvoNGxvVTVF4YluRtXT0j7nf86rqgr0k=; b=znK0b9++zpEp5xhl44Em7LfvHSw+afplN48+9nNL/VFdVwLVRLhruHxP2dOV4GUowFkbZoSFI yN9mbrW9/AeBpNkjDBXmbsP+9EMZWSgD/0ehRiCiGT8gWF0pkHGATBa X-Developer-Key: i=gregor.herburger@ew.tq-group.com; a=ed25519; pk=+eRxwX7ikXwazcRjlOjj2/tbDmfVZdDLoW+xLZbQ4h4= X-Last-TLS-Session-Version: TLSv1.3 MCP2518FD exits Low-Power Mode (LPM) when CS is asserted. When chip is send to sleep and the timestamp workqueue is not stopped chip is waked by SPI transfer of mcp251xfd_timestamp_read. So before sending chip to sleep stop timestamp otherwise the mcp251xfd_timestamp_read callback would wake chip up. Also there are error paths in mcp251xfd_chip_start where workqueue has not been initialized but mcp251xfd_chip_stop is called. So check for initialized func before canceling delayed_work. Fixes: 55e5b97f003e ("can: mcp25xxfd: add driver for Microchip MCP25xxFD SP= I CAN") Signed-off-by: Gregor Herburger --- drivers/net/can/spi/mcp251xfd/mcp251xfd-core.c | 1 + drivers/net/can/spi/mcp251xfd/mcp251xfd-timestamp.c | 5 ++++- 2 files changed, 5 insertions(+), 1 deletion(-) diff --git a/drivers/net/can/spi/mcp251xfd/mcp251xfd-core.c b/drivers/net/c= an/spi/mcp251xfd/mcp251xfd-core.c index 1d9057dc44f2..eb699288c076 100644 --- a/drivers/net/can/spi/mcp251xfd/mcp251xfd-core.c +++ b/drivers/net/can/spi/mcp251xfd/mcp251xfd-core.c @@ -744,6 +744,7 @@ static void mcp251xfd_chip_stop(struct mcp251xfd_priv *= priv, =20 mcp251xfd_chip_interrupts_disable(priv); mcp251xfd_chip_rx_int_disable(priv); + mcp251xfd_timestamp_stop(priv); mcp251xfd_chip_sleep(priv); } =20 diff --git a/drivers/net/can/spi/mcp251xfd/mcp251xfd-timestamp.c b/drivers/= net/can/spi/mcp251xfd/mcp251xfd-timestamp.c index 712e09186987..537c31890838 100644 --- a/drivers/net/can/spi/mcp251xfd/mcp251xfd-timestamp.c +++ b/drivers/net/can/spi/mcp251xfd/mcp251xfd-timestamp.c @@ -67,5 +67,8 @@ void mcp251xfd_timestamp_init(struct mcp251xfd_priv *priv) =20 void mcp251xfd_timestamp_stop(struct mcp251xfd_priv *priv) { - cancel_delayed_work_sync(&priv->timestamp); + struct work_struct *work =3D &priv->timestamp.work; + + if (work->func) + cancel_delayed_work_sync(&priv->timestamp); } --=20 2.34.1 From nobody Wed May 15 19:50:00 2024 Received: from mx1.tq-group.com (mx1.tq-group.com [93.104.207.81]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D514A140384; Wed, 17 Apr 2024 13:44:18 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=93.104.207.81 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1713361462; cv=none; b=iScoE9b38SXIV4jdeNZ/HC75VdX0rJ6SSfP+WPqiBSPA5MWnMVi2sx3p08a+qYM5+5Tqx72C0k8YrjAe/Y3p1Y/OG5mvwcNUsF2+6TSSuVOPLo4Q13fXXKmHF3ZqMbPEoHS/WT0031iUNJjjcshtOEyRGj3bYSrbWLAmC8I8eJw= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1713361462; c=relaxed/simple; bh=yK+ROtYitetXJ8XItGGO6/66x6yNtq2igZnZMLn+JwQ=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; 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d=ew.tq-group.com; s=dkim; t=1713361454; h=from:subject:date:message-id:to:cc:mime-version:content-type: content-transfer-encoding:in-reply-to:references; bh=CR6cJnQRvZN30ZHhHz6IPksA2Q8whaqadyCrTglEecc=; b=I3j9U7Cc4zIBmBF7fLlz1b5cg9hVllwfbGQZ1JdEuPxrn8Guq7Y+6tcZgbc1+9+8uDf01U XYqBn3wNOOoHXsQJoFIlKNEUsNg/3vBWpr8LXqosVzzcuckW4lohix/whUP0RyxMmc69gR MVO9iOj29liXnxYqNcHqw2i71DAsWN0Eh6YZ/z6fg2WUNaEpj9QQNg6Hm5zn35cED7C+dc vpapbRzqAkpJdG8qJFPnBF4bI9vyZdzW0AY1GG/oT9mlHMrks0JTJhV6LE3jhUnA4EdLcp WjTmUiSQXNgo3MSnnam897b8LcXkfone+ld5PaoD6wBezy49O3E3SxN078VHiA== From: Gregor Herburger Date: Wed, 17 Apr 2024 15:43:55 +0200 Subject: [PATCH 2/4] can: mcp251xfd: mcp251xfd_regmap_crc_write(): workaround for errata 5 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20240417-mcp251xfd-gpio-feature-v1-2-bc0c61fd0c80@ew.tq-group.com> References: <20240417-mcp251xfd-gpio-feature-v1-0-bc0c61fd0c80@ew.tq-group.com> In-Reply-To: <20240417-mcp251xfd-gpio-feature-v1-0-bc0c61fd0c80@ew.tq-group.com> To: Marc Kleine-Budde , Manivannan Sadhasivam , Thomas Kopp , Vincent Mailhol , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: linux-can@vger.kernel.org, netdev@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux@ew.tq-group.com, gregor.herburger@ew.tq-group.com, alexander.stein@ew.tq-group.com X-Mailer: b4 0.12.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1713361443; l=2482; i=gregor.herburger@ew.tq-group.com; s=20230829; h=from:subject:message-id; bh=yK+ROtYitetXJ8XItGGO6/66x6yNtq2igZnZMLn+JwQ=; b=NTlVNUGdN/FgjDQUOEv+ceBRxM5INd2qvI5QU8/MlIO4G4ViHcqs1qHWld/jSxyllh8xHp6QA 5q+iqGB9b+pCkeFCOu/NSdNpG1l85aL6Nw1SNDqHynW0aEFNFRe+EXc X-Developer-Key: i=gregor.herburger@ew.tq-group.com; a=ed25519; pk=+eRxwX7ikXwazcRjlOjj2/tbDmfVZdDLoW+xLZbQ4h4= X-Last-TLS-Session-Version: TLSv1.3 According to Errata DS80000789E 5 writing IOCON register using one SPI write command clears LAT0/LAT1. Errata Fix/Work Around suggests to write registers with single byte write instructions. However, it seems that every write to the second byte causes the overrite of LAT0/LAT1. Never write byte 2 of IOCON register to avoid clearing of LAT0/LAT1. Signed-off-by: Gregor Herburger --- drivers/net/can/spi/mcp251xfd/mcp251xfd-regmap.c | 35 ++++++++++++++++++++= +++- 1 file changed, 34 insertions(+), 1 deletion(-) diff --git a/drivers/net/can/spi/mcp251xfd/mcp251xfd-regmap.c b/drivers/net= /can/spi/mcp251xfd/mcp251xfd-regmap.c index 92b7bc7f14b9..ab4e372baffb 100644 --- a/drivers/net/can/spi/mcp251xfd/mcp251xfd-regmap.c +++ b/drivers/net/can/spi/mcp251xfd/mcp251xfd-regmap.c @@ -229,14 +229,47 @@ mcp251xfd_regmap_crc_gather_write(void *context, return spi_sync_transfer(spi, xfer, ARRAY_SIZE(xfer)); } =20 +static int +mcp251xfd_regmap_crc_write_iocon(void *context, const void *data, size_t c= ount) +{ + const size_t data_offset =3D sizeof(__be16) + + mcp251xfd_regmap_crc.pad_bits / BITS_PER_BYTE; + u16 reg =3D *(u16 *)data; + + /* Never write to bits 16..23 of IOCON register to avoid clearing of LAT0= /LAT1 + * + * According to Errata DS80000789E 5 writing IOCON register using one + * SPI write command clears LAT0/LAT1. + * + * Errata Fix/Work Around suggests to write registers with single byte + * write instructions. However, it seems that the byte at 0xe06(IOCON[23:= 16]) + * is for read-only access and writing to it causes the cleraing of LAT0/= LAT1. + */ + + /* Write IOCON[15:0] */ + mcp251xfd_regmap_crc_gather_write(context, ®, 1, + data + data_offset, 2); + reg +=3D 3; + /* Write IOCON[31:24] */ + mcp251xfd_regmap_crc_gather_write(context, ®, 1, + data + data_offset + 3, 1); + + return 0; +} + static int mcp251xfd_regmap_crc_write(void *context, const void *data, size_t count) { const size_t data_offset =3D sizeof(__be16) + mcp251xfd_regmap_crc.pad_bits / BITS_PER_BYTE; + u16 reg =3D *(u16 *)data; =20 - return mcp251xfd_regmap_crc_gather_write(context, + if (reg =3D=3D MCP251XFD_REG_IOCON) + return mcp251xfd_regmap_crc_write_iocon(context, + data, count); + else + return mcp251xfd_regmap_crc_gather_write(context, data, data_offset, data + data_offset, count - data_offset); --=20 2.34.1 From nobody Wed May 15 19:50:00 2024 Received: from mx1.tq-group.com (mx1.tq-group.com [93.104.207.81]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id F0CA21420D7; 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X-IronPort-AV: E=Sophos;i="6.07,209,1708383600"; d="scan'208";a="36469976" Received: from vmailcow01.tq-net.de ([10.150.86.48]) by mx1.tq-group.com with ESMTP; 17 Apr 2024 15:44:22 +0200 Received: from [127.0.0.1] (localhost [127.0.0.1]) by localhost (Mailerdaemon) with ESMTPSA id 4DE2E173169; Wed, 17 Apr 2024 15:44:18 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ew.tq-group.com; s=dkim; t=1713361458; h=from:subject:date:message-id:to:cc:mime-version:content-type: content-transfer-encoding:in-reply-to:references; bh=cTwHyBVGSzBF5RrV+Hrp9YM0PLGEUzjEGPZAV4aGLek=; b=Q4+k6x7rcegfhs59C7P3fF0opUq6vtUjixcnbfhcrQqWaf9aUKkMGkFHvORv/AmjU3Al1g tDgwRkZq5ekV1isW4a3Qotgw9vIfiONEuok9kW0GhylMnF5KxLvRLyvXxqvqI/59NMlIqu 5ZmqYb4UZuOynOxAWQ35JlGD6taDzVM2WujY0fsCwlqVGeH3s3mE2M1+SF8JJXZbwJ693Y Q5jT9Qo4TfwJ9QoK0Vc3ziHaImyt7CsuaIrRTlLIXHOW0IcXmDpINurLOH7hCgdLpokPwA iGMQcjLWgbKYRS1Z+X+a7JKV12l0PRJBI4J4aHY67wa4Y0/pYXpu5jD9CO1aLg== From: Gregor Herburger Date: Wed, 17 Apr 2024 15:43:56 +0200 Subject: [PATCH 3/4] can: mcp251xfd: add gpio functionality Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20240417-mcp251xfd-gpio-feature-v1-3-bc0c61fd0c80@ew.tq-group.com> References: <20240417-mcp251xfd-gpio-feature-v1-0-bc0c61fd0c80@ew.tq-group.com> In-Reply-To: <20240417-mcp251xfd-gpio-feature-v1-0-bc0c61fd0c80@ew.tq-group.com> To: Marc Kleine-Budde , Manivannan Sadhasivam , Thomas Kopp , Vincent Mailhol , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: linux-can@vger.kernel.org, netdev@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux@ew.tq-group.com, gregor.herburger@ew.tq-group.com, alexander.stein@ew.tq-group.com X-Mailer: b4 0.12.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1713361443; l=8827; i=gregor.herburger@ew.tq-group.com; s=20230829; h=from:subject:message-id; bh=yBJvo9fxw05iYnuFLCi6gZl2hY/U88+2pKil0WBPN14=; b=DSi00dmPgUB6iQeEXw/P/fusAlRMoZMFFi7HuTNcRk8vhnUCn8zItGByADAi8HpPT2v70tmgr 2BGKPvBhdeJCgDhnDoa6dSeCrzkfyh4wl7YHMjvlufG7Cbok/UGNDJL X-Developer-Key: i=gregor.herburger@ew.tq-group.com; a=ed25519; pk=+eRxwX7ikXwazcRjlOjj2/tbDmfVZdDLoW+xLZbQ4h4= X-Last-TLS-Session-Version: TLSv1.3 The mcp251xfd devices allow two pins to be configured as gpio. Add this functionality to driver. Signed-off-by: Gregor Herburger --- drivers/net/can/spi/mcp251xfd/mcp251xfd-core.c | 138 +++++++++++++++++++= +++- drivers/net/can/spi/mcp251xfd/mcp251xfd-regmap.c | 21 +++- drivers/net/can/spi/mcp251xfd/mcp251xfd.h | 4 + 3 files changed, 159 insertions(+), 4 deletions(-) diff --git a/drivers/net/can/spi/mcp251xfd/mcp251xfd-core.c b/drivers/net/c= an/spi/mcp251xfd/mcp251xfd-core.c index eb699288c076..5ba9fd0af4b6 100644 --- a/drivers/net/can/spi/mcp251xfd/mcp251xfd-core.c +++ b/drivers/net/can/spi/mcp251xfd/mcp251xfd-core.c @@ -16,6 +16,7 @@ #include #include #include +#include #include #include #include @@ -366,6 +367,8 @@ static int mcp251xfd_chip_wake(const struct mcp251xfd_p= riv *priv) =20 static inline int mcp251xfd_chip_sleep(const struct mcp251xfd_priv *priv) { + int ret; + if (priv->pll_enable) { u32 osc; int err; @@ -381,7 +384,12 @@ static inline int mcp251xfd_chip_sleep(const struct mc= p251xfd_priv *priv) priv->spi->max_speed_hz =3D priv->spi_max_speed_hz_slow; } =20 - return mcp251xfd_chip_set_mode(priv, MCP251XFD_REG_CON_MODE_SLEEP); + ret =3D mcp251xfd_chip_set_mode(priv, MCP251XFD_REG_CON_MODE_SLEEP); + + regcache_cache_only(priv->map_reg, true); + regcache_mark_dirty(priv->map_reg); + + return ret; } =20 static int mcp251xfd_chip_softreset_do(const struct mcp251xfd_priv *priv) @@ -389,6 +397,8 @@ static int mcp251xfd_chip_softreset_do(const struct mcp= 251xfd_priv *priv) const __be16 cmd =3D mcp251xfd_cmd_reset(); int err; =20 + regcache_cache_only(priv->map_reg, false); + /* The Set Mode and SPI Reset command only works if the * controller is not in Sleep Mode. */ @@ -401,7 +411,12 @@ static int mcp251xfd_chip_softreset_do(const struct mc= p251xfd_priv *priv) return err; =20 /* spi_write_then_read() works with non DMA-safe buffers */ - return spi_write_then_read(priv->spi, &cmd, sizeof(cmd), NULL, 0); + err =3D spi_write_then_read(priv->spi, &cmd, sizeof(cmd), NULL, 0); + if (err) + return err; + + /* After reset restore cached register values to hardware */ + return regcache_sync(priv->map_reg); } =20 static int mcp251xfd_chip_softreset_check(const struct mcp251xfd_priv *pri= v) @@ -1772,6 +1787,119 @@ static int mcp251xfd_register_check_rx_int(struct m= cp251xfd_priv *priv) return 0; } =20 +static const char * const mcp251xfd_gpio_names[] =3D {"GPIO0", "GPIO1"}; + +static int mcp251xfd_gpio_request(struct gpio_chip *chip, unsigned int off= set) +{ + struct mcp251xfd_priv *priv =3D gpiochip_get_data(chip); + u32 pin_mask =3D MCP251XFD_REG_IOCON_PM0 << offset; + + return regmap_update_bits(priv->map_reg, MCP251XFD_REG_IOCON, + pin_mask, pin_mask); +} + +static int mcp251xfd_gpio_get_direction(struct gpio_chip *chip, + unsigned int offset) +{ + struct mcp251xfd_priv *priv =3D gpiochip_get_data(chip); + u32 mask =3D MCP251XFD_REG_IOCON_TRIS0 << offset; + u32 val; + + regmap_read(priv->map_reg, MCP251XFD_REG_IOCON, &val); + + if (mask & val) + return GPIO_LINE_DIRECTION_IN; + + return GPIO_LINE_DIRECTION_OUT; +} + +static int mcp251xfd_gpio_get(struct gpio_chip *chip, unsigned int offset) +{ + struct mcp251xfd_priv *priv =3D gpiochip_get_data(chip); + u32 mask =3D MCP251XFD_REG_IOCON_GPIO0 << offset; + u32 val; + + regcache_drop_region(priv->map_reg, MCP251XFD_REG_IOCON, MCP251XFD_REG_IO= CON); + regmap_read(priv->map_reg, MCP251XFD_REG_IOCON, &val); + + return !!(mask & val); +} + +static int mcp251xfd_gpio_direction_output(struct gpio_chip *chip, + unsigned int offset, int value) +{ + struct mcp251xfd_priv *priv =3D gpiochip_get_data(chip); + u32 dir_mask =3D MCP251XFD_REG_IOCON_TRIS0 << offset; + u32 val_mask =3D MCP251XFD_REG_IOCON_LAT0 << offset; + u32 val; + + if (value) + val =3D val_mask; + else + val =3D 0; + + return regmap_update_bits(priv->map_reg, MCP251XFD_REG_IOCON, + dir_mask | val_mask, val); +} + +static int mcp251xfd_gpio_direction_input(struct gpio_chip *chip, + unsigned int offset) +{ + struct mcp251xfd_priv *priv =3D gpiochip_get_data(chip); + u32 dir_mask =3D MCP251XFD_REG_IOCON_TRIS0 << offset; + + return regmap_update_bits(priv->map_reg, MCP251XFD_REG_IOCON, + dir_mask, dir_mask); +} + +static void mcp251xfd_gpio_set(struct gpio_chip *chip, unsigned int offset, + int value) +{ + struct mcp251xfd_priv *priv =3D gpiochip_get_data(chip); + u32 val_mask =3D MCP251XFD_REG_IOCON_LAT0 << offset; + u32 val; + int ret; + + if (value) + val =3D val_mask; + else + val =3D 0; + + ret =3D regmap_update_bits(priv->map_reg, MCP251XFD_REG_IOCON, + val_mask, val); + if (ret) + dev_warn(&priv->spi->dev, + "Failed to set GPIO %u: %d\n", offset, ret); +} + +static int mcp251fdx_gpio_setup(struct mcp251xfd_priv *priv) +{ + struct gpio_chip *gc =3D &priv->gc; + + if (!device_property_present(&priv->spi->dev, "gpio-controller")) + return 0; + + if (priv->rx_int) + return dev_err_probe(&priv->spi->dev, -EINVAL, + "Can't configure gpio-controller with RX-INT!\n"); + + gc->label =3D dev_name(&priv->spi->dev); + gc->parent =3D &priv->spi->dev; + gc->owner =3D THIS_MODULE; + gc->request =3D mcp251xfd_gpio_request; + gc->get_direction =3D mcp251xfd_gpio_get_direction; + gc->direction_output =3D mcp251xfd_gpio_direction_output; + gc->direction_input =3D mcp251xfd_gpio_direction_input; + gc->get =3D mcp251xfd_gpio_get; + gc->set =3D mcp251xfd_gpio_set; + gc->base =3D -1; + gc->can_sleep =3D true; + gc->ngpio =3D ARRAY_SIZE(mcp251xfd_gpio_names); + gc->names =3D mcp251xfd_gpio_names; + + return devm_gpiochip_add_data(&priv->spi->dev, gc, priv); +} + static int mcp251xfd_register_get_dev_id(const struct mcp251xfd_priv *priv, u32 *dev_= id, u32 *effective_speed_hz_slow, @@ -2142,6 +2270,12 @@ static int mcp251xfd_probe(struct spi_device *spi) if (err) goto out_free_candev; =20 + err =3D mcp251fdx_gpio_setup(priv); + if (err) { + dev_err_probe(&spi->dev, err, "Failed to register gpio-controller.\n"); + goto out_free_candev; + } + err =3D mcp251xfd_register(priv); if (err) { dev_err_probe(&spi->dev, err, "Failed to detect %s.\n", diff --git a/drivers/net/can/spi/mcp251xfd/mcp251xfd-regmap.c b/drivers/net= /can/spi/mcp251xfd/mcp251xfd-regmap.c index ab4e372baffb..868c424f22a4 100644 --- a/drivers/net/can/spi/mcp251xfd/mcp251xfd-regmap.c +++ b/drivers/net/can/spi/mcp251xfd/mcp251xfd-regmap.c @@ -447,6 +447,21 @@ static const struct regmap_access_table mcp251xfd_reg_= table =3D { .n_yes_ranges =3D ARRAY_SIZE(mcp251xfd_reg_table_yes_range), }; =20 +static bool mcp251xfd_volatile_reg(struct device *dev, unsigned int reg) +{ + switch (reg) { + case MCP251XFD_REG_ECCCON: + case MCP251XFD_REG_DEVID: + case MCP251XFD_REG_NBTCFG: + case MCP251XFD_REG_DBTCFG: + case MCP251XFD_REG_TDC: + case MCP251XFD_REG_TSCON: + case MCP251XFD_REG_IOCON: + return false; + } + return true; +} + static const struct regmap_config mcp251xfd_regmap_nocrc =3D { .name =3D "nocrc", .reg_bits =3D 16, @@ -456,7 +471,8 @@ static const struct regmap_config mcp251xfd_regmap_nocr= c =3D { .max_register =3D 0xffc, .wr_table =3D &mcp251xfd_reg_table, .rd_table =3D &mcp251xfd_reg_table, - .cache_type =3D REGCACHE_NONE, + .cache_type =3D REGCACHE_MAPLE, + .volatile_reg =3D mcp251xfd_volatile_reg, .read_flag_mask =3D (__force unsigned long) cpu_to_be16(MCP251XFD_SPI_INSTRUCTION_READ), .write_flag_mask =3D (__force unsigned long) @@ -483,7 +499,8 @@ static const struct regmap_config mcp251xfd_regmap_crc = =3D { .max_register =3D 0xffc, .wr_table =3D &mcp251xfd_reg_table, .rd_table =3D &mcp251xfd_reg_table, - .cache_type =3D REGCACHE_NONE, + .cache_type =3D REGCACHE_MAPLE, + .volatile_reg =3D mcp251xfd_volatile_reg, }; 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X-IronPort-AV: E=Sophos;i="6.07,209,1708383600"; d="scan'208";a="36469982" Received: from vmailcow01.tq-net.de ([10.150.86.48]) by mx1.tq-group.com with ESMTP; 17 Apr 2024 15:44:43 +0200 Received: from [127.0.0.1] (localhost [127.0.0.1]) by localhost (Mailerdaemon) with ESMTPSA id DA06D17306A; Wed, 17 Apr 2024 15:44:22 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ew.tq-group.com; s=dkim; t=1713361479; h=from:subject:date:message-id:to:cc:mime-version:content-type: content-transfer-encoding:in-reply-to:references; bh=b3ELLPN+ySGYaDSAWWGeNI7utIoIFKJYGDkEJ6HDu/A=; b=i/v8b+oaWPEM44e21oTH/NIvw6b+HUaPep4JDDfuY3OOHWq1LyWsdt6GDmGviH3U16vVFf veZrLsGuJKsOrtHefQHh4N7QddNMO/ZwzCt8lG6tiQFuThhrwSBq0HJIxl5LGVfSF4Eu2t +CDcn16CRMQIT3qp5a8yfCyDnHBsihoW3lYj1PjqhhN6O17rT+SZP/AYcIsZoRr6SkbOQ3 XtH4WwQv8vcHcQjG9gdWjJNs5Pu32UKKR1rU8TTI/4KsZCJnlnGA3eTmjfPrYZFTSrl3bx Boci8oKMsw4258wHKhtpZCGsY8lrB+f9y+A5vQs0u+L10L/Y7iB/N1/tpS4GIA== From: Gregor Herburger Date: Wed, 17 Apr 2024 15:43:57 +0200 Subject: [PATCH 4/4] dt-binding: can: mcp251xfd: add gpio-controller property Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20240417-mcp251xfd-gpio-feature-v1-4-bc0c61fd0c80@ew.tq-group.com> References: <20240417-mcp251xfd-gpio-feature-v1-0-bc0c61fd0c80@ew.tq-group.com> In-Reply-To: <20240417-mcp251xfd-gpio-feature-v1-0-bc0c61fd0c80@ew.tq-group.com> To: Marc Kleine-Budde , Manivannan Sadhasivam , Thomas Kopp , Vincent Mailhol , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: linux-can@vger.kernel.org, netdev@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux@ew.tq-group.com, gregor.herburger@ew.tq-group.com, alexander.stein@ew.tq-group.com X-Mailer: b4 0.12.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1713361443; l=827; i=gregor.herburger@ew.tq-group.com; s=20230829; h=from:subject:message-id; bh=NEaYgAWRd6TcMPM/LBwSVWln9/i/3Yena3DmCf4ovYI=; b=/IY1DPKUqbMX8ny61LuUyhOymyEQXILW7azYSjzbg6Yp11Mhehe8Zww4yVU/L4yaoJtCuhWSK A6v1kB+T015ABBOKI3NciM37pAZEDNhSSSyuPzO4kMjeAQzmd3Uo+7j X-Developer-Key: i=gregor.herburger@ew.tq-group.com; a=ed25519; pk=+eRxwX7ikXwazcRjlOjj2/tbDmfVZdDLoW+xLZbQ4h4= X-Last-TLS-Session-Version: TLSv1.3 The mcp251xfd has two pins that can be used as gpio. Add gpio-controller property to binding description. Signed-off-by: Gregor Herburger --- Documentation/devicetree/bindings/net/can/microchip,mcp251xfd.yaml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/net/can/microchip,mcp251xfd.= yaml b/Documentation/devicetree/bindings/net/can/microchip,mcp251xfd.yaml index 2a98b26630cb..e8a3ad4b1231 100644 --- a/Documentation/devicetree/bindings/net/can/microchip,mcp251xfd.yaml +++ b/Documentation/devicetree/bindings/net/can/microchip,mcp251xfd.yaml @@ -49,6 +49,8 @@ properties: Must be half or less of "clocks" frequency. maximum: 20000000 =20 + gpio-controller: true + required: - compatible - reg --=20 2.34.1