From nobody Fri May 17 07:07:48 2024 Received: from fllv0015.ext.ti.com (fllv0015.ext.ti.com [198.47.19.141]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 17B0112D1F6; Tue, 16 Apr 2024 22:17:08 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.47.19.141 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1713305830; cv=none; b=tW+v363Z/vw0TYWWM4X6ATzP89THEjgVu1RTxwpxWAJeRX48OnlMvQuB5quXwEPu48IdN3G6WH4dzCptWaFsWOo8ZiM+sR0pEeZ+HM7AAKzalVQnHPWLzfn1ctrmeJFbiSru5SnaVk4fyt/IkqxHfFUKsvPdr8bqvTxWBdVMCa4= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1713305830; c=relaxed/simple; bh=jUvaW60+DtV8F1+6wh7ShTId7kTL/aiUDITODWsceFQ=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=MGhm8TPC/3cHZ9THQ/8VbJ3E4tdPvAqGwfTBsuDYnNGCS6Hnd9YN0c+lKe4YTwHZMNGfCg59cvPiUZz3YIv8KjXmZHQqe1cHakRGbnvcYaelVB3ourmxL6aITLdvfow5cgfEUG2JgrzFYQtvs9qdIATojTGGNia2ATFYXWg5Vjo= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com; spf=pass smtp.mailfrom=ti.com; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b=uk0yPksH; arc=none smtp.client-ip=198.47.19.141 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=ti.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b="uk0yPksH" Received: from lelv0266.itg.ti.com ([10.180.67.225]) by fllv0015.ext.ti.com (8.15.2/8.15.2) with ESMTP id 43GMGmCp005866; Tue, 16 Apr 2024 17:16:49 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1713305809; bh=WFMeOU0m4ToBWRhRl3Xmgk21SCQyCS9G5xDQiDvZXps=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=uk0yPksHuYS2uauSm/JMuW2MRfxWoeBWKwr95pQFD4iTxMUWGmYh+/QKh2cQqvqv8 VY7w7vSary3hgYBo5rtJx7Uxb9c58X+0ICBPgC9eVyLX6D727aV4hUo+2qYDjS6mQr uMhFyxw23HaZI4VuNu8x1Fw9S/0ElBIOpzNcWhNA= Received: from DFLE115.ent.ti.com (dfle115.ent.ti.com [10.64.6.36]) by lelv0266.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 43GMGmQ3033113 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Tue, 16 Apr 2024 17:16:48 -0500 Received: from DFLE101.ent.ti.com (10.64.6.22) by DFLE115.ent.ti.com (10.64.6.36) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23; Tue, 16 Apr 2024 17:16:48 -0500 Received: from lelvsmtp5.itg.ti.com (10.180.75.250) by DFLE101.ent.ti.com (10.64.6.22) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23 via Frontend Transport; Tue, 16 Apr 2024 17:16:48 -0500 Received: from judy-hp.dhcp.ti.com (judy-hp.dhcp.ti.com [128.247.81.105]) by lelvsmtp5.itg.ti.com (8.15.2/8.15.2) with ESMTP id 43GMGmSl102285; Tue, 16 Apr 2024 17:16:48 -0500 From: Judith Mendez To: Rob Herring , Krzysztof Kozlowski , Catalin Marinas , Will Deacon CC: Vignesh Raghavendra , Conor Dooley , , , , Bhavya Kapoor , Dasnavis Sabiya Subject: [PATCH v2 1/6] arm64: dts: ti: k3-am65-main: Update sdhci properties Date: Tue, 16 Apr 2024 17:16:43 -0500 Message-ID: <20240416221648.3522201-2-jm@ti.com> X-Mailer: git-send-email 2.43.2 In-Reply-To: <20240416221648.3522201-1-jm@ti.com> References: <20240416221648.3522201-1-jm@ti.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Content-Type: text/plain; charset="utf-8" Update otap-del-sel properties as per datasheet [0]. Add missing clkbuf-sel and itap-del-sel values also as per datasheet [0]. Move clkbuf-sel and ti,trm-icp above the otap-del-sel properties so the sdhci nodes could be more uniform across platforms. [0] https://www.ti.com/lit/ds/symlink/am6548.pdf Fixes: eac99d38f861 ("arm64: dts: ti: k3-am654-main: Update otap-del-sel va= lues") Fixes: d7600d070fb0 ("arm64: dts: ti: k3-am65-main: Add support for sdhci1") Signed-off-by: Judith Mendez --- Changes since v1: - no change --- arch/arm64/boot/dts/ti/k3-am65-main.dtsi | 17 +++++++++++------ 1 file changed, 11 insertions(+), 6 deletions(-) diff --git a/arch/arm64/boot/dts/ti/k3-am65-main.dtsi b/arch/arm64/boot/dts= /ti/k3-am65-main.dtsi index 670557c89f756..0803a8b9bfe84 100644 --- a/arch/arm64/boot/dts/ti/k3-am65-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am65-main.dtsi @@ -435,6 +435,8 @@ sdhci0: mmc@4f80000 { interrupts =3D ; mmc-ddr-1_8v; mmc-hs200-1_8v; + ti,clkbuf-sel =3D <0x7>; + ti,trm-icp =3D <0x8>; ti,otap-del-sel-legacy =3D <0x0>; ti,otap-del-sel-mmc-hs =3D <0x0>; ti,otap-del-sel-sd-hs =3D <0x0>; @@ -445,8 +447,7 @@ sdhci0: mmc@4f80000 { ti,otap-del-sel-ddr50 =3D <0x5>; ti,otap-del-sel-ddr52 =3D <0x5>; ti,otap-del-sel-hs200 =3D <0x5>; - ti,otap-del-sel-hs400 =3D <0x0>; - ti,trm-icp =3D <0x8>; + ti,itap-del-sel-ddr52 =3D <0x0>; dma-coherent; status =3D "disabled"; }; @@ -458,18 +459,22 @@ sdhci1: mmc@4fa0000 { clocks =3D <&k3_clks 48 0>, <&k3_clks 48 1>; clock-names =3D "clk_ahb", "clk_xin"; interrupts =3D ; + ti,clkbuf-sel =3D <0x7>; + ti,trm-icp =3D <0x8>; ti,otap-del-sel-legacy =3D <0x0>; ti,otap-del-sel-mmc-hs =3D <0x0>; ti,otap-del-sel-sd-hs =3D <0x0>; - ti,otap-del-sel-sdr12 =3D <0x0>; - ti,otap-del-sel-sdr25 =3D <0x0>; + ti,otap-del-sel-sdr12 =3D <0xf>; + ti,otap-del-sel-sdr25 =3D <0xf>; ti,otap-del-sel-sdr50 =3D <0x8>; ti,otap-del-sel-sdr104 =3D <0x7>; ti,otap-del-sel-ddr50 =3D <0x4>; ti,otap-del-sel-ddr52 =3D <0x4>; ti,otap-del-sel-hs200 =3D <0x7>; - ti,clkbuf-sel =3D <0x7>; - ti,trm-icp =3D <0x8>; + ti,itap-del-sel-legacy =3D <0xa>; + ti,itap-del-sel-sd-hs =3D <0x1>; + ti,itap-del-sel-sdr12 =3D <0xa>; + ti,itap-del-sel-sdr25 =3D <0x1>; dma-coherent; status =3D "disabled"; }; --=20 2.43.2 From nobody Fri May 17 07:07:48 2024 Received: from fllv0016.ext.ti.com (fllv0016.ext.ti.com [198.47.19.142]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 5218F84E01; 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charset="utf-8" On AM65x platform, sdhci0 is for eMMC and sdhci1 is for SD. Remove the properties that are not applicable for each device. Fixes: eac99d38f861 ("arm64: dts: ti: k3-am654-main: Update otap-del-sel va= lues") Fixes: d7600d070fb0 ("arm64: dts: ti: k3-am65-main: Add support for sdhci1") Signed-off-by: Judith Mendez --- Changes since v1: - no change --- arch/arm64/boot/dts/ti/k3-am65-main.dtsi | 9 --------- 1 file changed, 9 deletions(-) diff --git a/arch/arm64/boot/dts/ti/k3-am65-main.dtsi b/arch/arm64/boot/dts= /ti/k3-am65-main.dtsi index 0803a8b9bfe84..127f581a56bc6 100644 --- a/arch/arm64/boot/dts/ti/k3-am65-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am65-main.dtsi @@ -439,12 +439,6 @@ sdhci0: mmc@4f80000 { ti,trm-icp =3D <0x8>; ti,otap-del-sel-legacy =3D <0x0>; ti,otap-del-sel-mmc-hs =3D <0x0>; - ti,otap-del-sel-sd-hs =3D <0x0>; - ti,otap-del-sel-sdr12 =3D <0x0>; - ti,otap-del-sel-sdr25 =3D <0x0>; - ti,otap-del-sel-sdr50 =3D <0x8>; - ti,otap-del-sel-sdr104 =3D <0x7>; - ti,otap-del-sel-ddr50 =3D <0x5>; ti,otap-del-sel-ddr52 =3D <0x5>; ti,otap-del-sel-hs200 =3D <0x5>; ti,itap-del-sel-ddr52 =3D <0x0>; @@ -462,15 +456,12 @@ sdhci1: mmc@4fa0000 { ti,clkbuf-sel =3D <0x7>; ti,trm-icp =3D <0x8>; ti,otap-del-sel-legacy =3D <0x0>; - ti,otap-del-sel-mmc-hs =3D <0x0>; ti,otap-del-sel-sd-hs =3D <0x0>; ti,otap-del-sel-sdr12 =3D <0xf>; ti,otap-del-sel-sdr25 =3D <0xf>; ti,otap-del-sel-sdr50 =3D <0x8>; ti,otap-del-sel-sdr104 =3D <0x7>; ti,otap-del-sel-ddr50 =3D <0x4>; - ti,otap-del-sel-ddr52 =3D <0x4>; - ti,otap-del-sel-hs200 =3D <0x7>; ti,itap-del-sel-legacy =3D <0xa>; ti,itap-del-sel-sd-hs =3D <0x1>; ti,itap-del-sel-sdr12 =3D <0xa>; --=20 2.43.2 From nobody Fri May 17 07:07:48 2024 Received: from lelv0143.ext.ti.com (lelv0143.ext.ti.com [198.47.23.248]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B8BE56EB5B; Tue, 16 Apr 2024 22:17:06 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.47.23.248 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1713305828; cv=none; b=cQZ3gYyoHTk2Bglvr8D3TMXtXlri2kUxWci3F09/C4qeh/osWsh1DUq9kjD9ffHMKf8qo9wyhntVkhxO44gPMmxW4K3K34zVwvVXrEryqZ54wV2vu0Wz5ulAc/6nBeTFNjuwoKGNo/frWf7RI2F1865aH4CDocVpLRk0mKsHywE= ARC-Message-Signature: i=1; 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Tue, 16 Apr 2024 17:16:48 -0500 Received: from judy-hp.dhcp.ti.com (judy-hp.dhcp.ti.com [128.247.81.105]) by lelvsmtp5.itg.ti.com (8.15.2/8.15.2) with ESMTP id 43GMGmSn102285; Tue, 16 Apr 2024 17:16:48 -0500 From: Judith Mendez To: Rob Herring , Krzysztof Kozlowski , Catalin Marinas , Will Deacon CC: Vignesh Raghavendra , Conor Dooley , , , , Bhavya Kapoor , Dasnavis Sabiya Subject: [PATCH v2 3/6] arm64: dts: ti: k3-am62a: Enable UHS mode support for SD cards Date: Tue, 16 Apr 2024 17:16:45 -0500 Message-ID: <20240416221648.3522201-4-jm@ti.com> X-Mailer: git-send-email 2.43.2 In-Reply-To: <20240416221648.3522201-1-jm@ti.com> References: <20240416221648.3522201-1-jm@ti.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Content-Type: text/plain; charset="utf-8" From: Vignesh Raghavendra Hook up required IO voltage regulators and drop no-1-8-v to support UHS modes on SD cards. Fixes: 5fc6b1b62639 ("arm64: dts: ti: Introduce AM62A7 family of SoCs") Signed-off-by: Vignesh Raghavendra [Judith: Remove no-1-8-v for sdhci2, keep otap-del-sel-legacy=3D0, add fixes tag, reword commit] Signed-off-by: Judith Mendez --- Changes since v1: - no change --- arch/arm64/boot/dts/ti/k3-am62a-main.dtsi | 2 -- arch/arm64/boot/dts/ti/k3-am62a7-sk.dts | 21 +++++++++++++++++++++ 2 files changed, 21 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/ti/k3-am62a-main.dtsi b/arch/arm64/boot/dt= s/ti/k3-am62a-main.dtsi index aa1e057082f08..6652701d3e3b8 100644 --- a/arch/arm64/boot/dts/ti/k3-am62a-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am62a-main.dtsi @@ -573,7 +573,6 @@ sdhci1: mmc@fa00000 { ti,itap-del-sel-sd-hs =3D <0x0>; ti,itap-del-sel-sdr12 =3D <0x0>; ti,itap-del-sel-sdr25 =3D <0x0>; - no-1-8-v; status =3D "disabled"; }; =20 @@ -597,7 +596,6 @@ sdhci2: mmc@fa20000 { ti,itap-del-sel-sd-hs =3D <0x0>; ti,itap-del-sel-sdr12 =3D <0x0>; ti,itap-del-sel-sdr25 =3D <0x0>; - no-1-8-v; status =3D "disabled"; }; =20 diff --git a/arch/arm64/boot/dts/ti/k3-am62a7-sk.dts b/arch/arm64/boot/dts/= ti/k3-am62a7-sk.dts index f241637a5642a..fa43cd0b631e6 100644 --- a/arch/arm64/boot/dts/ti/k3-am62a7-sk.dts +++ b/arch/arm64/boot/dts/ti/k3-am62a7-sk.dts @@ -113,6 +113,20 @@ vcc_3v3_sys: regulator-4 { regulator-boot-on; }; =20 + vddshv_sdio: regulator-5 { + compatible =3D "regulator-gpio"; + regulator-name =3D "vddshv_sdio"; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&vddshv_sdio_pins_default>; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <3300000>; + regulator-boot-on; + vin-supply =3D <&ldo1>; + gpios =3D <&main_gpio0 31 GPIO_ACTIVE_HIGH>; + states =3D <1800000 0x0>, + <3300000 0x1>; + }; + leds { compatible =3D "gpio-leds"; pinctrl-names =3D "default"; @@ -342,6 +356,12 @@ main_gpio1_ioexp_intr_pins_default: main-gpio1-ioexp-i= ntr-default-pins { AM62AX_IOPAD(0x01d4, PIN_INPUT, 7) /* (C15) UART0_RTSn.GPIO1_23 */ >; }; + + vddshv_sdio_pins_default: vddshv-sdio-default-pins { + pinctrl-single,pins =3D < + AM62AX_IOPAD(0x07c, PIN_OUTPUT, 7) /* (M19) GPMC0_CLK.GPIO0_31 */ + >; + }; }; =20 &mcu_pmx0 { @@ -580,6 +600,7 @@ &sdhci1 { /* SD/MMC */ status =3D "okay"; vmmc-supply =3D <&vdd_mmc1>; + vqmmc-supply =3D <&vddshv_sdio>; pinctrl-names =3D "default"; pinctrl-0 =3D <&main_mmc1_pins_default>; disable-wp; --=20 2.43.2 From nobody Fri May 17 07:07:48 2024 Received: from fllv0015.ext.ti.com (fllv0015.ext.ti.com [198.47.19.141]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id CC6A584FB3; Tue, 16 Apr 2024 22:17:08 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.47.19.141 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1713305830; cv=none; b=YoPeSOpA5X+I/6ErTY5m+rHstYP+ydijq14ueSZEZhxRQdz707HTeA5xrOuEIh2ccqCuuqhAsV7nfKI4Fnrf4LSdC4VNMUn7tnhC5aVMGCfrC3WJKkr4cWgdV77dZnEuQFekUajhrSQiLcHRBrESDVQcmftp0ntcy/2P0VeLGuc= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1713305830; 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Tue, 16 Apr 2024 17:16:48 -0500 Received: from judy-hp.dhcp.ti.com (judy-hp.dhcp.ti.com [128.247.81.105]) by lelvsmtp5.itg.ti.com (8.15.2/8.15.2) with ESMTP id 43GMGmSo102285; Tue, 16 Apr 2024 17:16:48 -0500 From: Judith Mendez To: Rob Herring , Krzysztof Kozlowski , Catalin Marinas , Will Deacon CC: Vignesh Raghavendra , Conor Dooley , , , , Bhavya Kapoor , Dasnavis Sabiya Subject: [PATCH v2 4/6] arm64: dts: ti: k3-j721s2-main: Enable support for SDR104 speed mode Date: Tue, 16 Apr 2024 17:16:46 -0500 Message-ID: <20240416221648.3522201-5-jm@ti.com> X-Mailer: git-send-email 2.43.2 In-Reply-To: <20240416221648.3522201-1-jm@ti.com> References: <20240416221648.3522201-1-jm@ti.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Content-Type: text/plain; charset="utf-8" From: Bhavya Kapoor According to TRM for J721S2, SDR104 speed mode is supported by the SoC but its capabilities were masked in device tree. Remove sdhci-caps-mask to enable support for SDR104 speed mode for SD card in J721S2 SoC. [+] Refer to : section 12.3.6.1.1 MMCSD Features, in J721S2 TRM - https://www.ti.com/lit/zip/spruj28 Fixes: b8545f9d3a54 ("arm64: dts: ti: Add initial support for J721S2 SoC") Signed-off-by: Bhavya Kapoor Signed-off-by: Vignesh Raghavendra --- Changes since v1: - no change --- arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi | 2 -- 1 file changed, 2 deletions(-) diff --git a/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi b/arch/arm64/boot/d= ts/ti/k3-j721s2-main.dtsi index 3cb06a7e4117f..9ed6949b40e9d 100644 --- a/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi @@ -768,8 +768,6 @@ main_sdhci1: mmc@4fb0000 { ti,clkbuf-sel =3D <0x7>; ti,trm-icp =3D <0x8>; dma-coherent; - /* Masking support for SDR104 capability */ - sdhci-caps-mask =3D <0x00000003 0x00000000>; status =3D "disabled"; }; =20 --=20 2.43.2 From nobody Fri May 17 07:07:48 2024 Received: from lelv0143.ext.ti.com (lelv0143.ext.ti.com [198.47.23.248]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 0DCC584D3B; Tue, 16 Apr 2024 22:17:07 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.47.23.248 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1713305829; cv=none; b=GaER0WwQ9tLSPDyEkh6ycs8Mgpi9clxsUiZXu414IoC0hqu7GYT9R9ZWOYZAhkzdKunw35+hZ7bGOkdz37b5yRu7A1vZQ/eRnJPul+Vjv3JFkwbajydwuLLAY5wSmg87atg8G4smhor4TnGLxKh3ragIdMpw9v/6YMkRIGTPKdk= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1713305829; c=relaxed/simple; bh=/r2A3U86DrQWK58HmyUtSBfncTMbSG8hZpg5gw3B6c8=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=rMgmoO12mmNJ0WnVSOkPTjiBjkSMccp9Ayg5ksaz+XjrOYiUPZaPvcKcQOWZn6GJsKVcpb4e6/qWCip+6Y3/TNWM/frttD/LQqMxk5Q3ydJ7bmuHSrRAfqAeD9lRLXeINu7HKpOGPYtprsWntljYM0A2y4rc3M9I8jBQTlGHjds= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com; spf=pass smtp.mailfrom=ti.com; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b=x++c0dsK; arc=none smtp.client-ip=198.47.23.248 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=ti.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b="x++c0dsK" Received: from fllv0035.itg.ti.com ([10.64.41.0]) by lelv0143.ext.ti.com (8.15.2/8.15.2) with ESMTP id 43GMGnFN065475; Tue, 16 Apr 2024 17:16:49 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1713305809; bh=hC7S8iATRYbpfYUlqNN78DDTwCwaRv8ntPclDXxhb1A=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=x++c0dsKiwMKcr2g0urHtzuvZ5XmTvzDj5Gn3khp+TNEnpjLaGvJHY+QPz2dWKSod mU2zJ0sANoB2JMOIcqUwl44RUUUWE9KKi1f8eogFgMAqGlkT9WrMfeATz9cyFivhHN m+YnePQOnUHHvTBzTzRudYGW6cqa1hudMiiWwvOg= Received: from DLEE100.ent.ti.com (dlee100.ent.ti.com [157.170.170.30]) by fllv0035.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 43GMGnpv080068 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Tue, 16 Apr 2024 17:16:49 -0500 Received: from DLEE107.ent.ti.com (157.170.170.37) by DLEE100.ent.ti.com (157.170.170.30) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23; Tue, 16 Apr 2024 17:16:48 -0500 Received: from lelvsmtp5.itg.ti.com (10.180.75.250) by DLEE107.ent.ti.com (157.170.170.37) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23 via Frontend Transport; Tue, 16 Apr 2024 17:16:49 -0500 Received: from judy-hp.dhcp.ti.com (judy-hp.dhcp.ti.com [128.247.81.105]) by lelvsmtp5.itg.ti.com (8.15.2/8.15.2) with ESMTP id 43GMGmSp102285; Tue, 16 Apr 2024 17:16:48 -0500 From: Judith Mendez To: Rob Herring , Krzysztof Kozlowski , Catalin Marinas , Will Deacon CC: Vignesh Raghavendra , Conor Dooley , , , , Bhavya Kapoor , Dasnavis Sabiya Subject: [PATCH v2 5/6] arm64: dts: ti: k3-j784s4-main: Enable support for UHS mode Date: Tue, 16 Apr 2024 17:16:47 -0500 Message-ID: <20240416221648.3522201-6-jm@ti.com> X-Mailer: git-send-email 2.43.2 In-Reply-To: <20240416221648.3522201-1-jm@ti.com> References: <20240416221648.3522201-1-jm@ti.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Content-Type: text/plain; charset="utf-8" From: Dasnavis Sabiya Remove sdhci-caps-mask to enable support for SDR104 speed mode for SD card and remove no-1-8-v property so that SD card can work in any UHS-1 high speed mode it can support. Fixes: 4664ebd8346a ("arm64: dts: ti: Add initial support for J784S4 SoC") Signed-off-by: Bhavya Kapoor Signed-off-by: Dasnavis Sabiya Signed-off-by: Vignesh Raghavendra [Judith: Add fixes tag] Signed-off-by: Judith Mendez --- Changes since v1: - no change --- arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi | 2 -- 1 file changed, 2 deletions(-) diff --git a/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi b/arch/arm64/boot/d= ts/ti/k3-j784s4-main.dtsi index d42f25cacf23d..6a4554c6c9c13 100644 --- a/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi @@ -904,8 +904,6 @@ main_sdhci1: mmc@4fb0000 { ti,clkbuf-sel =3D <0x7>; ti,trm-icp =3D <0x8>; dma-coherent; - sdhci-caps-mask =3D <0x00000003 0x00000000>; - no-1-8-v; status =3D "disabled"; }; =20 --=20 2.43.2 From nobody Fri May 17 07:07:48 2024 Received: from fllv0015.ext.ti.com (fllv0015.ext.ti.com [198.47.19.141]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A33306BFCF; Tue, 16 Apr 2024 22:17:05 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.47.19.141 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1713305827; cv=none; b=dMKfo528tP2WLCRyUrP4dEPcmrvGozidq+AWE/PHoUGHNNZ4zq1wwBW8dz11qpQYuELDgxIpDCbj5+jNh8y614PH+DbteRfOea7n+w8BR81DtvcURwTG1Z+1SEPMmuvDfq4xyAADXCK6OCHwBz6RZtD19JKwpuzTT/X7qD7J3lU= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1713305827; c=relaxed/simple; bh=RQXLts+2Rn12zPZ12Grc51NYSJbRWnHadEoB87tXqiU=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=UhRq+W5C9+Vwu3Y9DD5PpK80c/yKvzZ0/4afS9jB3/IcVWiPuZ5d/h723muTeQ9de2Pdga3tBKCfn4BKu5BT9IxsJaC7uq71uc0ekzKEUxc16kDUHaSX16nJvPsjLE8VHR9lmg9cV/ndJ98KBGuWfeuInsgo2GeOZMIOMZ0h0eQ= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com; spf=pass smtp.mailfrom=ti.com; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b=AfR3tbSr; arc=none smtp.client-ip=198.47.19.141 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=ti.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b="AfR3tbSr" Received: from lelv0265.itg.ti.com ([10.180.67.224]) by fllv0015.ext.ti.com (8.15.2/8.15.2) with ESMTP id 43GMGng4005876; Tue, 16 Apr 2024 17:16:49 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1713305809; bh=RWH/iQBiLInYxzD4x9yZTgA4icfQMVshpbXpgkbwrw0=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=AfR3tbSr4ZVD+V3ispOeIr3f5V3KQNPis9zreLbUWEK3cYyOpMtB+YX5i0V08p7YU 1Nv87gUZkZv8KH1W78/7hMqrvoaUL2HcmWr54xq5ZFLogChfbu7g+zf2q0tyHUet91 ZX3ncphyc8Opb+siMlJg7ApDQYC1uOpEP4rFBxbM= Received: from DFLE105.ent.ti.com (dfle105.ent.ti.com [10.64.6.26]) by lelv0265.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 43GMGnDw020612 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Tue, 16 Apr 2024 17:16:49 -0500 Received: from DFLE103.ent.ti.com (10.64.6.24) by DFLE105.ent.ti.com (10.64.6.26) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23; Tue, 16 Apr 2024 17:16:48 -0500 Received: from lelvsmtp5.itg.ti.com (10.180.75.250) by DFLE103.ent.ti.com (10.64.6.24) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23 via Frontend Transport; Tue, 16 Apr 2024 17:16:48 -0500 Received: from judy-hp.dhcp.ti.com (judy-hp.dhcp.ti.com [128.247.81.105]) by lelvsmtp5.itg.ti.com (8.15.2/8.15.2) with ESMTP id 43GMGmSq102285; Tue, 16 Apr 2024 17:16:48 -0500 From: Judith Mendez To: Rob Herring , Krzysztof Kozlowski , Catalin Marinas , Will Deacon CC: Vignesh Raghavendra , Conor Dooley , , , , Bhavya Kapoor , Dasnavis Sabiya Subject: [PATCH v2 6/6] arm64: defconfig: Set CONFIG_MFD_TPS6594_I2C=y Date: Tue, 16 Apr 2024 17:16:48 -0500 Message-ID: <20240416221648.3522201-7-jm@ti.com> X-Mailer: git-send-email 2.43.2 In-Reply-To: <20240416221648.3522201-1-jm@ti.com> References: <20240416221648.3522201-1-jm@ti.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Content-Type: text/plain; charset="utf-8" SK-AM62A-LP uses TPS6593x PMIC (interfaced over I2C) to power the SoC and various other peripherals on the board [1]. Booting SD with UHS modes have a dependency on TPS6593x PMIC driver so change to built in order to boot using SD boot at the higher speed modes. Fixes: f9010eb938be ("arm64: defconfig: Enable TPS6593 PMIC for SK-AM62A") Signed-off-by: Judith Mendez --- Changes since v1: - Add patch 6/6 --- arch/arm64/configs/defconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig index 2c30d617e1802..c994ba7b682dd 100644 --- a/arch/arm64/configs/defconfig +++ b/arch/arm64/configs/defconfig @@ -741,7 +741,7 @@ CONFIG_MFD_SL28CPLD=3Dy CONFIG_RZ_MTU3=3Dy CONFIG_MFD_TI_AM335X_TSCADC=3Dm CONFIG_MFD_TPS65219=3Dy -CONFIG_MFD_TPS6594_I2C=3Dm +CONFIG_MFD_TPS6594_I2C=3Dy CONFIG_MFD_ROHM_BD718XX=3Dy CONFIG_MFD_WCD934X=3Dm CONFIG_MFD_KHADAS_MCU=3Dm --=20 2.43.2