From nobody Mon Feb 9 20:43:19 2026 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.13]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 147AC13C67D for ; Tue, 16 Apr 2024 21:20:09 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.13 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1713302411; cv=none; b=fCZopbLO+C8f4y7Xh+zO3NvACllUVfT5v5sb3mKm4M48UMVjTX9ZELkCFDZgljqiHS1Q4noK0L2NnVd4AZw7OVng6dheSM9OGaCN5b5YK6sFqpIhyKWIa+EkijreUsrz54O0BCtf6blQBXNO+IrfzWWl7K0uky/LrJ4oMDTO2hI= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1713302411; c=relaxed/simple; bh=G4t+oufuiWfevvnnKG7dGJPRWJMmXMgYV/G6McWVaD8=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=PF+cZ3ed69Z7OOhHAHqOlL1RTXfkkYQ7E9iPi+UxmGdUBk9P3dFGHTuTaFOHyCFUic1JvMXWDZSD+kfS7z5gtVWZyotdfvM03E76vprmjjXXoSSM75acwnVWCrPW+wyMDmhb5tUdxFSSAYesp3SCPiexaOni4H8U9DRV3vg/I8Q= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com; spf=pass smtp.mailfrom=intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=RNMpvXCA; arc=none smtp.client-ip=198.175.65.13 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="RNMpvXCA" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1713302409; x=1744838409; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=G4t+oufuiWfevvnnKG7dGJPRWJMmXMgYV/G6McWVaD8=; b=RNMpvXCACZGbrYFwpJmh/R2nsFAXboZn4sfiuqpHKhK1GDRSUd23vLOv gEjfyc7BjPLPzSySToDp2HVQOlDXMMf9RDQYzOIBskLqmqCkinHCSIBht XJOIEwKG+YThmRqo50CACBOB71jLRWJtecQACBXApvc3oy+QKgecpUE65 SDPCh8Qlwlkbe+6qqXvkuGBCakO4v80Civ9PhOaTbIUbQVCM8MEvSytqL jTM655ys6zZtoRMxNRulXj0MVqi/Zm9BDcztu2w844MXc+OBr9dLhFXS0 nJG82NfJLM2mHKVAiTovIsxfqmB24t6v8qN9/WUwWtb5YeEs7XRFy3dfO w==; X-CSE-ConnectionGUID: 9xYHH/twSImF3jUhzI9fbg== X-CSE-MsgGUID: BP7OgYNLTxm147OFzcL2Ew== X-IronPort-AV: E=McAfee;i="6600,9927,11046"; a="19914789" X-IronPort-AV: E=Sophos;i="6.07,207,1708416000"; d="scan'208";a="19914789" Received: from orviesa007.jf.intel.com ([10.64.159.147]) by orvoesa105.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 16 Apr 2024 14:20:01 -0700 X-CSE-ConnectionGUID: KllF7TpVTm6QLorEhQCEpA== X-CSE-MsgGUID: jGVcYaaBRaiWdcuW7aOySA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.07,207,1708416000"; d="scan'208";a="22871976" Received: from agluck-desk3.sc.intel.com ([172.25.222.105]) by orviesa007-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 16 Apr 2024 14:20:00 -0700 From: Tony Luck To: Borislav Petkov Cc: x86@kernel.org, linux-kernel@vger.kernel.org, patches@lists.linux.dev, Tony Luck Subject: [PATCH v3 26/74] x86/cpu/vfm: Update arch/x86/kernel/cpu/resctrl/pseudo_lock.c Date: Tue, 16 Apr 2024 14:19:28 -0700 Message-ID: <20240416211941.9369-27-tony.luck@intel.com> X-Mailer: git-send-email 2.44.0 In-Reply-To: <20240416211941.9369-1-tony.luck@intel.com> References: <20240416211941.9369-1-tony.luck@intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" New CPU #defines encode vendor and family as well as model. Signed-off-by: Tony Luck --- arch/x86/kernel/cpu/resctrl/pseudo_lock.c | 21 +++++++++++---------- 1 file changed, 11 insertions(+), 10 deletions(-) diff --git a/arch/x86/kernel/cpu/resctrl/pseudo_lock.c b/arch/x86/kernel/cp= u/resctrl/pseudo_lock.c index 884b88e25141..a068f0c3bc20 100644 --- a/arch/x86/kernel/cpu/resctrl/pseudo_lock.c +++ b/arch/x86/kernel/cpu/resctrl/pseudo_lock.c @@ -23,6 +23,7 @@ #include =20 #include +#include #include #include #include @@ -88,8 +89,8 @@ static u64 get_prefetch_disable_bits(void) boot_cpu_data.x86 !=3D 6) return 0; =20 - switch (boot_cpu_data.x86_model) { - case INTEL_FAM6_BROADWELL_X: + switch (boot_cpu_data.x86_vfm) { + case INTEL_BROADWELL_X: /* * SDM defines bits of MSR_MISC_FEATURE_CONTROL register * as: @@ -100,8 +101,8 @@ static u64 get_prefetch_disable_bits(void) * 63:4 Reserved */ return 0xF; - case INTEL_FAM6_ATOM_GOLDMONT: - case INTEL_FAM6_ATOM_GOLDMONT_PLUS: + case INTEL_ATOM_GOLDMONT: + case INTEL_ATOM_GOLDMONT_PLUS: /* * SDM defines bits of MSR_MISC_FEATURE_CONTROL register * as: @@ -1084,9 +1085,9 @@ static int measure_l2_residency(void *_plr) * L2_HIT 02H * L2_MISS 10H */ - switch (boot_cpu_data.x86_model) { - case INTEL_FAM6_ATOM_GOLDMONT: - case INTEL_FAM6_ATOM_GOLDMONT_PLUS: + switch (boot_cpu_data.x86_vfm) { + case INTEL_ATOM_GOLDMONT: + case INTEL_ATOM_GOLDMONT_PLUS: perf_miss_attr.config =3D X86_CONFIG(.event =3D 0xd1, .umask =3D 0x10); perf_hit_attr.config =3D X86_CONFIG(.event =3D 0xd1, @@ -1123,8 +1124,8 @@ static int measure_l3_residency(void *_plr) * MISS 41H */ =20 - switch (boot_cpu_data.x86_model) { - case INTEL_FAM6_BROADWELL_X: + switch (boot_cpu_data.x86_vfm) { + case INTEL_BROADWELL_X: /* On BDW the hit event counts references, not hits */ perf_hit_attr.config =3D X86_CONFIG(.event =3D 0x2e, .umask =3D 0x4f); @@ -1142,7 +1143,7 @@ static int measure_l3_residency(void *_plr) */ =20 counts.miss_after -=3D counts.miss_before; - if (boot_cpu_data.x86_model =3D=3D INTEL_FAM6_BROADWELL_X) { + if (boot_cpu_data.x86_vfm =3D=3D INTEL_BROADWELL_X) { /* * On BDW references and misses are counted, need to adjust. * Sometimes the "hits" counter is a bit more than the --=20 2.44.0