From nobody Mon Feb 9 05:52:12 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 75DA584A5C for ; Fri, 12 Apr 2024 13:44:16 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1712929456; cv=none; b=Ln+f4EXbAzDzwh/Pp+PUxJbABvpIZuvLiC8N1PX2KnOgLXLKagd/z4SwQrS3sXmpJq/TOf8Fxb1qOOIn7Z52mIEjxlnQqWRN9G6eFpSLXrgD0wZ5j74RUGQ9lCi48lGzSZZ7f1EXijHUPwg9Ith6JqrOgiH4TN6dNoFU5/tPUE0= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1712929456; c=relaxed/simple; bh=QVHvqJfpR6HpyyA7+X+VGVBwzk2Mqc1k3kJ/dIAhUrk=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=XuZ7S20DI2JbOvwUPd4VNnLPiiL3Mi6z1yTqYCLz96jf/StrCuhZQmjdp6Y+c4EJorvV/6go7n5tsiHyHmwJOaeR6Sh6TO3xvY54QyIXbm9fVqDi0NB8wYIK5Y3jr8j4VjW2d64K7B7cFIe3TFPzKj8EwWIHOsUS62p3Whgppes= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=WP1cF5Qh; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="WP1cF5Qh" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 93CEAC2BD10; Fri, 12 Apr 2024 13:44:14 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1712929456; bh=QVHvqJfpR6HpyyA7+X+VGVBwzk2Mqc1k3kJ/dIAhUrk=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=WP1cF5QhBykq4x7XD5/jiX0GC/x54f1IsADqN8ZfcHbGEtONmV8pqlnuENU6hGHW6 +Pu5WSpww2r4SS2rCBx712bRuQNxIokkeKd6KFBuvlz7XfHt5VCJ0eB4aN0aNX15fd yidrOYlzgVqYrWf0Hs1ykqeLar34dBV5I8CSvv4bKT97TMdxvki+IRc6AK7XFlBpZc B6oFmN/9WTLwxxAcurW6b69pzl9gPX8mumYAJN+zrkOjLouRBygLdEv06QoKe1Yqrr iq3XqyA3SVoCwXQhfFQ5OUhnZ75vh7xN647iDZoVi9QRYfEY6O1AvTTzzb0vl8EtO7 8WsvejyW/zCeQ== From: Michael Walle To: Tudor Ambarus , Pratyush Yadav , Miquel Raynal , Richard Weinberger , Vignesh Raghavendra Cc: linux-kernel@vger.kernel.org, linux-mtd@lists.infradead.org, Michael Walle Subject: [PATCH v1 1/6] mtd: spi-nor: Remove support for Xilinx S3AN flashes Date: Fri, 12 Apr 2024 15:44:00 +0200 Message-Id: <20240412134405.381832-2-mwalle@kernel.org> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20240412134405.381832-1-mwalle@kernel.org> References: <20240412134405.381832-1-mwalle@kernel.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" These flashes are kind of an oddball for the very old Xilinx Spartan 3 FPGAs to store their bitstream. More importantly, they reuse the Atmel JEDEC manufacturer ID and in fact the at45db081d already blocks the use of the 3S700AN flash chip. It's time to sunset support for these flashes. Signed-off-by: Michael Walle Acked-by: Tudor Ambarus Reviewed-by: Pratyush Yadav --- drivers/mtd/spi-nor/Makefile | 1 - drivers/mtd/spi-nor/core.c | 1 - drivers/mtd/spi-nor/core.h | 1 - drivers/mtd/spi-nor/xilinx.c | 169 ----------------------------------- 4 files changed, 172 deletions(-) delete mode 100644 drivers/mtd/spi-nor/xilinx.c diff --git a/drivers/mtd/spi-nor/Makefile b/drivers/mtd/spi-nor/Makefile index 5e68468b72fc..5dd9c35f6b6f 100644 --- a/drivers/mtd/spi-nor/Makefile +++ b/drivers/mtd/spi-nor/Makefile @@ -13,7 +13,6 @@ spi-nor-objs +=3D micron-st.o spi-nor-objs +=3D spansion.o spi-nor-objs +=3D sst.o spi-nor-objs +=3D winbond.o -spi-nor-objs +=3D xilinx.o spi-nor-objs +=3D xmc.o spi-nor-$(CONFIG_DEBUG_FS) +=3D debugfs.o obj-$(CONFIG_MTD_SPI_NOR) +=3D spi-nor.o diff --git a/drivers/mtd/spi-nor/core.c b/drivers/mtd/spi-nor/core.c index 3e1f1913536b..cbe5f92eb0af 100644 --- a/drivers/mtd/spi-nor/core.c +++ b/drivers/mtd/spi-nor/core.c @@ -1986,7 +1986,6 @@ static const struct spi_nor_manufacturer *manufacture= rs[] =3D { &spi_nor_spansion, &spi_nor_sst, &spi_nor_winbond, - &spi_nor_xilinx, &spi_nor_xmc, }; =20 diff --git a/drivers/mtd/spi-nor/core.h b/drivers/mtd/spi-nor/core.h index 442786685515..072c69b0d06c 100644 --- a/drivers/mtd/spi-nor/core.h +++ b/drivers/mtd/spi-nor/core.h @@ -603,7 +603,6 @@ extern const struct spi_nor_manufacturer spi_nor_st; extern const struct spi_nor_manufacturer spi_nor_spansion; extern const struct spi_nor_manufacturer spi_nor_sst; extern const struct spi_nor_manufacturer spi_nor_winbond; -extern const struct spi_nor_manufacturer spi_nor_xilinx; extern const struct spi_nor_manufacturer spi_nor_xmc; =20 extern const struct attribute_group *spi_nor_sysfs_groups[]; diff --git a/drivers/mtd/spi-nor/xilinx.c b/drivers/mtd/spi-nor/xilinx.c deleted file mode 100644 index f99118c691b0..000000000000 --- a/drivers/mtd/spi-nor/xilinx.c +++ /dev/null @@ -1,169 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Copyright (C) 2005, Intec Automation Inc. - * Copyright (C) 2014, Freescale Semiconductor, Inc. - */ - -#include - -#include "core.h" - -#define XILINX_OP_SE 0x50 /* Sector erase */ -#define XILINX_OP_PP 0x82 /* Page program */ -#define XILINX_OP_RDSR 0xd7 /* Read status register */ - -#define XSR_PAGESIZE BIT(0) /* Page size in Po2 or Linear */ -#define XSR_RDY BIT(7) /* Ready */ - -#define XILINX_RDSR_OP(buf) \ - SPI_MEM_OP(SPI_MEM_OP_CMD(XILINX_OP_RDSR, 0), \ - SPI_MEM_OP_NO_ADDR, \ - SPI_MEM_OP_NO_DUMMY, \ - SPI_MEM_OP_DATA_IN(1, buf, 0)) - -#define S3AN_FLASH(_id, _name, _n_sectors, _page_size) \ - .id =3D _id, \ - .name =3D _name, \ - .size =3D 8 * (_page_size) * (_n_sectors), \ - .sector_size =3D (8 * (_page_size)), \ - .page_size =3D (_page_size), \ - .flags =3D SPI_NOR_NO_FR - -/* Xilinx S3AN share MFR with Atmel SPI NOR */ -static const struct flash_info xilinx_nor_parts[] =3D { - /* Xilinx S3AN Internal Flash */ - { S3AN_FLASH(SNOR_ID(0x1f, 0x22, 0x00), "3S50AN", 64, 264) }, - { S3AN_FLASH(SNOR_ID(0x1f, 0x24, 0x00), "3S200AN", 256, 264) }, - { S3AN_FLASH(SNOR_ID(0x1f, 0x24, 0x00), "3S400AN", 256, 264) }, - { S3AN_FLASH(SNOR_ID(0x1f, 0x25, 0x00), "3S700AN", 512, 264) }, - { S3AN_FLASH(SNOR_ID(0x1f, 0x26, 0x00), "3S1400AN", 512, 528) }, -}; - -/* - * This code converts an address to the Default Address Mode, that has non - * power of two page sizes. We must support this mode because it is the de= fault - * mode supported by Xilinx tools, it can access the whole flash area and - * changing over to the Power-of-two mode is irreversible and corrupts the - * original data. - * Addr can safely be unsigned int, the biggest S3AN device is smaller than - * 4 MiB. - */ -static u32 s3an_nor_convert_addr(struct spi_nor *nor, u32 addr) -{ - u32 page_size =3D nor->params->page_size; - u32 offset, page; - - offset =3D addr % page_size; - page =3D addr / page_size; - page <<=3D (page_size > 512) ? 10 : 9; - - return page | offset; -} - -/** - * xilinx_nor_read_sr() - Read the Status Register on S3AN flashes. - * @nor: pointer to 'struct spi_nor'. - * @sr: pointer to a DMA-able buffer where the value of the - * Status Register will be written. - * - * Return: 0 on success, -errno otherwise. - */ -static int xilinx_nor_read_sr(struct spi_nor *nor, u8 *sr) -{ - int ret; - - if (nor->spimem) { - struct spi_mem_op op =3D XILINX_RDSR_OP(sr); - - spi_nor_spimem_setup_op(nor, &op, nor->reg_proto); - - ret =3D spi_mem_exec_op(nor->spimem, &op); - } else { - ret =3D spi_nor_controller_ops_read_reg(nor, XILINX_OP_RDSR, sr, - 1); - } - - if (ret) - dev_dbg(nor->dev, "error %d reading SR\n", ret); - - return ret; -} - -/** - * xilinx_nor_sr_ready() - Query the Status Register of the S3AN flash to = see - * if the flash is ready for new commands. - * @nor: pointer to 'struct spi_nor'. - * - * Return: 1 if ready, 0 if not ready, -errno on errors. - */ -static int xilinx_nor_sr_ready(struct spi_nor *nor) -{ - int ret; - - ret =3D xilinx_nor_read_sr(nor, nor->bouncebuf); - if (ret) - return ret; - - return !!(nor->bouncebuf[0] & XSR_RDY); -} - -static int xilinx_nor_setup(struct spi_nor *nor, - const struct spi_nor_hwcaps *hwcaps) -{ - u32 page_size; - int ret; - - ret =3D xilinx_nor_read_sr(nor, nor->bouncebuf); - if (ret) - return ret; - - nor->erase_opcode =3D XILINX_OP_SE; - nor->program_opcode =3D XILINX_OP_PP; - nor->read_opcode =3D SPINOR_OP_READ; - nor->flags |=3D SNOR_F_NO_OP_CHIP_ERASE; - - /* - * This flashes have a page size of 264 or 528 bytes (known as - * Default addressing mode). It can be changed to a more standard - * Power of two mode where the page size is 256/512. This comes - * with a price: there is 3% less of space, the data is corrupted - * and the page size cannot be changed back to default addressing - * mode. - * - * The current addressing mode can be read from the XRDSR register - * and should not be changed, because is a destructive operation. - */ - if (nor->bouncebuf[0] & XSR_PAGESIZE) { - /* Flash in Power of 2 mode */ - page_size =3D (nor->params->page_size =3D=3D 264) ? 256 : 512; - nor->params->page_size =3D page_size; - nor->mtd.writebufsize =3D page_size; - nor->params->size =3D nor->info->size; - nor->mtd.erasesize =3D 8 * page_size; - } else { - /* Flash in Default addressing mode */ - nor->params->convert_addr =3D s3an_nor_convert_addr; - nor->mtd.erasesize =3D nor->info->sector_size; - } - - return 0; -} - -static int xilinx_nor_late_init(struct spi_nor *nor) -{ - nor->params->setup =3D xilinx_nor_setup; - nor->params->ready =3D xilinx_nor_sr_ready; - - return 0; -} - -static const struct spi_nor_fixups xilinx_nor_fixups =3D { - .late_init =3D xilinx_nor_late_init, -}; - -const struct spi_nor_manufacturer spi_nor_xilinx =3D { - .name =3D "xilinx", - .parts =3D xilinx_nor_parts, - .nparts =3D ARRAY_SIZE(xilinx_nor_parts), - .fixups =3D &xilinx_nor_fixups, -}; --=20 2.39.2 From nobody Mon Feb 9 05:52:12 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id CE07F84E01 for ; Fri, 12 Apr 2024 13:44:18 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1712929458; cv=none; b=GxmkbOhxSG3aD1VMkV/G6fGjmrR4QPx/5SFx+JF79boCBPIlVqnVlOTMH5IXnkVnk6U/hvJZbbmZvr2fPKGPCU57Bz6zf3dc1EhcwVvTJioBr70DLT7Zg73VASLSUBUIQCNW8o53qYxg4jH97l2FisW4wbi2eKrMQQmoeV52bGY= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1712929458; c=relaxed/simple; bh=gKGUc/1cQbsMy5SwuoHZdZG4ZL+HCcopgsRqDXXZ9hs=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=eqL+wR82kTTsGNjus9DJcYKuOlDIVn7tzVmjNgkll93hoKE+f+6Of/4AwffihQnalAQyaxKTqCZKV0E0sqbU+BAPssQfN48DvMBlO/qA/twu4ykukj2hbhJzpVLxZDEa/sge3gpHLRONigSBGGX89rgcxiDKhuL4UdU1xa8U4oc= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=ZmzdkDDa; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="ZmzdkDDa" Received: by smtp.kernel.org (Postfix) with ESMTPSA id B3FAAC32781; Fri, 12 Apr 2024 13:44:16 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1712929458; bh=gKGUc/1cQbsMy5SwuoHZdZG4ZL+HCcopgsRqDXXZ9hs=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=ZmzdkDDascJuxzR8+nPCVHl7jYh25K94DrpS2ELa323WyinpN/GBlZSskLtax//Wk s3ApOWXuhhXGkqtOHgbpOGzG76/jpg99HGyYfTzNUDUez5VUwNNkPJQL9ITjCT4Fb0 jwO0sMyoWswWQEuYxKl8MA91tlMKrdMdlhJreZ30OMYFPZkRbsCdv3/mc2Usa5PTgK 6QdGoM+KYzLLu18GKoIZUJ8b0kkr9+VbyGosI4HSjCM4nQrqpI48ytJQln2dAsEy9i DbWp9qDQn0yWKa9emz+6CUFnH0YF2PHuMELxp8MQS6ogbFAx/suSVPxzwi8foGTom1 M7cqGMUZ/mMjQ== From: Michael Walle To: Tudor Ambarus , Pratyush Yadav , Miquel Raynal , Richard Weinberger , Vignesh Raghavendra Cc: linux-kernel@vger.kernel.org, linux-mtd@lists.infradead.org, Michael Walle Subject: [PATCH v1 2/6] mtd: spi-nor: get rid of non-power-of-2 page size handling Date: Fri, 12 Apr 2024 15:44:01 +0200 Message-Id: <20240412134405.381832-3-mwalle@kernel.org> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20240412134405.381832-1-mwalle@kernel.org> References: <20240412134405.381832-1-mwalle@kernel.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The Xilinx flashes were the only user of the page sized that were no power of 2. Support for them were dropped, thus we can also get rid of the special page size handling for it. Signed-off-by: Michael Walle Acked-by: Tudor Ambarus --- drivers/mtd/spi-nor/core.c | 27 +++++++++++---------------- 1 file changed, 11 insertions(+), 16 deletions(-) diff --git a/drivers/mtd/spi-nor/core.c b/drivers/mtd/spi-nor/core.c index cbe5f92eb0af..fb76e0522665 100644 --- a/drivers/mtd/spi-nor/core.c +++ b/drivers/mtd/spi-nor/core.c @@ -2098,7 +2098,7 @@ static int spi_nor_write(struct mtd_info *mtd, loff_t= to, size_t len, size_t *retlen, const u_char *buf) { struct spi_nor *nor =3D mtd_to_spi_nor(mtd); - size_t page_offset, page_remain, i; + size_t i; ssize_t ret; u32 page_size =3D nor->params->page_size; =20 @@ -2111,21 +2111,9 @@ static int spi_nor_write(struct mtd_info *mtd, loff_= t to, size_t len, for (i =3D 0; i < len; ) { ssize_t written; loff_t addr =3D to + i; - - /* - * If page_size is a power of two, the offset can be quickly - * calculated with an AND operation. On the other cases we - * need to do a modulus operation (more expensive). - */ - if (is_power_of_2(page_size)) { - page_offset =3D addr & (page_size - 1); - } else { - u64 aux =3D addr; - - page_offset =3D do_div(aux, page_size); - } + size_t page_offset =3D addr & (page_size - 1); /* the size of data remaining on the first page */ - page_remain =3D min_t(size_t, page_size - page_offset, len - i); + size_t page_remain =3D min_t(size_t, page_size - page_offset, len - i); =20 addr =3D spi_nor_convert_addr(nor, addr); =20 @@ -3054,7 +3042,14 @@ static int spi_nor_init_params(struct spi_nor *nor) spi_nor_init_params_deprecated(nor); } =20 - return spi_nor_late_init_params(nor); + ret =3D spi_nor_late_init_params(nor); + if (ret) + return ret; + + if (WARN_ON(!is_power_of_2(nor->params->page_size))) + return -EINVAL; + + return 0; } =20 /** spi_nor_set_octal_dtr() - enable or disable Octal DTR I/O. --=20 2.39.2 From nobody Mon Feb 9 05:52:12 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 030F684E1C for ; Fri, 12 Apr 2024 13:44:20 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1712929461; cv=none; b=CzWEZk5f1tOv7hQ8q65wC6Nnz3ZL4kGxhlVK5bHzRUv1gVYtNX5ZjlGOC7wwcED9N0nHxYZy0ULFkaebtw5FRRsSqYhSu1j1u6vTwKDDhU60pbcc1e2AjhtezQH0WkE0aZeAXTjlIG1wdyye9qgUWBV9ynwVOpnjR2aP4g4YXT8= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1712929461; c=relaxed/simple; bh=AWw8QbtlrB4/ifJTs50t8o18KiRdvOyj1VqAGw4riZg=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=rPp331ox/HpH2u3vuAHNC9BC24zbdGAcn5FHSpBNwOR4nGvcTftMoID0UBXiHQLSe+1eg7BnYe2XkdFktY4nos3zcgxhR3BZDaEYsQA2qIzByVKDtKVtFM0ZsLboLSciIfrvmZJ/PvaMqCTHWA5p8q/GNFiNZM757sCtSsRi2Yc= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=Y5bW4N7Y; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="Y5bW4N7Y" Received: by smtp.kernel.org (Postfix) with ESMTPSA id D2D29C113CC; Fri, 12 Apr 2024 13:44:18 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1712929460; bh=AWw8QbtlrB4/ifJTs50t8o18KiRdvOyj1VqAGw4riZg=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=Y5bW4N7YtsBTPZQWSl+W7pqUwakqlNtumlkAg3tNKkn33l87kakt6DdsnqGeyuBDA IrHE+Csk5ZZ2gM8lNWKZQzuL6LB/ttsAtxdBLEdBF2Mt7rHGHuEWyjwivTspBisfFh XEUXOq0vPnOTHYrK+WKNRKCPtGPWFJ4W7wlEZxK3xSNsCPKUOLRdAPoHNBkXivy/tw X7Cy1uEJsQSHgpFNM2OSjXW2BTJaQZ8mmnBf8fSQtME0rY4eBJq56ImlqUaRaoApWD xCqwVXBclDHmA9aMU94FzT6n61R1GBQT4x1uCBKl8iLOiT1qFM2W+VnEYsdldxxyyu t/lzEfqalFtwQ== From: Michael Walle To: Tudor Ambarus , Pratyush Yadav , Miquel Raynal , Richard Weinberger , Vignesh Raghavendra Cc: linux-kernel@vger.kernel.org, linux-mtd@lists.infradead.org, Michael Walle Subject: [PATCH v1 3/6] mtd: spi-nor: get rid of SPI_NOR_NO_FR Date: Fri, 12 Apr 2024 15:44:02 +0200 Message-Id: <20240412134405.381832-4-mwalle@kernel.org> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20240412134405.381832-1-mwalle@kernel.org> References: <20240412134405.381832-1-mwalle@kernel.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The evervision FRAM devices are the only user of the NO_FR flag. Drop the global flag and instead use a manufacturer fixup for the evervision flashes to drop the fast read support. Signed-off-by: Michael Walle --- Please note, that the fast read opcode will still be set in spi_nor_init_default_params(), but the selection of the read opcodes just depends on the mask. That is also something I want to fix soon: the opcodes can always be set and the drivers/SFDP will only set the mask. Opcodes then can be switched between 3b and 4b ones if necessary. --- drivers/mtd/spi-nor/core.c | 12 +++++------- drivers/mtd/spi-nor/core.h | 2 -- drivers/mtd/spi-nor/everspin.c | 19 +++++++++++++++---- 3 files changed, 20 insertions(+), 13 deletions(-) diff --git a/drivers/mtd/spi-nor/core.c b/drivers/mtd/spi-nor/core.c index fb76e0522665..65e6531ada0a 100644 --- a/drivers/mtd/spi-nor/core.c +++ b/drivers/mtd/spi-nor/core.c @@ -2952,14 +2952,12 @@ static void spi_nor_init_default_params(struct spi_= nor *nor) params->page_size =3D info->page_size ?: SPI_NOR_DEFAULT_PAGE_SIZE; params->n_banks =3D info->n_banks ?: SPI_NOR_DEFAULT_N_BANKS; =20 - if (!(info->flags & SPI_NOR_NO_FR)) { - /* Default to Fast Read for DT and non-DT platform devices. */ - params->hwcaps.mask |=3D SNOR_HWCAPS_READ_FAST; + /* Default to Fast Read for DT and non-DT platform devices. */ + params->hwcaps.mask |=3D SNOR_HWCAPS_READ_FAST; =20 - /* Mask out Fast Read if not requested at DT instantiation. */ - if (np && !of_property_read_bool(np, "m25p,fast-read")) - params->hwcaps.mask &=3D ~SNOR_HWCAPS_READ_FAST; - } + /* Mask out Fast Read if not requested at DT instantiation. */ + if (np && !of_property_read_bool(np, "m25p,fast-read")) + params->hwcaps.mask &=3D ~SNOR_HWCAPS_READ_FAST; =20 /* (Fast) Read settings. */ params->hwcaps.mask |=3D SNOR_HWCAPS_READ; diff --git a/drivers/mtd/spi-nor/core.h b/drivers/mtd/spi-nor/core.h index 072c69b0d06c..9aa7d6399c8a 100644 --- a/drivers/mtd/spi-nor/core.h +++ b/drivers/mtd/spi-nor/core.h @@ -479,7 +479,6 @@ struct spi_nor_id { * Usually these will power-up in a write-prote= cted * state. * SPI_NOR_NO_ERASE: no erase command needed. - * SPI_NOR_NO_FR: can't do fastread. * SPI_NOR_QUAD_PP: flash supports Quad Input Page Program. * SPI_NOR_RWW: flash supports reads while write. * @@ -528,7 +527,6 @@ struct flash_info { #define SPI_NOR_BP3_SR_BIT6 BIT(4) #define SPI_NOR_SWP_IS_VOLATILE BIT(5) #define SPI_NOR_NO_ERASE BIT(6) -#define SPI_NOR_NO_FR BIT(7) #define SPI_NOR_QUAD_PP BIT(8) #define SPI_NOR_RWW BIT(9) =20 diff --git a/drivers/mtd/spi-nor/everspin.c b/drivers/mtd/spi-nor/everspin.c index 5f321e24ae7d..0720a61947e7 100644 --- a/drivers/mtd/spi-nor/everspin.c +++ b/drivers/mtd/spi-nor/everspin.c @@ -14,28 +14,39 @@ static const struct flash_info everspin_nor_parts[] =3D= { .size =3D SZ_16K, .sector_size =3D SZ_16K, .addr_nbytes =3D 2, - .flags =3D SPI_NOR_NO_ERASE | SPI_NOR_NO_FR, + .flags =3D SPI_NOR_NO_ERASE, }, { .name =3D "mr25h256", .size =3D SZ_32K, .sector_size =3D SZ_32K, .addr_nbytes =3D 2, - .flags =3D SPI_NOR_NO_ERASE | SPI_NOR_NO_FR, + .flags =3D SPI_NOR_NO_ERASE, }, { .name =3D "mr25h10", .size =3D SZ_128K, .sector_size =3D SZ_128K, - .flags =3D SPI_NOR_NO_ERASE | SPI_NOR_NO_FR, + .flags =3D SPI_NOR_NO_ERASE, }, { .name =3D "mr25h40", .size =3D SZ_512K, .sector_size =3D SZ_512K, - .flags =3D SPI_NOR_NO_ERASE | SPI_NOR_NO_FR, + .flags =3D SPI_NOR_NO_ERASE, } }; =20 +static void evervision_nor_default_init(struct spi_nor *nor) +{ + /* Everspin FRAMs don't support the fast read opcode. */ + nor->params->hwcaps.mask &=3D ~SNOR_HWCAPS_READ_FAST; +} + +static const struct spi_nor_fixups evervision_nor_fixups =3D { + .default_init =3D evervision_nor_default_init, +}; + const struct spi_nor_manufacturer spi_nor_everspin =3D { .name =3D "everspin", .parts =3D everspin_nor_parts, .nparts =3D ARRAY_SIZE(everspin_nor_parts), + .fixups =3D &evervision_nor_fixups, }; --=20 2.39.2 From nobody Mon Feb 9 05:52:12 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 1176985261 for ; Fri, 12 Apr 2024 13:44:22 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; 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a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1712929462; bh=A6BCPGJ14ENBTg9zhAGY9Mu4ckKO6EuAyGkOaKXiHHc=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=OFU3Lzy8z+yqS3ejO+Tcv7VXdremci/vj/siJdZYf2xB1NQB2tC6yhrDX6BmYb/vG gj9m4waCMEED7nkXBaFWXY0jw81LE1NUtmZqdp5dOCcU7lEVvXpd62xtEygRfM+JPj Ssqy/+9duN9wzsIz2K/PXiDoPy7ab6vxcuICJ+itpIdKDz8s7zIRNJGAhMPV+3Ylcj X1erVsCLV/qeHr4iWxzon2l1smWICW6MaHR1og5iZWg9H1osBPf8OeT0BxksQ9XINi Y9SdTJmkF2gSR4aLOb6HxZbpfbNq4MezBkqNo3Pr1rBKx2vVnk3QxyIWGCdcaO6gye T/4IGBmBS297g== From: Michael Walle To: Tudor Ambarus , Pratyush Yadav , Miquel Raynal , Richard Weinberger , Vignesh Raghavendra Cc: linux-kernel@vger.kernel.org, linux-mtd@lists.infradead.org, Michael Walle Subject: [PATCH v1 4/6] mtd: spi-nor: remove .setup() callback Date: Fri, 12 Apr 2024 15:44:03 +0200 Message-Id: <20240412134405.381832-5-mwalle@kernel.org> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20240412134405.381832-1-mwalle@kernel.org> References: <20240412134405.381832-1-mwalle@kernel.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" There is no flash driver using that hook. The original intention was to let the driver configure special requirements like page size an opcodes. This is already possible by other means and it is unlikely a flash will overwrite the (more or less complex) setup function. Signed-off-by: Michael Walle --- drivers/mtd/spi-nor/core.c | 105 ++++++++++++++++--------------------- drivers/mtd/spi-nor/core.h | 5 -- 2 files changed, 45 insertions(+), 65 deletions(-) diff --git a/drivers/mtd/spi-nor/core.c b/drivers/mtd/spi-nor/core.c index 65e6531ada0a..bbfef7b3997f 100644 --- a/drivers/mtd/spi-nor/core.c +++ b/drivers/mtd/spi-nor/core.c @@ -2568,8 +2568,51 @@ static int spi_nor_select_erase(struct spi_nor *nor) return 0; } =20 -static int spi_nor_default_setup(struct spi_nor *nor, - const struct spi_nor_hwcaps *hwcaps) +static int spi_nor_set_addr_nbytes(struct spi_nor *nor) +{ + if (nor->params->addr_nbytes) { + nor->addr_nbytes =3D nor->params->addr_nbytes; + } else if (nor->read_proto =3D=3D SNOR_PROTO_8_8_8_DTR) { + /* + * In 8D-8D-8D mode, one byte takes half a cycle to transfer. So + * in this protocol an odd addr_nbytes cannot be used because + * then the address phase would only span a cycle and a half. + * Half a cycle would be left over. We would then have to start + * the dummy phase in the middle of a cycle and so too the data + * phase, and we will end the transaction with half a cycle left + * over. + * + * Force all 8D-8D-8D flashes to use an addr_nbytes of 4 to + * avoid this situation. + */ + nor->addr_nbytes =3D 4; + } else if (nor->info->addr_nbytes) { + nor->addr_nbytes =3D nor->info->addr_nbytes; + } else { + nor->addr_nbytes =3D 3; + } + + if (nor->addr_nbytes =3D=3D 3 && nor->params->size > 0x1000000) { + /* enable 4-byte addressing if the device exceeds 16MiB */ + nor->addr_nbytes =3D 4; + } + + if (nor->addr_nbytes > SPI_NOR_MAX_ADDR_NBYTES) { + dev_dbg(nor->dev, "The number of address bytes is too large: %u\n", + nor->addr_nbytes); + return -EINVAL; + } + + /* Set 4byte opcodes when possible. */ + if (nor->addr_nbytes =3D=3D 4 && nor->flags & SNOR_F_4B_OPCODES && + !(nor->flags & SNOR_F_HAS_4BAIT)) + spi_nor_set_4byte_opcodes(nor); + + return 0; +} + +static int spi_nor_setup(struct spi_nor *nor, + const struct spi_nor_hwcaps *hwcaps) { struct spi_nor_flash_parameter *params =3D nor->params; u32 ignored_mask, shared_mask; @@ -2626,64 +2669,6 @@ static int spi_nor_default_setup(struct spi_nor *nor, return err; } =20 - return 0; -} - -static int spi_nor_set_addr_nbytes(struct spi_nor *nor) -{ - if (nor->params->addr_nbytes) { - nor->addr_nbytes =3D nor->params->addr_nbytes; - } else if (nor->read_proto =3D=3D SNOR_PROTO_8_8_8_DTR) { - /* - * In 8D-8D-8D mode, one byte takes half a cycle to transfer. So - * in this protocol an odd addr_nbytes cannot be used because - * then the address phase would only span a cycle and a half. - * Half a cycle would be left over. We would then have to start - * the dummy phase in the middle of a cycle and so too the data - * phase, and we will end the transaction with half a cycle left - * over. - * - * Force all 8D-8D-8D flashes to use an addr_nbytes of 4 to - * avoid this situation. - */ - nor->addr_nbytes =3D 4; - } else if (nor->info->addr_nbytes) { - nor->addr_nbytes =3D nor->info->addr_nbytes; - } else { - nor->addr_nbytes =3D 3; - } - - if (nor->addr_nbytes =3D=3D 3 && nor->params->size > 0x1000000) { - /* enable 4-byte addressing if the device exceeds 16MiB */ - nor->addr_nbytes =3D 4; - } - - if (nor->addr_nbytes > SPI_NOR_MAX_ADDR_NBYTES) { - dev_dbg(nor->dev, "The number of address bytes is too large: %u\n", - nor->addr_nbytes); - return -EINVAL; - } - - /* Set 4byte opcodes when possible. */ - if (nor->addr_nbytes =3D=3D 4 && nor->flags & SNOR_F_4B_OPCODES && - !(nor->flags & SNOR_F_HAS_4BAIT)) - spi_nor_set_4byte_opcodes(nor); - - return 0; -} - -static int spi_nor_setup(struct spi_nor *nor, - const struct spi_nor_hwcaps *hwcaps) -{ - int ret; - - if (nor->params->setup) - ret =3D nor->params->setup(nor, hwcaps); - else - ret =3D spi_nor_default_setup(nor, hwcaps); - if (ret) - return ret; - return spi_nor_set_addr_nbytes(nor); } =20 diff --git a/drivers/mtd/spi-nor/core.h b/drivers/mtd/spi-nor/core.h index 9aa7d6399c8a..8552e31b1b07 100644 --- a/drivers/mtd/spi-nor/core.h +++ b/drivers/mtd/spi-nor/core.h @@ -369,10 +369,6 @@ struct spi_nor_otp { * @convert_addr: converts an absolute address into something the flash * will understand. Particularly useful when pagesize= is * not a power-of-2. - * @setup: (optional) configures the SPI NOR memory. Useful for - * SPI NOR flashes that have peculiarities to the SPI NOR - * standard e.g. different opcodes, specific address - * calculation, page size, etc. * @ready: (optional) flashes might use a different mechanism * than reading the status register to indicate they * are ready for a new command @@ -404,7 +400,6 @@ struct spi_nor_flash_parameter { int (*quad_enable)(struct spi_nor *nor); int (*set_4byte_addr_mode)(struct spi_nor *nor, bool enable); u32 (*convert_addr)(struct spi_nor *nor, u32 addr); - int (*setup)(struct spi_nor *nor, const struct spi_nor_hwcaps *hwcaps); int (*ready)(struct spi_nor *nor); =20 const struct spi_nor_locking_ops *locking_ops; --=20 2.39.2 From nobody Mon Feb 9 05:52:12 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C04E685954 for ; Fri, 12 Apr 2024 13:44:25 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1712929465; cv=none; b=qVyDX63qHQlGhWsyRVNEeZItefduxxvdiophaPIJyF+3oR9tVVRiH3lXhAK9e/4BMT5jLH8j9visD1hTPOng8tL7X7XT9vmE2KGcURwLZQztYvIld0lnd8mzgN6N4V6L5wfp/tX3i9KcPgsUrzfG0Ip58UBkSb1YSl5e+2boNA0= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1712929465; c=relaxed/simple; bh=B7/0WXuNeHfB1kb629KPZ4FB30EU6w2b00Yh+4BqI5Q=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=K1MfrXTJle3k6D4AGkFl5FLM9DDI1DMa72Pc+zn2RUQzc4TLbe4FCmdrsQIWs04oya5Hk11lfbt7+nJ/WgDCC5a+WjlvkXZaqScTB6j7K1k489Uhp/pBYqBLtIOGqWqnPCQDYAoPbcUuQbH+abbkKILs3njLbSyF5yIl4aRpf8o= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=kzndw7DQ; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="kzndw7DQ" Received: by smtp.kernel.org (Postfix) with ESMTPSA id E0450C2BD11; Fri, 12 Apr 2024 13:44:23 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1712929465; bh=B7/0WXuNeHfB1kb629KPZ4FB30EU6w2b00Yh+4BqI5Q=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=kzndw7DQL4qgxyf+i/F1X6Ux4uobIQIrrUahDYPKEe/uuUdQiwNY8rkMf8YlVuaKn BJaODhv1AMqazS3IfOT5wTTawOpqvif6YS31LOmMRqD3QKVELrlEWI0Y2W54NvubhU C4+X7gQz9EZhjd+Etq3YVBUUWNAReyN5bl8djIWSsasPto7Cj8/RSdy7K7LmYOh8BL F4aOZiroGwU4dYWR7Ia3chsHv8fsJUJDoDEYHz2Fox/8Dl7e4R1HlttvXeI0nmA2zZ edOMT2eWhJop6owo34F7zDkQir/C3uUzSpYGylF608I8UXURaH0Z9yinJIQHfOH/jO 6dz+CbrPEv+hQ== From: Michael Walle To: Tudor Ambarus , Pratyush Yadav , Miquel Raynal , Richard Weinberger , Vignesh Raghavendra Cc: linux-kernel@vger.kernel.org, linux-mtd@lists.infradead.org, Michael Walle Subject: [PATCH v1 5/6] mtd: spi-nor: simplify spi_nor_get_flash_info() Date: Fri, 12 Apr 2024 15:44:04 +0200 Message-Id: <20240412134405.381832-6-mwalle@kernel.org> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20240412134405.381832-1-mwalle@kernel.org> References: <20240412134405.381832-1-mwalle@kernel.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Rework spi_nor_get_flash_info() to make it look more straight forward and esp. don't return early. The latter is a preparation to check for deprecated flashes. Signed-off-by: Michael Walle Reviewed-by: Pratyush Yadav --- drivers/mtd/spi-nor/core.c | 45 ++++++++++++++++++-------------------- 1 file changed, 21 insertions(+), 24 deletions(-) diff --git a/drivers/mtd/spi-nor/core.c b/drivers/mtd/spi-nor/core.c index bbfef7b3997f..58d310427d35 100644 --- a/drivers/mtd/spi-nor/core.c +++ b/drivers/mtd/spi-nor/core.c @@ -3311,39 +3311,36 @@ static const struct flash_info *spi_nor_match_name(= struct spi_nor *nor, static const struct flash_info *spi_nor_get_flash_info(struct spi_nor *nor, const char *name) { - const struct flash_info *info =3D NULL; + const struct flash_info *jinfo =3D NULL, *info =3D NULL; =20 if (name) info =3D spi_nor_match_name(nor, name); - /* Try to auto-detect if chip name wasn't specified or not found */ - if (!info) - return spi_nor_detect(nor); - /* - * If caller has specified name of flash model that can normally be - * detected using JEDEC, let's verify it. + * Auto-detect if chip name wasn't specified or not found, or the chip + * has an ID. If the chip supposedly has an ID, we also do an + * auto-detection to compare it later. */ - if (name && info->id) { - const struct flash_info *jinfo; - + if (!info || info->id) { jinfo =3D spi_nor_detect(nor); - if (IS_ERR(jinfo)) { + if (IS_ERR(jinfo)) return jinfo; - } else if (jinfo !=3D info) { - /* - * JEDEC knows better, so overwrite platform ID. We - * can't trust partitions any longer, but we'll let - * mtd apply them anyway, since some partitions may be - * marked read-only, and we don't want to loose that - * information, even if it's not 100% accurate. - */ - dev_warn(nor->dev, "found %s, expected %s\n", - jinfo->name, info->name); - info =3D jinfo; - } } =20 - return info; + /* + * If caller has specified name of flash model that can normally be + * detected using JEDEC, let's verify it. + */ + if (info && jinfo && jinfo !=3D info) + dev_warn(nor->dev, "found %s, expected %s\n", + jinfo->name, info->name); + + /* + * JEDEC knows better, so overwrite platform ID. We can't trust + * partitions any longer, but we'll let mtd apply them anyway, since + * some partitions may be marked read-only, and we don't want to loose + * that information, even if it's not 100% accurate. + */ + return jinfo ?: info; } =20 static u32 --=20 2.39.2 From nobody Mon Feb 9 05:52:12 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id DB4F986258 for ; Fri, 12 Apr 2024 13:44:27 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1712929467; cv=none; b=J2EayGYwQZmYnPRG/sW2huFif1K1zIoSG3FXl/mNV3qa9htCv0ym/7CfmCu9TSuxEqxl52GvvubJHNcapDpPMwYKmfUwbDcs+O2Zoa6kbBIMG2fkfLViIwApo54w1WaCj0GlzAnsdvcVMtfR9JHq5eubdVgdr+eX36518jWsvMU= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1712929467; c=relaxed/simple; bh=Hetc/oU2jZtMC9jkGVkbwuLoaws05Gs3ek4EybKWEMU=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=WLy8WXjZrUHV/vXVYrqPAWmdD2mskbhwxmdbpFMVKwsm+xNRd/+NY8hZjJFYxZmHOoqHqd4VAKNxi6ka0Ixcr/9RwY+W/zC1oim0uNxOk0TIevbRNqnqTNCg7zcagvoazhg5ySTF8IJgv7yqGY6PH/5mnpwA1fOh+ErkvrSqX70= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=h3HBauPO; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="h3HBauPO" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 123BCC2BD10; Fri, 12 Apr 2024 13:44:25 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1712929467; bh=Hetc/oU2jZtMC9jkGVkbwuLoaws05Gs3ek4EybKWEMU=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=h3HBauPOR0oPi0tOF6mEj1wDwCkaBlUi0Wq3QWcIVW9hWixJ5AS2Lk0mbuRzp/jlR WR09bQOmjRCBddX2sOdOldFbb5tO8hV48GbfdiFN38I7dFHw3k8+204OdsN8XIRyKF dKt6879LcC3LGSn/1GlzpKlGu7TLiM39ugnpnw6BviHV3Uhjy4JCvQ/Di+CUAV7OOG J4JuW05KVu7JRdIPRi5sI1YcWcfLQOiaeFVqUw4XSAhRt9tiY9wkuExoWEo7J90egI HgzcXod64yKmBDtjZ16XaiMs3vJDDjGm0L0CMB9laMEsOOIkyO4cqH9um7MoHfLYeC M3YPWXWYucP1g== From: Michael Walle To: Tudor Ambarus , Pratyush Yadav , Miquel Raynal , Richard Weinberger , Vignesh Raghavendra Cc: linux-kernel@vger.kernel.org, linux-mtd@lists.infradead.org, Michael Walle Subject: [RFC PATCH v1 6/6] mtd: spi-nor: introduce support for displaying deprecation message Date: Fri, 12 Apr 2024 15:44:05 +0200 Message-Id: <20240412134405.381832-7-mwalle@kernel.org> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20240412134405.381832-1-mwalle@kernel.org> References: <20240412134405.381832-1-mwalle@kernel.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" SPI-NOR will automatically detect the attached flash device most of the time. We cannot easily find out if boards are using a given flash. Therefore, introduce a (temporary) flag to display a message on boot if support for a given flash device is scheduled to be removed in the future. Signed-off-by: Michael Walle --- drivers/mtd/spi-nor/core.c | 12 ++++++++++++ drivers/mtd/spi-nor/core.h | 1 + 2 files changed, 13 insertions(+) diff --git a/drivers/mtd/spi-nor/core.c b/drivers/mtd/spi-nor/core.c index 58d310427d35..a294eef2e34a 100644 --- a/drivers/mtd/spi-nor/core.c +++ b/drivers/mtd/spi-nor/core.c @@ -3312,6 +3312,7 @@ static const struct flash_info *spi_nor_get_flash_inf= o(struct spi_nor *nor, const char *name) { const struct flash_info *jinfo =3D NULL, *info =3D NULL; + const char *deprecated =3D NULL; =20 if (name) info =3D spi_nor_match_name(nor, name); @@ -3326,6 +3327,17 @@ static const struct flash_info *spi_nor_get_flash_in= fo(struct spi_nor *nor, return jinfo; } =20 + if (info && (info->flags & SPI_NOR_DEPRECATED)) + deprecated =3D info->name; + else if (jinfo && (jinfo->flags & SPI_NOR_DEPRECATED)) + deprecated =3D jinfo->name; + + if (deprecated) + pr_warn("Your board or device tree is using a SPI NOR flash (%s) with\n" + "deprecated driver support. It will be removed in future kernel\n" + "version. If you feel this shouldn't be the case, please contact\n" + "us at linux-mtd@lists.infradead.org\n", deprecated); + /* * If caller has specified name of flash model that can normally be * detected using JEDEC, let's verify it. diff --git a/drivers/mtd/spi-nor/core.h b/drivers/mtd/spi-nor/core.h index 8552e31b1b07..0317d8e253f4 100644 --- a/drivers/mtd/spi-nor/core.h +++ b/drivers/mtd/spi-nor/core.h @@ -524,6 +524,7 @@ struct flash_info { #define SPI_NOR_NO_ERASE BIT(6) #define SPI_NOR_QUAD_PP BIT(8) #define SPI_NOR_RWW BIT(9) +#define SPI_NOR_DEPRECATED BIT(15) =20 u8 no_sfdp_flags; #define SPI_NOR_SKIP_SFDP BIT(0) --=20 2.39.2