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Fri, 12 Apr 2024 06:05:53 -0700 From: Sumit Gupta To: , , , , , , CC: , , , , , Subject: [Patch v3 1/2] dt-bindings: make sid and broadcast reg optional Date: Fri, 12 Apr 2024 18:35:39 +0530 Message-ID: <20240412130540.28447-2-sumitg@nvidia.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20240412130540.28447-1-sumitg@nvidia.com> References: <20240412130540.28447-1-sumitg@nvidia.com> X-NVConfidentiality: public Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SA2PEPF00001505:EE_|DS7PR12MB5933:EE_ X-MS-Office365-Filtering-Correlation-Id: aed766e2-a69f-4ced-bcb3-08dc5af1524b X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: bYNgGjcQGC9EWYGzwI7O9pERdBo/zoXW+8+VlrE5Q8n5sG/jSEJlCk3PxkOHTaQJ+fjzUqYbsJGxpLnJeuE6haULyfkFc9xteDmnRAPN7xX3iU1McW3P6pznKbqdnFpHQ9DBAQdx+6BmiuIFmbjrw8gpa0+JEhP706aIrpqF4P+OUCVQ4tI97y+B1v8dhjqwR1w0qW56uOASDWzgcFUF1AQpYDgLsuhYVA1O6f/0GsV2Emkflw7NKIr/hqBzVJs+nSv9b6E1k2HGt/z1VmOvBbrYaV2rnGGVKBALqMK9XUaCqGq63BarDDTPqd318aEvz586eq8Ate2GOvLNIKAKSiCLcMshidHk0yvi5a470Sc4heVtmsd57ne1toqBWN/4lb9cIwJkhKseENdDOAP5xCRyU3F3QjYMlsugqn4JgdJgY4Za/WdFGPdewaZ3+ZSkpfIljkyFgEpWOWCMaaZSbxkWM/EEmymbVVMYYs+mDyjH/6dgL6Jqd2K2Asv8SpZyMbyTbiNPFur2Ao5Gq6vIBUieksI/KGHoPyv2h+TKUj5UJfCDH4jHpvt6XoA0ogB3Bds5xCUh9ltprbZneASwZqOlV6hYnJJ9/pwmbqyuCGzC35Du7/7tS84ahQ04rVzeei7FzHqheMfb/iu1wxrJAhJ9yp3Eahjoa75Gri2yxHyJv3f5LYi8qVUDiM/5eG4lhA+uwFxBqWnNqnRKQbEDl/ej+ru1T1igL7Y6O2eG//lDK8AEH1TRjnbfhPr6aspH X-Forefront-Antispam-Report: CIP:216.228.118.233;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc7edge2.nvidia.com;CAT:NONE;SFS:(13230031)(82310400014)(1800799015)(376005)(36860700004);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 12 Apr 2024 13:06:09.2831 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: aed766e2-a69f-4ced-bcb3-08dc5af1524b X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.233];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: SA2PEPF00001505.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DS7PR12MB5933 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" MC SID and Broadbast channel register access is restricted for Guest VM. Make both the regions as optional for SoC's from Tegra186 onwards. Tegra MC driver will skip access to the restricted registers from Guest if the respective regions are not present in the memory-controller node of Guest DT. Suggested-by: Thierry Reding Signed-off-by: Sumit Gupta --- .../nvidia,tegra186-mc.yaml | 95 ++++++++++--------- 1 file changed, 49 insertions(+), 46 deletions(-) diff --git a/Documentation/devicetree/bindings/memory-controllers/nvidia,te= gra186-mc.yaml b/Documentation/devicetree/bindings/memory-controllers/nvidi= a,tegra186-mc.yaml index 935d63d181d9..e0bd013ecca3 100644 --- a/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra186-= mc.yaml +++ b/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra186-= mc.yaml @@ -34,11 +34,11 @@ properties: - nvidia,tegra234-mc =20 reg: - minItems: 6 + minItems: 4 maxItems: 18 =20 reg-names: - minItems: 6 + minItems: 4 maxItems: 18 =20 interrupts: @@ -151,12 +151,13 @@ allOf: =20 reg-names: items: - - const: sid - - const: broadcast - - const: ch0 - - const: ch1 - - const: ch2 - - const: ch3 + enum: + - sid + - broadcast + - ch0 + - ch1 + - ch2 + - ch3 =20 - if: properties: @@ -165,29 +166,30 @@ allOf: then: properties: reg: - minItems: 18 + minItems: 16 description: 17 memory controller channels and 1 for stream-id r= egisters =20 reg-names: items: - - const: sid - - const: broadcast - - const: ch0 - - const: ch1 - - const: ch2 - - const: ch3 - - const: ch4 - - const: ch5 - - const: ch6 - - const: ch7 - - const: ch8 - - const: ch9 - - const: ch10 - - const: ch11 - - const: ch12 - - const: ch13 - - const: ch14 - - const: ch15 + enum: + - sid + - broadcast + - ch0 + - ch1 + - ch2 + - ch3 + - ch4 + - ch5 + - ch6 + - ch7 + - ch8 + - ch9 + - ch10 + - ch11 + - ch12 + - ch13 + - ch14 + - ch15 =20 - if: properties: @@ -196,29 +198,30 @@ allOf: then: properties: reg: - minItems: 18 + minItems: 16 description: 17 memory controller channels and 1 for stream-id r= egisters =20 reg-names: items: - - const: sid - - const: broadcast - - const: ch0 - - const: ch1 - - const: ch2 - - const: ch3 - - const: ch4 - - const: ch5 - - const: ch6 - - const: ch7 - - const: ch8 - - const: ch9 - - const: ch10 - - const: ch11 - - const: ch12 - - const: ch13 - - const: ch14 - - const: ch15 + enum: + - sid + - broadcast + - ch0 + - ch1 + - ch2 + - ch3 + - ch4 + - ch5 + - ch6 + - ch7 + - ch8 + - ch9 + - ch10 + - ch11 + - ch12 + - ch13 + - ch14 + - ch15 =20 additionalProperties: false =20 --=20 2.17.1 From nobody Mon Feb 9 05:52:52 2026 Received: from NAM10-DM6-obe.outbound.protection.outlook.com (mail-dm6nam10on2047.outbound.protection.outlook.com [40.107.93.47]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id EE74A5EE78; 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X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 12 Apr 2024 13:06:16.1322 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 49dadcf5-ffff-44c4-9795-08dc5af15665 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.232];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CH1PEPF0000AD81.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CY5PR12MB6480 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" MC SID and Broadbast channel register access is restricted for Guest VM. In Tegra MC driver, consider both the regions as optional and skip access to restricted registers from Guest if a region is not present in Guest DT. Signed-off-by: Sumit Gupta --- drivers/memory/tegra/mc.c | 9 ++++++++- drivers/memory/tegra/mc.h | 22 ++++++++++++---------- drivers/memory/tegra/tegra186.c | 25 +++++++++++++------------ 3 files changed, 33 insertions(+), 23 deletions(-) diff --git a/drivers/memory/tegra/mc.c b/drivers/memory/tegra/mc.c index 224b488794e5..d819dab1b223 100644 --- a/drivers/memory/tegra/mc.c +++ b/drivers/memory/tegra/mc.c @@ -899,6 +899,7 @@ static void tegra_mc_num_channel_enabled(struct tegra_m= c *mc) =20 static int tegra_mc_probe(struct platform_device *pdev) { + struct resource *res; struct tegra_mc *mc; u64 mask; int err; @@ -923,7 +924,13 @@ static int tegra_mc_probe(struct platform_device *pdev) /* length of MC tick in nanoseconds */ mc->tick =3D 30; =20 - mc->regs =3D devm_platform_ioremap_resource(pdev, 0); + if (mc->soc->num_channels) { + res =3D platform_get_resource_byname(pdev, IORESOURCE_MEM, "sid"); + if (res) + mc->regs =3D devm_ioremap_resource(&pdev->dev, res); + } else { + mc->regs =3D devm_platform_ioremap_resource(pdev, 0); + } if (IS_ERR(mc->regs)) return PTR_ERR(mc->regs); =20 diff --git a/drivers/memory/tegra/mc.h b/drivers/memory/tegra/mc.h index c3f6655bec60..7e7bd3e09cdc 100644 --- a/drivers/memory/tegra/mc.h +++ b/drivers/memory/tegra/mc.h @@ -112,25 +112,27 @@ icc_provider_to_tegra_mc(struct icc_provider *provide= r) static inline u32 mc_ch_readl(const struct tegra_mc *mc, int ch, unsigned long offset) { - if (!mc->bcast_ch_regs) - return 0; - - if (ch =3D=3D MC_BROADCAST_CHANNEL) + if (ch =3D=3D MC_BROADCAST_CHANNEL) { + if (!mc->bcast_ch_regs) + return 0; return readl_relaxed(mc->bcast_ch_regs + offset); + } else if (mc->ch_regs) { + return readl_relaxed(mc->ch_regs[ch] + offset); + } =20 - return readl_relaxed(mc->ch_regs[ch] + offset); + return 0; } =20 static inline void mc_ch_writel(const struct tegra_mc *mc, int ch, u32 value, unsigned long offset) { - if (!mc->bcast_ch_regs) - return; - - if (ch =3D=3D MC_BROADCAST_CHANNEL) + if (ch =3D=3D MC_BROADCAST_CHANNEL) { + if (!mc->bcast_ch_regs) + return; writel_relaxed(value, mc->bcast_ch_regs + offset); - else + } else if (mc->ch_regs) { writel_relaxed(value, mc->ch_regs[ch] + offset); + } } =20 static inline u32 mc_readl(const struct tegra_mc *mc, unsigned long offset) diff --git a/drivers/memory/tegra/tegra186.c b/drivers/memory/tegra/tegra18= 6.c index 1b3183951bfe..716582255eeb 100644 --- a/drivers/memory/tegra/tegra186.c +++ b/drivers/memory/tegra/tegra186.c @@ -26,20 +26,16 @@ static int tegra186_mc_probe(struct tegra_mc *mc) { struct platform_device *pdev =3D to_platform_device(mc->dev); + struct resource *res; unsigned int i; - char name[8]; + char name[14]; int err; =20 - mc->bcast_ch_regs =3D devm_platform_ioremap_resource_byname(pdev, "broadc= ast"); - if (IS_ERR(mc->bcast_ch_regs)) { - if (PTR_ERR(mc->bcast_ch_regs) =3D=3D -EINVAL) { - dev_warn(&pdev->dev, - "Broadcast channel is missing, please update your device-tree\n"); - mc->bcast_ch_regs =3D NULL; - goto populate; - } - - return PTR_ERR(mc->bcast_ch_regs); + res =3D platform_get_resource_byname(pdev, IORESOURCE_MEM, "broadcast"); + if (res) { + mc->bcast_ch_regs =3D devm_ioremap_resource(&pdev->dev, res); + if (IS_ERR(mc->bcast_ch_regs)) + return PTR_ERR(mc->bcast_ch_regs); } =20 mc->ch_regs =3D devm_kcalloc(mc->dev, mc->soc->num_channels, sizeof(*mc->= ch_regs), @@ -55,7 +51,6 @@ static int tegra186_mc_probe(struct tegra_mc *mc) return PTR_ERR(mc->ch_regs[i]); } =20 -populate: err =3D of_platform_populate(mc->dev->of_node, NULL, NULL, mc->dev); if (err < 0) return err; @@ -121,6 +116,9 @@ static int tegra186_mc_probe_device(struct tegra_mc *mc= , struct device *dev) if (!tegra_dev_iommu_get_stream_id(dev, &sid)) return 0; =20 + if (!mc->regs) + return 0; + while (!of_parse_phandle_with_args(dev->of_node, "interconnects", "#inter= connect-cells", index, &args)) { if (args.np =3D=3D mc->dev->of_node && args.args_count !=3D 0) { @@ -146,6 +144,9 @@ static int tegra186_mc_resume(struct tegra_mc *mc) #if IS_ENABLED(CONFIG_IOMMU_API) unsigned int i; =20 + if (!mc->regs) + return 0; + for (i =3D 0; i < mc->soc->num_clients; i++) { const struct tegra_mc_client *client =3D &mc->soc->clients[i]; =20 --=20 2.17.1