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Signed-off-by: David Yang --- drivers/clk/hisilicon/clk-hi3670.c | 250 +++++++++-------------------- 1 file changed, 76 insertions(+), 174 deletions(-) diff --git a/drivers/clk/hisilicon/clk-hi3670.c b/drivers/clk/hisilicon/clk= -hi3670.c index fa20ad144c8e..b6005be71290 100644 --- a/drivers/clk/hisilicon/clk-hi3670.c +++ b/drivers/clk/hisilicon/clk-hi3670.c @@ -9,8 +9,11 @@ =20 #include #include -#include +#include +#include +#include #include + #include "clk.h" =20 static const struct hisi_fixed_rate_clock hi3670_fixed_rate_clks[] =3D { @@ -822,195 +825,94 @@ static const struct hisi_gate_clock hi3670_media2_ga= te_sep_clks[] =3D { CLK_SET_RATE_PARENT, 0x00, 2, 0, }, }; =20 -static void hi3670_clk_crgctrl_init(struct device_node *np) -{ - struct hisi_clock_data *clk_data; - - int nr =3D ARRAY_SIZE(hi3670_fixed_rate_clks) + - ARRAY_SIZE(hi3670_crgctrl_gate_sep_clks) + - ARRAY_SIZE(hi3670_crgctrl_gate_clks) + - ARRAY_SIZE(hi3670_crgctrl_mux_clks) + - ARRAY_SIZE(hi3670_crg_fixed_factor_clks) + - ARRAY_SIZE(hi3670_crgctrl_divider_clks); - - clk_data =3D hisi_clk_init(np, nr); - if (!clk_data) - return; - - hisi_clk_register_fixed_rate(hi3670_fixed_rate_clks, - ARRAY_SIZE(hi3670_fixed_rate_clks), - clk_data); - hisi_clk_register_gate_sep(hi3670_crgctrl_gate_sep_clks, - ARRAY_SIZE(hi3670_crgctrl_gate_sep_clks), - clk_data); - hisi_clk_register_gate(hi3670_crgctrl_gate_clks, - ARRAY_SIZE(hi3670_crgctrl_gate_clks), - clk_data); - hisi_clk_register_mux(hi3670_crgctrl_mux_clks, - ARRAY_SIZE(hi3670_crgctrl_mux_clks), - clk_data); - hisi_clk_register_fixed_factor(hi3670_crg_fixed_factor_clks, - ARRAY_SIZE(hi3670_crg_fixed_factor_clks), - clk_data); - hisi_clk_register_divider(hi3670_crgctrl_divider_clks, - ARRAY_SIZE(hi3670_crgctrl_divider_clks), - clk_data); -} - -static void hi3670_clk_pctrl_init(struct device_node *np) -{ - struct hisi_clock_data *clk_data; - int nr =3D ARRAY_SIZE(hi3670_pctrl_gate_clks); - - clk_data =3D hisi_clk_init(np, nr); - if (!clk_data) - return; - hisi_clk_register_gate(hi3670_pctrl_gate_clks, - ARRAY_SIZE(hi3670_pctrl_gate_clks), clk_data); -} - -static void hi3670_clk_pmuctrl_init(struct device_node *np) -{ - struct hisi_clock_data *clk_data; - int nr =3D ARRAY_SIZE(hi3670_pmu_gate_clks); - - clk_data =3D hisi_clk_init(np, nr); - if (!clk_data) - return; - - hisi_clk_register_gate(hi3670_pmu_gate_clks, - ARRAY_SIZE(hi3670_pmu_gate_clks), clk_data); -} - -static void hi3670_clk_sctrl_init(struct device_node *np) -{ - struct hisi_clock_data *clk_data; - int nr =3D ARRAY_SIZE(hi3670_sctrl_gate_sep_clks) + - ARRAY_SIZE(hi3670_sctrl_gate_clks) + - ARRAY_SIZE(hi3670_sctrl_mux_clks) + - ARRAY_SIZE(hi3670_sctrl_divider_clks); - - clk_data =3D hisi_clk_init(np, nr); - if (!clk_data) - return; - - hisi_clk_register_gate_sep(hi3670_sctrl_gate_sep_clks, - ARRAY_SIZE(hi3670_sctrl_gate_sep_clks), - clk_data); - hisi_clk_register_gate(hi3670_sctrl_gate_clks, - ARRAY_SIZE(hi3670_sctrl_gate_clks), - clk_data); - hisi_clk_register_mux(hi3670_sctrl_mux_clks, - ARRAY_SIZE(hi3670_sctrl_mux_clks), - clk_data); - hisi_clk_register_divider(hi3670_sctrl_divider_clks, - ARRAY_SIZE(hi3670_sctrl_divider_clks), - clk_data); -} - -static void hi3670_clk_iomcu_init(struct device_node *np) -{ - struct hisi_clock_data *clk_data; - int nr =3D ARRAY_SIZE(hi3670_iomcu_gate_sep_clks) + - ARRAY_SIZE(hi3670_iomcu_fixed_factor_clks); - - clk_data =3D hisi_clk_init(np, nr); - if (!clk_data) - return; - - hisi_clk_register_gate(hi3670_iomcu_gate_sep_clks, - ARRAY_SIZE(hi3670_iomcu_gate_sep_clks), clk_data); - - hisi_clk_register_fixed_factor(hi3670_iomcu_fixed_factor_clks, - ARRAY_SIZE(hi3670_iomcu_fixed_factor_clks), - clk_data); -} - -static void hi3670_clk_media1_init(struct device_node *np) -{ - struct hisi_clock_data *clk_data; - - int nr =3D ARRAY_SIZE(hi3670_media1_gate_sep_clks) + - ARRAY_SIZE(hi3670_media1_gate_clks) + - ARRAY_SIZE(hi3670_media1_mux_clks) + - ARRAY_SIZE(hi3670_media1_divider_clks); - - clk_data =3D hisi_clk_init(np, nr); - if (!clk_data) - return; - - hisi_clk_register_gate_sep(hi3670_media1_gate_sep_clks, - ARRAY_SIZE(hi3670_media1_gate_sep_clks), - clk_data); - hisi_clk_register_gate(hi3670_media1_gate_clks, - ARRAY_SIZE(hi3670_media1_gate_clks), - clk_data); - hisi_clk_register_mux(hi3670_media1_mux_clks, - ARRAY_SIZE(hi3670_media1_mux_clks), - clk_data); - hisi_clk_register_divider(hi3670_media1_divider_clks, - ARRAY_SIZE(hi3670_media1_divider_clks), - clk_data); -} - -static void hi3670_clk_media2_init(struct device_node *np) -{ - struct hisi_clock_data *clk_data; - - int nr =3D ARRAY_SIZE(hi3670_media2_gate_sep_clks); - - clk_data =3D hisi_clk_init(np, nr); - if (!clk_data) - return; - - hisi_clk_register_gate_sep(hi3670_media2_gate_sep_clks, - ARRAY_SIZE(hi3670_media2_gate_sep_clks), - clk_data); -} +static const struct hisi_clocks hi3670_clk_crgctrl_clks =3D { + .fixed_rate_clks =3D hi3670_fixed_rate_clks, + .fixed_rate_clks_num =3D ARRAY_SIZE(hi3670_fixed_rate_clks), + .fixed_factor_clks =3D hi3670_crg_fixed_factor_clks, + .fixed_factor_clks_num =3D ARRAY_SIZE(hi3670_crg_fixed_factor_clks), + .mux_clks =3D hi3670_crgctrl_mux_clks, + .mux_clks_num =3D ARRAY_SIZE(hi3670_crgctrl_mux_clks), + .divider_clks =3D hi3670_crgctrl_divider_clks, + .divider_clks_num =3D ARRAY_SIZE(hi3670_crgctrl_divider_clks), + .gate_clks =3D hi3670_crgctrl_gate_clks, + .gate_clks_num =3D ARRAY_SIZE(hi3670_crgctrl_gate_clks), + .gate_sep_clks =3D hi3670_crgctrl_gate_sep_clks, + .gate_sep_clks_num =3D ARRAY_SIZE(hi3670_crgctrl_gate_sep_clks), +}; + +static const struct hisi_clocks hi3670_clk_pctrl_clks =3D { + .gate_clks =3D hi3670_pctrl_gate_clks, + .gate_clks_num =3D ARRAY_SIZE(hi3670_pctrl_gate_clks), +}; + +static const struct hisi_clocks hi3670_clk_pmuctrl_clks =3D { + .gate_clks =3D hi3670_pmu_gate_clks, + .gate_clks_num =3D ARRAY_SIZE(hi3670_pmu_gate_clks), +}; + +static const struct hisi_clocks hi3670_clk_sctrl_clks =3D { + .mux_clks =3D hi3670_sctrl_mux_clks, + .mux_clks_num =3D ARRAY_SIZE(hi3670_sctrl_mux_clks), + .divider_clks =3D hi3670_sctrl_divider_clks, + .divider_clks_num =3D ARRAY_SIZE(hi3670_sctrl_divider_clks), + .gate_clks =3D hi3670_sctrl_gate_clks, + .gate_clks_num =3D ARRAY_SIZE(hi3670_sctrl_gate_clks), + .gate_sep_clks =3D hi3670_sctrl_gate_sep_clks, + .gate_sep_clks_num =3D ARRAY_SIZE(hi3670_sctrl_gate_sep_clks), +}; + +static const struct hisi_clocks hi3670_clk_iomcu_clks =3D { + .fixed_factor_clks =3D hi3670_iomcu_fixed_factor_clks, + .fixed_factor_clks_num =3D ARRAY_SIZE(hi3670_iomcu_fixed_factor_clks), + .gate_clks =3D hi3670_iomcu_gate_sep_clks, + .gate_clks_num =3D ARRAY_SIZE(hi3670_iomcu_gate_sep_clks), +}; + +static const struct hisi_clocks hi3670_clk_media1_clks =3D { + .mux_clks =3D hi3670_media1_mux_clks, + .mux_clks_num =3D ARRAY_SIZE(hi3670_media1_mux_clks), + .divider_clks =3D hi3670_media1_divider_clks, + .divider_clks_num =3D ARRAY_SIZE(hi3670_media1_divider_clks), + .gate_clks =3D hi3670_media1_gate_clks, + .gate_clks_num =3D ARRAY_SIZE(hi3670_media1_gate_clks), + .gate_sep_clks =3D hi3670_media1_gate_sep_clks, + .gate_sep_clks_num =3D ARRAY_SIZE(hi3670_media1_gate_sep_clks), +}; + +static const struct hisi_clocks hi3670_clk_media2_clks =3D { + .gate_sep_clks =3D hi3670_media2_gate_sep_clks, + .gate_sep_clks_num =3D ARRAY_SIZE(hi3670_media2_gate_sep_clks), +}; =20 static const struct of_device_id hi3670_clk_match_table[] =3D { { .compatible =3D "hisilicon,hi3670-crgctrl", - .data =3D hi3670_clk_crgctrl_init }, + .data =3D &hi3670_clk_crgctrl_clks }, { .compatible =3D "hisilicon,hi3670-pctrl", - .data =3D hi3670_clk_pctrl_init }, + .data =3D &hi3670_clk_pctrl_clks }, { .compatible =3D "hisilicon,hi3670-pmuctrl", - .data =3D hi3670_clk_pmuctrl_init }, + .data =3D &hi3670_clk_pmuctrl_clks }, { .compatible =3D "hisilicon,hi3670-sctrl", - .data =3D hi3670_clk_sctrl_init }, + .data =3D &hi3670_clk_sctrl_clks }, { .compatible =3D "hisilicon,hi3670-iomcu", - .data =3D hi3670_clk_iomcu_init }, + .data =3D &hi3670_clk_iomcu_clks }, { .compatible =3D "hisilicon,hi3670-media1-crg", - .data =3D hi3670_clk_media1_init }, + .data =3D &hi3670_clk_media1_clks }, { .compatible =3D "hisilicon,hi3670-media2-crg", - .data =3D hi3670_clk_media2_init }, + .data =3D &hi3670_clk_media2_clks }, { } }; - -static int hi3670_clk_probe(struct platform_device *pdev) -{ - struct device *dev =3D &pdev->dev; - struct device_node *np =3D pdev->dev.of_node; - void (*init_func)(struct device_node *np); - - init_func =3D of_device_get_match_data(dev); - if (!init_func) - return -ENODEV; - - init_func(np); - - return 0; -} +MODULE_DEVICE_TABLE(of, hi3670_clk_match_table); =20 static struct platform_driver hi3670_clk_driver =3D { - .probe =3D hi3670_clk_probe, + .probe =3D hisi_clk_probe, + .remove_new =3D hisi_clk_remove, .driver =3D { .name =3D "hi3670-clk", .of_match_table =3D hi3670_clk_match_table, }, }; =20 -static int __init hi3670_clk_init(void) -{ - return platform_driver_register(&hi3670_clk_driver); -} -core_initcall(hi3670_clk_init); +module_platform_driver(hi3670_clk_driver); + +MODULE_LICENSE("GPL v2"); +MODULE_DESCRIPTION("HiSilicon Hi3670 Clock Driver"); --=20 2.43.0