From nobody Tue Feb 10 04:13:28 2026 Received: from mx0a-00128a01.pphosted.com (mx0a-00128a01.pphosted.com [148.163.135.77]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id BFE771C29F; Fri, 12 Apr 2024 03:21:57 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=148.163.135.77 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1712892119; cv=none; b=mnCyRct8+oCC7I0nllOH1v7I83jbxdof8egFgercdcfi3fV91fe8uJ8gm7pnRNAWe9sV/qfEuGIEj/vGSqXqM6ApxDZpzpkqsHOLQmuK04xceDKOgdrx33xzLWIXbc87lB/Zf8J2gm11j5bYsfIUnHwVQ0I3g3Cr/mohWXau7cU= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1712892119; c=relaxed/simple; bh=AKPe30Lkkb2ALaF3MpW3QAR6qGafn8d626/Wc/B6FjI=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=iLWsg9xMXFOBSgt+bbZULd0e9fC6wxntsLAdgUHPM19hyGhN6bWvPvW03fba1bV/8Jg1d6RsN8BpZKtpYTMxDC0C6fVvlAlsr7AFweJPxqMyhrFdHc0JARVcBJSHH8ZrJ+YPJWoVPS0J+z4FAcQ/Cnp1uVIJ5N3esFOcu7lYrUY= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=analog.com; spf=pass smtp.mailfrom=analog.com; dkim=pass (2048-bit key) header.d=analog.com header.i=@analog.com header.b=Yy0K3BTg; arc=none smtp.client-ip=148.163.135.77 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=analog.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=analog.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=analog.com header.i=@analog.com header.b="Yy0K3BTg" Received: from pps.filterd (m0167089.ppops.net [127.0.0.1]) by mx0a-00128a01.pphosted.com (8.17.1.24/8.17.1.24) with ESMTP id 43C2Ov8t017716; Thu, 11 Apr 2024 23:21:41 -0400 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=analog.com; h= from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-type:content-transfer-encoding; s=DKIM; bh=a4Mul6E1bdinbHUPpudcNBMMnS1YS7YiBaHomYCsbY0=; b=Yy0K3BTgsNhs Vc6ZF9Jus/XQ5ZhDtyA+WuHB7ljf2MkyeaDHXxzYDuKsOnnr9E5B9/B9jfhTqaQW UHXwl9EviZy1jdC+m+BN380exYA//i5it1Hu96AFx7UB/pEtyMz3/oP+4FG0rb0n rnapq6bFD46pPstbYJvB0Uws87b6r8MTj/77+je3m99ozlL74bePfajx/f7OJiNx qZ+qsL1oYK4KZwdQ/88LBOIIqr4QXDEBsb7DimjwciA+IRvbx5+SurIrsW+DKLKN /i0IhZ48Y8tEuJAgK4FiNIVmx1wXJpT79BetcrPLAgMtSkM4APx4pG1lmPvNoXr0 CgkCzx9Ysw== Received: from nwd2mta3.analog.com ([137.71.173.56]) by mx0a-00128a01.pphosted.com (PPS) with ESMTPS id 3xek1et81e-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 11 Apr 2024 23:21:40 -0400 (EDT) Received: from ASHBMBX9.ad.analog.com (ASHBMBX9.ad.analog.com [10.64.17.10]) by nwd2mta3.analog.com (8.14.7/8.14.7) with ESMTP id 43C3LdKH021590 (version=TLSv1/SSLv3 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=FAIL); Thu, 11 Apr 2024 23:21:39 -0400 Received: from ASHBCASHYB4.ad.analog.com (10.64.17.132) by ASHBMBX9.ad.analog.com (10.64.17.10) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.14; Thu, 11 Apr 2024 23:21:38 -0400 Received: from ASHBMBX8.ad.analog.com (10.64.17.5) by ASHBCASHYB4.ad.analog.com (10.64.17.132) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.14; Thu, 11 Apr 2024 23:21:38 -0400 Received: from zeus.spd.analog.com (10.66.68.11) by ashbmbx8.ad.analog.com (10.64.17.5) with Microsoft SMTP Server id 15.2.986.14 via Frontend Transport; Thu, 11 Apr 2024 23:21:38 -0400 Received: from kim-VirtualBox.ad.analog.com (KPALLER2-L03.ad.analog.com [10.117.220.36]) by zeus.spd.analog.com (8.15.1/8.15.1) with ESMTP id 43C3L8pi021230; Thu, 11 Apr 2024 23:21:32 -0400 From: Kim Seer Paller To: , , CC: Jonathan Cameron , Lars-Peter Clausen , Rob Herring , Krzysztof Kozlowski , Conor Dooley , "Liam Girdwood" , Mark Brown , "David Lechner" , Michael Hennerich Subject: [PATCH 4/4] iio: dac: ltc2664: Add driver for LTC2664 and LTC2672 Date: Fri, 12 Apr 2024 11:21:02 +0800 Message-ID: <20240412032102.136071-5-kimseer.paller@analog.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240412032102.136071-1-kimseer.paller@analog.com> References: <20240412032102.136071-1-kimseer.paller@analog.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ADIRuleOP-NewSCL: Rule Triggered X-Proofpoint-ORIG-GUID: wPLmqIIC7UZmU9zH3468uIz8zTZU-xQ9 X-Proofpoint-GUID: wPLmqIIC7UZmU9zH3468uIz8zTZU-xQ9 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.272,Aquarius:18.0.1011,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2024-04-11_14,2024-04-09_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 spamscore=0 impostorscore=0 bulkscore=0 mlxscore=0 clxscore=1015 suspectscore=0 phishscore=0 priorityscore=1501 malwarescore=0 lowpriorityscore=0 mlxlogscore=999 adultscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2404010003 definitions=main-2404120023 LTC2664 4 channel, 16 bit Voltage Output SoftSpan DAC LTC2672 5 channel, 16 bit Current Output Softspan DAC Co-developed-by: Michael Hennerich Signed-off-by: Michael Hennerich Signed-off-by: Kim Seer Paller --- MAINTAINERS | 1 + drivers/iio/dac/Kconfig | 11 + drivers/iio/dac/Makefile | 1 + drivers/iio/dac/ltc2664.c | 785 ++++++++++++++++++++++++++++++++++++++ 4 files changed, 798 insertions(+) create mode 100644 drivers/iio/dac/ltc2664.c diff --git a/MAINTAINERS b/MAINTAINERS index fba8bacc0..9b5c3d6d1 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -12845,6 +12845,7 @@ W: https://ez.analog.com/linux-software-drivers F: Documentation/ABI/testing/sysfs-bus-iio-dac-ltc2664 F: Documentation/ABI/testing/sysfs-bus-iio-dac-ltc2672 F: Documentation/devicetree/bindings/iio/dac/adi,ltc2664.yaml +F: drivers/iio/dac/ltc2664.c =20 LTC2688 IIO DAC DRIVER M: Nuno S=C3=A1 diff --git a/drivers/iio/dac/Kconfig b/drivers/iio/dac/Kconfig index 34eb40bb9..79b7a547e 100644 --- a/drivers/iio/dac/Kconfig +++ b/drivers/iio/dac/Kconfig @@ -333,6 +333,17 @@ config LTC2632 To compile this driver as a module, choose M here: the module will be called ltc2632. =20 +config LTC2664 + tristate "Analog Devices LTC2664 and LTC2672 DAC SPI driver" + depends on SPI + select REGMAP + help + Say yes here to build support for Analog Devices + LTC2664 and LTC2672 converters (DAC). + + To compile this driver as a module, choose M here: the + module will be called ltc2664. + config M62332 tristate "Mitsubishi M62332 DAC driver" depends on I2C diff --git a/drivers/iio/dac/Makefile b/drivers/iio/dac/Makefile index 55bf89739..62df8d7e4 100644 --- a/drivers/iio/dac/Makefile +++ b/drivers/iio/dac/Makefile @@ -35,6 +35,7 @@ obj-$(CONFIG_DS4424) +=3D ds4424.o obj-$(CONFIG_LPC18XX_DAC) +=3D lpc18xx_dac.o obj-$(CONFIG_LTC1660) +=3D ltc1660.o obj-$(CONFIG_LTC2632) +=3D ltc2632.o +obj-$(CONFIG_LTC2664) +=3D ltc2664.o obj-$(CONFIG_LTC2688) +=3D ltc2688.o obj-$(CONFIG_M62332) +=3D m62332.o obj-$(CONFIG_MAX517) +=3D max517.o diff --git a/drivers/iio/dac/ltc2664.c b/drivers/iio/dac/ltc2664.c new file mode 100644 index 000000000..70c43fe17 --- /dev/null +++ b/drivers/iio/dac/ltc2664.c @@ -0,0 +1,785 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * LTC2664 4 channel, 16 bit Voltage Output SoftSpan DAC driver + * LTC2672 5 channel, 16 bit Current Output Softspan DAC driver + * + * Copyright 2024 Analog Devices Inc. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define LTC2664_CMD_WRITE_N(n) (0x00 + (n)) +#define LTC2664_CMD_UPDATE_N(n) (0x10 + (n)) +#define LTC2664_CMD_WRITE_N_UPDATE_ALL 0x20 +#define LTC2664_CMD_WRITE_N_UPDATE_N(n) (0x30 + (n)) +#define LTC2664_CMD_POWER_DOWN_N(n) (0x40 + (n)) +#define LTC2664_CMD_POWER_DOWN_ALL 0x50 +#define LTC2664_CMD_SPAN_N(n) (0x60 + (n)) +#define LTC2664_CMD_CONFIG 0x70 +#define LTC2664_CMD_MUX 0xB0 +#define LTC2664_CMD_TOGGLE_SEL 0xC0 +#define LTC2664_CMD_GLOBAL_TOGGLE 0xD0 +#define LTC2664_CMD_NO_OPERATION 0xF0 +#define LTC2664_REF_DISABLE 0x0001 +#define LTC2664_MSPAN_SOFTSPAN 7 + +#define LTC2672_MAX_CHANNEL 5 +#define LTC2672_MAX_SPAN 7 +#define LTC2672_OFFSET_CODE 384 +#define LTC2672_SCALE_MULTIPLIER(n) (50 * BIT(n)) + +enum ltc2664_ids { + LTC2664, + LTC2672, +}; + +enum { + LTC2664_SPAN_RANGE_0V_5V, + LTC2664_SPAN_RANGE_0V_10V, + LTC2664_SPAN_RANGE_M5V_5V, + LTC2664_SPAN_RANGE_M10V_10V, + LTC2664_SPAN_RANGE_M2V5_2V5, +}; + +enum { + LTC2664_INPUT_A, + LTC2664_INPUT_B, + LTC2664_INPUT_B_AVAIL, + LTC2664_POWERDOWN, + LTC2664_TOGGLE_EN, + LTC2664_GLOBAL_TOGGLE, +}; + +static const u16 ltc2664_mspan_lut[8][2] =3D { + {LTC2664_SPAN_RANGE_M10V_10V, 32768}, /* MPS2=3D0, MPS1=3D0, MSP0=3D0 (0)= */ + {LTC2664_SPAN_RANGE_M5V_5V, 32768}, /* MPS2=3D0, MPS1=3D0, MSP0=3D1 (1)*/ + {LTC2664_SPAN_RANGE_M2V5_2V5, 32768}, /* MPS2=3D0, MPS1=3D1, MSP0=3D0 (2)= */ + {LTC2664_SPAN_RANGE_0V_10V, 0}, /* MPS2=3D0, MPS1=3D1, MSP0=3D1 (3)*/ + {LTC2664_SPAN_RANGE_0V_10V, 32768}, /* MPS2=3D1, MPS1=3D0, MSP0=3D0 (4)*/ + {LTC2664_SPAN_RANGE_0V_5V, 0}, /* MPS2=3D1, MPS1=3D0, MSP0=3D1 (5)*/ + {LTC2664_SPAN_RANGE_0V_5V, 32768}, /* MPS2=3D1, MPS1=3D1, MSP0=3D0 (6)*/ + {LTC2664_SPAN_RANGE_0V_5V, 0} /* MPS2=3D1, MPS1=3D1, MSP0=3D1 (7)*/ +}; + +struct ltc2664_chip_info { + enum ltc2664_ids id; + const char *name; + unsigned int num_channels; + const struct iio_chan_spec *iio_chan; + const int (*span_helper)[2]; + unsigned int num_span; +}; + +struct ltc2664_chan { + bool toggle_chan; + bool powerdown; + u8 span; + u16 raw[2]; /* A/B */ +}; + +struct ltc2664_state { + struct spi_device *spi; + struct regmap *regmap; + struct ltc2664_chan channels[LTC2672_MAX_CHANNEL]; + /* lock to protect against multiple access to the device and shared data = */ + struct mutex lock; + const struct ltc2664_chip_info *chip_info; + struct iio_chan_spec *iio_channels; + int vref; + u32 toggle_sel; + u32 global_toggle; + u32 rfsadj; +}; + +static const int ltc2664_span_helper[][2] =3D { + {0, 5000}, {0, 10000}, {-5000, 5000}, {-10000, 10000}, {-2500, 2500}, +}; + +static const int ltc2672_span_helper[][2] =3D { + {0, 3125}, {0, 6250}, {0, 12500}, {0, 25000}, {0, 50000}, {0, 100000}, + {0, 200000}, {0, 300000}, +}; + +static int ltc2664_scale_get(const struct ltc2664_state *st, int c, int *v= al) +{ + const struct ltc2664_chan *chan =3D &st->channels[c]; + const int (*span_helper)[2] =3D st->chip_info->span_helper; + int span, fs; + + span =3D chan->span; + if (span < 0) + return span; + + switch (st->chip_info->id) { + case LTC2664: + fs =3D span_helper[span][1] - span_helper[span][0]; + + if (st->vref) + *val =3D (fs / 2500) * st->vref; + else + *val =3D fs; + + return 0; + case LTC2672: + if (span =3D=3D LTC2672_MAX_SPAN) + *val =3D 4800 * (1000 * st->vref / st->rfsadj); + else + *val =3D LTC2672_SCALE_MULTIPLIER(span) * + (1000 * st->vref / st->rfsadj); + + return 0; + default: + return -EINVAL; + } +} + +static int ltc2664_offset_get(const struct ltc2664_state *st, int c, int *= val) +{ + const struct ltc2664_chan *chan =3D &st->channels[c]; + int span; + + span =3D chan->span; + if (span < 0) + return span; + + if (st->chip_info->span_helper[span][0] < 0) + *val =3D -32768; + else if (chan->raw[0] >=3D LTC2672_OFFSET_CODE || + chan->raw[1] >=3D LTC2672_OFFSET_CODE) + *val =3D st->chip_info->span_helper[1][span] / 250; + else + *val =3D 0; + + return 0; +} + +static int ltc2664_dac_code_write(struct ltc2664_state *st, u32 chan, u32 = input, + u16 code) +{ + struct ltc2664_chan *c =3D &st->channels[chan]; + int ret, reg; + + guard(mutex)(&st->lock); + /* select the correct input register to write to */ + if (c->toggle_chan) { + ret =3D regmap_write(st->regmap, LTC2664_CMD_TOGGLE_SEL, + input << chan); + if (ret) + return ret; + } + /* + * If in toggle mode the dac should be updated by an + * external signal (or sw toggle) and not here. + */ + if (st->toggle_sel & BIT(chan)) + reg =3D LTC2664_CMD_WRITE_N(chan); + else + reg =3D LTC2664_CMD_WRITE_N_UPDATE_N(chan); + + ret =3D regmap_write(st->regmap, reg, code); + if (ret) + return ret; + + c->raw[input] =3D code; + + if (c->toggle_chan) { + ret =3D regmap_write(st->regmap, LTC2664_CMD_TOGGLE_SEL, + st->toggle_sel); + if (ret) + return ret; + } + + return ret; +} + +static int ltc2664_dac_code_read(struct ltc2664_state *st, u32 chan, u32 i= nput, + u32 *code) +{ + guard(mutex)(&st->lock); + *code =3D st->channels[chan].raw[input]; + + return 0; +} + +static const int ltc2664_raw_range[] =3D {0, 1, U16_MAX}; + +static int ltc2664_read_avail(struct iio_dev *indio_dev, + struct iio_chan_spec const *chan, + const int **vals, int *type, int *length, + long info) +{ + switch (info) { + case IIO_CHAN_INFO_RAW: + *vals =3D ltc2664_raw_range; + *type =3D IIO_VAL_INT; + + return IIO_AVAIL_RANGE; + default: + return -EINVAL; + } +} + +static int ltc2664_read_raw(struct iio_dev *indio_dev, + struct iio_chan_spec const *chan, int *val, + int *val2, long info) +{ + struct ltc2664_state *st =3D iio_priv(indio_dev); + int ret; + + switch (info) { + case IIO_CHAN_INFO_RAW: + ret =3D ltc2664_dac_code_read(st, chan->channel, + LTC2664_INPUT_A, val); + if (ret) + return ret; + + return IIO_VAL_INT; + case IIO_CHAN_INFO_OFFSET: + ret =3D ltc2664_offset_get(st, chan->channel, val); + if (ret) + return ret; + + return IIO_VAL_INT; + case IIO_CHAN_INFO_SCALE: + ret =3D ltc2664_scale_get(st, chan->channel, val); + if (ret) + return ret; + + *val2 =3D 16; + + return IIO_VAL_FRACTIONAL_LOG2; + default: + return -EINVAL; + } +} + +static int ltc2664_write_raw(struct iio_dev *indio_dev, + struct iio_chan_spec const *chan, int val, + int val2, long info) +{ + struct ltc2664_state *st =3D iio_priv(indio_dev); + + switch (info) { + case IIO_CHAN_INFO_RAW: + if (val > U16_MAX || val < 0) + return -EINVAL; + + return ltc2664_dac_code_write(st, chan->channel, + LTC2664_INPUT_A, val); + default: + return -EINVAL; + } +} + +static ssize_t ltc2664_reg_bool_get(struct iio_dev *indio_dev, + uintptr_t private, + const struct iio_chan_spec *chan, + char *buf) +{ + struct ltc2664_state *st =3D iio_priv(indio_dev); + u32 val; + + guard(mutex)(&st->lock); + switch (private) { + case LTC2664_POWERDOWN: + val =3D st->channels[chan->channel].powerdown; + + return sysfs_emit(buf, "%u\n", val); + case LTC2664_TOGGLE_EN: + val =3D !!(st->toggle_sel & BIT(chan->channel)); + + return sysfs_emit(buf, "%u\n", val); + case LTC2664_GLOBAL_TOGGLE: + val =3D st->global_toggle; + + return sysfs_emit(buf, "%u\n", val); + default: + return -EINVAL; + } +} + +static ssize_t ltc2664_reg_bool_set(struct iio_dev *indio_dev, + uintptr_t private, + const struct iio_chan_spec *chan, + const char *buf, size_t len) +{ + struct ltc2664_state *st =3D iio_priv(indio_dev); + int ret; + bool en; + + ret =3D kstrtobool(buf, &en); + if (ret) + return ret; + + guard(mutex)(&st->lock); + switch (private) { + case LTC2664_POWERDOWN: + ret =3D regmap_write(st->regmap, + en ? LTC2664_CMD_POWER_DOWN_N(chan->channel) : + LTC2664_CMD_UPDATE_N(chan->channel), en); + if (ret) + return ret; + + st->channels[chan->channel].powerdown =3D en; + + return len; + case LTC2664_TOGGLE_EN: + if (en) + st->toggle_sel |=3D BIT(chan->channel); + else + st->toggle_sel &=3D ~BIT(chan->channel); + + ret =3D regmap_write(st->regmap, LTC2664_CMD_TOGGLE_SEL, + st->toggle_sel); + if (ret) + return ret; + + return len; + case LTC2664_GLOBAL_TOGGLE: + ret =3D regmap_write(st->regmap, LTC2664_CMD_GLOBAL_TOGGLE, en); + if (ret) + return ret; + + st->global_toggle =3D en; + + return len; + default: + return -EINVAL; + } +} + +static ssize_t ltc2664_dac_input_read(struct iio_dev *indio_dev, + uintptr_t private, + const struct iio_chan_spec *chan, + char *buf) +{ + struct ltc2664_state *st =3D iio_priv(indio_dev); + int ret; + u32 val; + + if (private =3D=3D LTC2664_INPUT_B_AVAIL) + return sysfs_emit(buf, "[%u %u %u]\n", ltc2664_raw_range[0], + ltc2664_raw_range[1], + ltc2664_raw_range[2] / 4); + + ret =3D ltc2664_dac_code_read(st, chan->channel, private, &val); + if (ret) + return ret; + + return sysfs_emit(buf, "%u\n", val); +} + +static ssize_t ltc2664_dac_input_write(struct iio_dev *indio_dev, + uintptr_t private, + const struct iio_chan_spec *chan, + const char *buf, size_t len) +{ + struct ltc2664_state *st =3D iio_priv(indio_dev); + int ret; + u16 val; + + if (private =3D=3D LTC2664_INPUT_B_AVAIL) + return -EINVAL; + + ret =3D kstrtou16(buf, 10, &val); + if (ret) + return ret; + + ret =3D ltc2664_dac_code_write(st, chan->channel, private, val); + if (ret) + return ret; + + return len; +} + +static int ltc2664_reg_access(struct iio_dev *indio_dev, + unsigned int reg, + unsigned int writeval, + unsigned int *readval) +{ + struct ltc2664_state *st =3D iio_priv(indio_dev); + + if (readval) + return -EOPNOTSUPP; + + return regmap_write(st->regmap, reg, writeval); +} + +#define LTC2664_CHAN_EXT_INFO(_name, _what, _shared, _read, _write) { \ + .name =3D _name, \ + .read =3D (_read), \ + .write =3D (_write), \ + .private =3D (_what), \ + .shared =3D (_shared), \ +} + +/* + * For toggle mode we only expose the symbol attr (sw_toggle) in case a TG= Px is + * not provided in dts. + */ +static const struct iio_chan_spec_ext_info ltc2664_toggle_sym_ext_info[] = =3D { + LTC2664_CHAN_EXT_INFO("raw0", LTC2664_INPUT_A, IIO_SEPARATE, + ltc2664_dac_input_read, ltc2664_dac_input_write), + LTC2664_CHAN_EXT_INFO("raw1", LTC2664_INPUT_B, IIO_SEPARATE, + ltc2664_dac_input_read, ltc2664_dac_input_write), + LTC2664_CHAN_EXT_INFO("powerdown", LTC2664_POWERDOWN, IIO_SEPARATE, + ltc2664_reg_bool_get, ltc2664_reg_bool_set), + LTC2664_CHAN_EXT_INFO("symbol", LTC2664_GLOBAL_TOGGLE, IIO_SEPARATE, + ltc2664_reg_bool_get, ltc2664_reg_bool_set), + LTC2664_CHAN_EXT_INFO("toggle_en", LTC2664_TOGGLE_EN, + IIO_SEPARATE, ltc2664_reg_bool_get, + ltc2664_reg_bool_set), + {} +}; + +static const struct iio_chan_spec_ext_info ltc2664_ext_info[] =3D { + LTC2664_CHAN_EXT_INFO("powerdown", LTC2664_POWERDOWN, IIO_SEPARATE, + ltc2664_reg_bool_get, ltc2664_reg_bool_set), + {} +}; + +#define LTC2664_CHANNEL(_chan) { \ + .indexed =3D 1, \ + .output =3D 1, \ + .channel =3D (_chan), \ + .info_mask_separate =3D BIT(IIO_CHAN_INFO_SCALE) | \ + BIT(IIO_CHAN_INFO_OFFSET) | BIT(IIO_CHAN_INFO_RAW), \ + .info_mask_separate_available =3D BIT(IIO_CHAN_INFO_RAW), \ + .ext_info =3D ltc2664_ext_info, \ +} + +static const struct iio_chan_spec ltc2664_channels[] =3D { + LTC2664_CHANNEL(0), + LTC2664_CHANNEL(1), + LTC2664_CHANNEL(2), + LTC2664_CHANNEL(3), +}; + +static const struct iio_chan_spec ltc2672_channels[] =3D { + LTC2664_CHANNEL(0), + LTC2664_CHANNEL(1), + LTC2664_CHANNEL(2), + LTC2664_CHANNEL(3), + LTC2664_CHANNEL(4), +}; + +static const struct ltc2664_chip_info ltc2664_chip =3D { + .id =3D LTC2664, + .name =3D "ltc2664", + .num_channels =3D ARRAY_SIZE(ltc2664_channels), + .iio_chan =3D ltc2664_channels, + .span_helper =3D ltc2664_span_helper, + .num_span =3D ARRAY_SIZE(ltc2664_span_helper), +}; + +static const struct ltc2664_chip_info ltc2672_chip =3D { + .id =3D LTC2672, + .name =3D "ltc2672", + .num_channels =3D ARRAY_SIZE(ltc2672_channels), + .iio_chan =3D ltc2672_channels, + .span_helper =3D ltc2672_span_helper, + .num_span =3D ARRAY_SIZE(ltc2672_span_helper), +}; + +static int ltc2664_span_lookup(const struct ltc2664_state *st, int min, in= t max) +{ + const int (*span_helper)[2] =3D st->chip_info->span_helper; + int span; + + for (span =3D 0; span < st->chip_info->num_span; span++) { + if (min =3D=3D span_helper[span][0] && max =3D=3D span_helper[span][1]) + return span; + } + + return -EINVAL; +} + +static int ltc2664_channel_config(struct ltc2664_state *st) +{ + const struct ltc2664_chip_info *chip_info =3D st->chip_info; + struct device *dev =3D &st->spi->dev; + u32 reg, tmp[2], mspan; + int ret, span; + + mspan =3D LTC2664_MSPAN_SOFTSPAN; + ret =3D device_property_read_u32(dev, "adi,manual-span-operation-config", + &mspan); + if (!ret) { + if (chip_info->id !=3D LTC2664) + return dev_err_probe(dev, -EINVAL, + "adi,manual-span-operation-config not supported\n"); + + if (mspan > ARRAY_SIZE(ltc2664_mspan_lut)) + return dev_err_probe(dev, -EINVAL, + "adi,manual-span-operation-config not in range\n"); + } + + st->rfsadj =3D 20000; + ret =3D device_property_read_u32(dev, "adi,rfsadj-ohms", &st->rfsadj); + if (!ret) { + if (chip_info->id !=3D LTC2672) + return dev_err_probe(dev, -EINVAL, + "adi,rfsadj-ohms not supported\n"); + + if ((st->rfsadj < 19000 || st->rfsadj > 41000) || + chip_info->id !=3D LTC2672) + return dev_err_probe(dev, -EINVAL, + "adi,rfsadj-ohms not in range\n"); + } + + device_for_each_child_node_scoped(dev, child) { + struct ltc2664_chan *chan; + + ret =3D fwnode_property_read_u32(child, "reg", ®); + if (ret) + return dev_err_probe(dev, ret, + "Failed to get reg property\n"); + + if (reg >=3D chip_info->num_channels) + return dev_err_probe(dev, -EINVAL, + "reg bigger than: %d\n", + chip_info->num_channels); + + chan =3D &st->channels[reg]; + + if (fwnode_property_read_bool(child, "adi,toggle-mode")) { + chan->toggle_chan =3D true; + /* assume sw toggle ABI */ + st->iio_channels[reg].ext_info =3D ltc2664_toggle_sym_ext_info; + /* + * Clear IIO_CHAN_INFO_RAW bit as toggle channels expose + * out_voltage/current_raw{0|1} files. + */ + __clear_bit(IIO_CHAN_INFO_RAW, + &st->iio_channels[reg].info_mask_separate); + } + + chan->raw[0] =3D ltc2664_mspan_lut[mspan][1]; + chan->raw[1] =3D ltc2664_mspan_lut[mspan][1]; + + chan->span =3D ltc2664_mspan_lut[mspan][0]; + + ret =3D fwnode_property_read_u32_array(child, "adi,output-range-microvol= t", + tmp, ARRAY_SIZE(tmp)); + if (!ret && mspan =3D=3D LTC2664_MSPAN_SOFTSPAN) { + /* voltage type measurement */ + st->iio_channels[reg].type =3D IIO_VOLTAGE; + + span =3D ltc2664_span_lookup(st, (int)tmp[0] / 1000, + tmp[1] / 1000); + if (span < 0) + return dev_err_probe(dev, -EINVAL, + "output range not valid"); + + ret =3D regmap_write(st->regmap, + LTC2664_CMD_SPAN_N(reg), + span); + if (ret) + return dev_err_probe(dev, -EINVAL, + "failed to set chan settings\n"); + + chan->span =3D span; + } + + ret =3D fwnode_property_read_u32(child, + "adi,output-range-microamp", + &tmp[0]); + if (!ret) { + /* current type measurement */ + st->iio_channels[reg].type =3D IIO_CURRENT; + + span =3D ltc2664_span_lookup(st, 0, + (int)tmp[0] / 1000); + if (span < 0) + return dev_err_probe(dev, -EINVAL, + "output range not valid"); + + ret =3D regmap_write(st->regmap, + LTC2664_CMD_SPAN_N(reg), + span + 1); + if (ret) + return dev_err_probe(dev, -EINVAL, + "failed to set chan settings\n"); + + chan->span =3D span; + } + } + + return 0; +} + +static int ltc2664_setup(struct ltc2664_state *st, struct regulator *vref) +{ + const struct ltc2664_chip_info *chip_info =3D st->chip_info; + struct gpio_desc *gpio; + int ret; + + /* + * If we have a clr/reset pin, use that to reset the chip. + */ + gpio =3D devm_gpiod_get_optional(&st->spi->dev, "clr", GPIOD_OUT_HIGH); + if (IS_ERR(gpio)) + return dev_err_probe(&st->spi->dev, PTR_ERR(gpio), + "Failed to get reset gpio"); + if (gpio) { + usleep_range(1000, 1200); + /* bring device out of reset */ + gpiod_set_value_cansleep(gpio, 0); + } + + /* + * Duplicate the default channel configuration as it can change during + * @ltc2664_channel_config() + */ + st->iio_channels =3D devm_kmemdup(&st->spi->dev, chip_info->iio_chan, + chip_info->num_channels * + sizeof(*chip_info->iio_chan), + GFP_KERNEL); + + ret =3D ltc2664_channel_config(st); + if (ret) + return ret; + + if (!vref) + return 0; + + return regmap_set_bits(st->regmap, LTC2664_CMD_CONFIG, LTC2664_REF_DISABL= E); +} + +static void ltc2664_disable_regulator(void *regulator) +{ + regulator_disable(regulator); +} + +static const struct regmap_config ltc2664_regmap_config =3D { + .reg_bits =3D 8, + .val_bits =3D 16, + .max_register =3D LTC2664_CMD_NO_OPERATION, +}; + +static const struct iio_info ltc2664_info =3D { + .write_raw =3D ltc2664_write_raw, + .read_raw =3D ltc2664_read_raw, + .read_avail =3D ltc2664_read_avail, + .debugfs_reg_access =3D ltc2664_reg_access, +}; + +static int ltc2664_probe(struct spi_device *spi) +{ + static const char * const regulators[] =3D { "vcc", "iovcc" }; + const struct ltc2664_chip_info *chip_info; + struct device *dev =3D &spi->dev; + struct regulator *vref_reg; + struct iio_dev *indio_dev; + struct ltc2664_state *st; + int ret; + + indio_dev =3D devm_iio_device_alloc(dev, sizeof(*st)); + if (!indio_dev) + return -ENOMEM; + + st =3D iio_priv(indio_dev); + st->spi =3D spi; + + chip_info =3D spi_get_device_match_data(spi); + if (!chip_info) + return -ENOMEM; + + st->chip_info =3D chip_info; + + mutex_init(&st->lock); + + st->regmap =3D devm_regmap_init_spi(spi, <c2664_regmap_config); + if (IS_ERR(st->regmap)) + return dev_err_probe(dev, PTR_ERR(st->regmap), + "Failed to init regmap"); + + ret =3D devm_regulator_bulk_get_enable(dev, ARRAY_SIZE(regulators), + regulators); + if (ret) + return dev_err_probe(dev, ret, "Failed to enable regulators\n"); + + vref_reg =3D devm_regulator_get_optional(dev, "vref"); + if (IS_ERR(vref_reg)) { + if (PTR_ERR(vref_reg) !=3D -ENODEV) + return dev_err_probe(dev, PTR_ERR(vref_reg), + "Failed to get vref regulator"); + + vref_reg =3D NULL; + + /* internal reference */ + if (chip_info->id =3D=3D LTC2664) + st->vref =3D 2500; + else + st->vref =3D 1250; + } else { + ret =3D regulator_enable(vref_reg); + if (ret) + return dev_err_probe(dev, ret, + "Failed to enable vref regulators\n"); + + ret =3D devm_add_action_or_reset(dev, ltc2664_disable_regulator, + vref_reg); + if (ret) + return ret; + + ret =3D regulator_get_voltage(vref_reg); + if (ret < 0) + return dev_err_probe(dev, ret, "Failed to get vref\n"); + + st->vref =3D ret / 1000; + } + + ret =3D ltc2664_setup(st, vref_reg); + if (ret) + return ret; + + indio_dev->name =3D chip_info->name; + indio_dev->info =3D <c2664_info; + indio_dev->modes =3D INDIO_DIRECT_MODE; + indio_dev->channels =3D st->iio_channels; + indio_dev->num_channels =3D chip_info->num_channels; + + return devm_iio_device_register(dev, indio_dev); +} + +static const struct spi_device_id ltc2664_id[] =3D { + { "ltc2664", (kernel_ulong_t)<c2664_chip }, + { "ltc2672", (kernel_ulong_t)<c2672_chip }, + { }, +}; +MODULE_DEVICE_TABLE(spi, ltc2664_id); + +static const struct of_device_id ltc2664_of_id[] =3D { + { .compatible =3D "adi,ltc2664", .data =3D <c2664_chip }, + { .compatible =3D "adi,ltc2672", .data =3D <c2672_chip }, + { }, +}; +MODULE_DEVICE_TABLE(of, ltc2664_of_id); + +static struct spi_driver ltc2664_driver =3D { + .driver =3D { + .name =3D "ltc2664", + .of_match_table =3D ltc2664_of_id, + }, + .probe =3D ltc2664_probe, + .id_table =3D ltc2664_id, +}; +module_spi_driver(ltc2664_driver); + +MODULE_AUTHOR("Michael Hennerich "); +MODULE_AUTHOR("Kim Seer Paller "); +MODULE_DESCRIPTION("Analog Devices LTC2664 and LTC2672 DAC"); +MODULE_LICENSE("GPL"); --=20 2.34.1