From nobody Mon Feb 9 08:54:56 2026 Received: from fllv0016.ext.ti.com (fllv0016.ext.ti.com [198.47.19.142]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 9FB114D11D; Thu, 11 Apr 2024 22:53:18 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.47.19.142 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1712876000; cv=none; b=GbQ/3RqkX2VXolsGLmabuAq3A5r9/FJtHaV+7OZKHTBtLnde0lR+/6aOjLckhPM1OxMlTgejawXj+1zuMOoEwb/DGM2SwD8dVU8SCUWc2KOoz909Yv+F4jQREjiq+Zu92RwJ3kaU8ETrZ9Ut3HeWqBcKYY4h7Xv4YpGXA7Abdrw= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1712876000; c=relaxed/simple; bh=jDbmeXZIebAGorfKVLWPJCJNjENj1Wx0AuxQbE3hCow=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=KPcSg+lzMQ+O+wUVM/OfDr0DPpJkcLLKDLSoC5eISKeLe3XRUioygaE/tXg4yGaDQ2GjGQGhZMdzYnZSsUOHF3pT4ZJI5TEUG0AXpiok8KaHyHvBnTV5ca2+uK57qQzA84JchPsUUb4Jma8FtudhBCoGKpDVabw9KklxNhLcl2c= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com; spf=pass smtp.mailfrom=ti.com; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b=ujspUi31; arc=none smtp.client-ip=198.47.19.142 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=ti.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b="ujspUi31" Received: from lelv0265.itg.ti.com ([10.180.67.224]) by fllv0016.ext.ti.com (8.15.2/8.15.2) with ESMTP id 43BMqwO3033920; Thu, 11 Apr 2024 17:52:58 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1712875978; bh=HMqJSvOfd8Jmj35pEvHtJcgQoF/rFB+EBW0B/FwjSoM=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=ujspUi31D6bvBKOCHLTPwowCUjJB/PZXbenfsB7fF8IAzxlI55MKNsMStoDjUASxc +xtgfQOOkMz3IMYP5th/dGu1ZtxVRbtlKFjKPUcSbtlSFN7WfVsb3cg/L8uHbPdZ44 EF4ezu3cmmtvTvdLKUUb2lsK1BjTTKhnqx2P7hrI= Received: from DLEE105.ent.ti.com (dlee105.ent.ti.com [157.170.170.35]) by lelv0265.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 43BMqwXs019702 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Thu, 11 Apr 2024 17:52:58 -0500 Received: from DLEE114.ent.ti.com (157.170.170.25) by DLEE105.ent.ti.com (157.170.170.35) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23; Thu, 11 Apr 2024 17:52:57 -0500 Received: from lelvsmtp6.itg.ti.com (10.180.75.249) by DLEE114.ent.ti.com (157.170.170.25) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23 via Frontend Transport; Thu, 11 Apr 2024 17:52:57 -0500 Received: from judy-hp.dhcp.ti.com (judy-hp.dhcp.ti.com [128.247.81.105]) by lelvsmtp6.itg.ti.com (8.15.2/8.15.2) with ESMTP id 43BMqv7a002381; Thu, 11 Apr 2024 17:52:57 -0500 From: Judith Mendez To: Rob Herring , Krzysztof Kozlowski CC: Nishanth Menon , Vignesh Raghavendra , Tero Kristo , Conor Dooley , , , , Bhavya Kapoor , Dasnavis Sabiya , Udit Kumar Subject: [PATCH 4/7] arm64: dts: ti: k3-j721s2-main: Enable support for SDR104 speed mode Date: Thu, 11 Apr 2024 17:52:54 -0500 Message-ID: <20240411225257.383889-5-jm@ti.com> X-Mailer: git-send-email 2.43.2 In-Reply-To: <20240411225257.383889-1-jm@ti.com> References: <20240411225257.383889-1-jm@ti.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Content-Type: text/plain; charset="utf-8" From: Bhavya Kapoor According to TRM for J721S2, SDR104 speed mode is supported by the SoC but its capabilities were masked in device tree. Remove sdhci-caps-mask to enable support for SDR104 speed mode for SD card in J721S2 SoC. [+] Refer to : section 12.3.6.1.1 MMCSD Features, in J721S2 TRM - https://www.ti.com/lit/zip/spruj28 Fixes: b8545f9d3a54 ("arm64: dts: ti: Add initial support for J721S2 SoC") Signed-off-by: Bhavya Kapoor Signed-off-by: Vignesh Raghavendra --- arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi | 2 -- 1 file changed, 2 deletions(-) diff --git a/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi b/arch/arm64/boot/d= ts/ti/k3-j721s2-main.dtsi index 3cb06a7e4117f..9ed6949b40e9d 100644 --- a/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi @@ -768,8 +768,6 @@ main_sdhci1: mmc@4fb0000 { ti,clkbuf-sel =3D <0x7>; ti,trm-icp =3D <0x8>; dma-coherent; - /* Masking support for SDR104 capability */ - sdhci-caps-mask =3D <0x00000003 0x00000000>; status =3D "disabled"; }; =20 --=20 2.43.2