From nobody Sun Feb 8 12:58:32 2026 Received: from fllv0016.ext.ti.com (fllv0016.ext.ti.com [198.47.19.142]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 9FAE24D11B; Thu, 11 Apr 2024 22:53:18 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.47.19.142 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1712876000; cv=none; b=CHYpu1u34d9cKbIqAp+pRHc8zX0Vzah2795HUok5gwKMKa5zjeuJG9FNV3AP8oi6ZTO2c/uTG9VrhtW4tSNGKz5eQupU8tuhA6De9m2ruSy4lXkyp96DS0y/dApbZElYYBeFUOKcO/JlOkGmPZMIMmBAnB0JwcQpV3HDnvq0N4c= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1712876000; c=relaxed/simple; bh=fnwZwdTZHz7xYfHZkK8HW17q7uRXp9xrFm416v6m5KA=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=Mt1F5eNtw6qPlpjY1uFWGp5dFLDllE5yEH9WBxeONPOkJMK5FgTsKUgANNTao4jj+7AXUjmX4XodFYi4bVLniO8JwUZdZkfdjopQRzfvhSwCoFf40u0Bsu7OW+BLTCt6xCMkkUoGF6BNSna4mHe4lOJFtq7CeMD9sznfZf74c+U= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com; spf=pass smtp.mailfrom=ti.com; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b=VGP6d1eA; arc=none smtp.client-ip=198.47.19.142 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=ti.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b="VGP6d1eA" Received: from lelv0266.itg.ti.com ([10.180.67.225]) by fllv0016.ext.ti.com (8.15.2/8.15.2) with ESMTP id 43BMqvCJ033916; Thu, 11 Apr 2024 17:52:57 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1712875978; bh=izg+oGQCuUwOQiPJW6J8T+O9QAeRgI3fYhFwd8fM1Pc=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=VGP6d1eA94Cfxc1xdiVJgOZ7h5NL+n3Q0EnvCMjDZyixWBRZB5jkhJiDVmfH4SkSs SnnH6Kh5yd7jwpm89wjk7Utu+Nkb9cd14VpDAnghL/APxl2LJDfbVeVH+4Z1zmg0BL J3L0OkPqc2qvRPa4FRYj4LKh8vYK78w3k5pJjuuk= Received: from DLEE109.ent.ti.com (dlee109.ent.ti.com [157.170.170.41]) by lelv0266.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 43BMqv7R083766 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Thu, 11 Apr 2024 17:52:57 -0500 Received: from DLEE102.ent.ti.com (157.170.170.32) by DLEE109.ent.ti.com (157.170.170.41) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23; Thu, 11 Apr 2024 17:52:57 -0500 Received: from lelvsmtp6.itg.ti.com (10.180.75.249) by DLEE102.ent.ti.com (157.170.170.32) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23 via Frontend Transport; Thu, 11 Apr 2024 17:52:57 -0500 Received: from judy-hp.dhcp.ti.com (judy-hp.dhcp.ti.com [128.247.81.105]) by lelvsmtp6.itg.ti.com (8.15.2/8.15.2) with ESMTP id 43BMqv7X002381; Thu, 11 Apr 2024 17:52:57 -0500 From: Judith Mendez To: Rob Herring , Krzysztof Kozlowski CC: Nishanth Menon , Vignesh Raghavendra , Tero Kristo , Conor Dooley , , , , Bhavya Kapoor , Dasnavis Sabiya , Udit Kumar Subject: [PATCH 1/7] arm64: dts: ti: k3-am65-main: Update sdhci properties Date: Thu, 11 Apr 2024 17:52:51 -0500 Message-ID: <20240411225257.383889-2-jm@ti.com> X-Mailer: git-send-email 2.43.2 In-Reply-To: <20240411225257.383889-1-jm@ti.com> References: <20240411225257.383889-1-jm@ti.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Content-Type: text/plain; charset="utf-8" Update otap-del-sel properties as per datasheet [0]. Add missing clkbuf-sel and itap-del-sel values also as per datasheet [0]. Move clkbuf-sel and ti,trm-icp above the otap-del-sel properties so the sdhci nodes could be more uniform across platforms. [0] https://www.ti.com/lit/ds/symlink/am6548.pdf Fixes: eac99d38f861 ("arm64: dts: ti: k3-am654-main: Update otap-del-sel va= lues") Fixes: d7600d070fb0 ("arm64: dts: ti: k3-am65-main: Add support for sdhci1") Signed-off-by: Judith Mendez --- arch/arm64/boot/dts/ti/k3-am65-main.dtsi | 17 +++++++++++------ 1 file changed, 11 insertions(+), 6 deletions(-) diff --git a/arch/arm64/boot/dts/ti/k3-am65-main.dtsi b/arch/arm64/boot/dts= /ti/k3-am65-main.dtsi index 670557c89f756..0803a8b9bfe84 100644 --- a/arch/arm64/boot/dts/ti/k3-am65-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am65-main.dtsi @@ -435,6 +435,8 @@ sdhci0: mmc@4f80000 { interrupts =3D ; mmc-ddr-1_8v; mmc-hs200-1_8v; + ti,clkbuf-sel =3D <0x7>; + ti,trm-icp =3D <0x8>; ti,otap-del-sel-legacy =3D <0x0>; ti,otap-del-sel-mmc-hs =3D <0x0>; ti,otap-del-sel-sd-hs =3D <0x0>; @@ -445,8 +447,7 @@ sdhci0: mmc@4f80000 { ti,otap-del-sel-ddr50 =3D <0x5>; ti,otap-del-sel-ddr52 =3D <0x5>; ti,otap-del-sel-hs200 =3D <0x5>; - ti,otap-del-sel-hs400 =3D <0x0>; - ti,trm-icp =3D <0x8>; + ti,itap-del-sel-ddr52 =3D <0x0>; dma-coherent; status =3D "disabled"; }; @@ -458,18 +459,22 @@ sdhci1: mmc@4fa0000 { clocks =3D <&k3_clks 48 0>, <&k3_clks 48 1>; clock-names =3D "clk_ahb", "clk_xin"; interrupts =3D ; + ti,clkbuf-sel =3D <0x7>; + ti,trm-icp =3D <0x8>; ti,otap-del-sel-legacy =3D <0x0>; ti,otap-del-sel-mmc-hs =3D <0x0>; ti,otap-del-sel-sd-hs =3D <0x0>; - ti,otap-del-sel-sdr12 =3D <0x0>; - ti,otap-del-sel-sdr25 =3D <0x0>; + ti,otap-del-sel-sdr12 =3D <0xf>; + ti,otap-del-sel-sdr25 =3D <0xf>; ti,otap-del-sel-sdr50 =3D <0x8>; ti,otap-del-sel-sdr104 =3D <0x7>; ti,otap-del-sel-ddr50 =3D <0x4>; ti,otap-del-sel-ddr52 =3D <0x4>; ti,otap-del-sel-hs200 =3D <0x7>; - ti,clkbuf-sel =3D <0x7>; - ti,trm-icp =3D <0x8>; + ti,itap-del-sel-legacy =3D <0xa>; + ti,itap-del-sel-sd-hs =3D <0x1>; + ti,itap-del-sel-sdr12 =3D <0xa>; + ti,itap-del-sel-sdr25 =3D <0x1>; dma-coherent; status =3D "disabled"; }; --=20 2.43.2 From nobody Sun Feb 8 12:58:32 2026 Received: from fllv0015.ext.ti.com (fllv0015.ext.ti.com [198.47.19.141]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 9E4DC4D112; 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charset="utf-8" On AM65x platform, sdhci0 is for eMMC and sdhci1 is for SD. Remove the properties that are not applicable for each device. Fixes: eac99d38f861 ("arm64: dts: ti: k3-am654-main: Update otap-del-sel va= lues") Fixes: d7600d070fb0 ("arm64: dts: ti: k3-am65-main: Add support for sdhci1") Signed-off-by: Judith Mendez --- arch/arm64/boot/dts/ti/k3-am65-main.dtsi | 9 --------- 1 file changed, 9 deletions(-) diff --git a/arch/arm64/boot/dts/ti/k3-am65-main.dtsi b/arch/arm64/boot/dts= /ti/k3-am65-main.dtsi index 0803a8b9bfe84..127f581a56bc6 100644 --- a/arch/arm64/boot/dts/ti/k3-am65-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am65-main.dtsi @@ -439,12 +439,6 @@ sdhci0: mmc@4f80000 { ti,trm-icp =3D <0x8>; ti,otap-del-sel-legacy =3D <0x0>; ti,otap-del-sel-mmc-hs =3D <0x0>; - ti,otap-del-sel-sd-hs =3D <0x0>; - ti,otap-del-sel-sdr12 =3D <0x0>; - ti,otap-del-sel-sdr25 =3D <0x0>; - ti,otap-del-sel-sdr50 =3D <0x8>; - ti,otap-del-sel-sdr104 =3D <0x7>; - ti,otap-del-sel-ddr50 =3D <0x5>; ti,otap-del-sel-ddr52 =3D <0x5>; ti,otap-del-sel-hs200 =3D <0x5>; ti,itap-del-sel-ddr52 =3D <0x0>; @@ -462,15 +456,12 @@ sdhci1: mmc@4fa0000 { ti,clkbuf-sel =3D <0x7>; ti,trm-icp =3D <0x8>; ti,otap-del-sel-legacy =3D <0x0>; - ti,otap-del-sel-mmc-hs =3D <0x0>; ti,otap-del-sel-sd-hs =3D <0x0>; ti,otap-del-sel-sdr12 =3D <0xf>; ti,otap-del-sel-sdr25 =3D <0xf>; ti,otap-del-sel-sdr50 =3D <0x8>; ti,otap-del-sel-sdr104 =3D <0x7>; ti,otap-del-sel-ddr50 =3D <0x4>; - ti,otap-del-sel-ddr52 =3D <0x4>; - ti,otap-del-sel-hs200 =3D <0x7>; ti,itap-del-sel-legacy =3D <0xa>; ti,itap-del-sel-sd-hs =3D <0x1>; ti,itap-del-sel-sdr12 =3D <0xa>; --=20 2.43.2 From nobody Sun Feb 8 12:58:32 2026 Received: from lelv0142.ext.ti.com (lelv0142.ext.ti.com [198.47.23.249]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D797C4654F; Thu, 11 Apr 2024 22:53:07 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.47.23.249 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1712875989; cv=none; b=F/n75zjW42ZZdIzO0dz1xKdUHXhmRgo4ZPsiG0eSlqzB3ZS/a/KnSctMwlX1kdo+4R7xqz1xtpAQZ2Jb4Z707q9dOR1lIsshYsud2JP0i171pJpu7lyIL78E9NRV1ZfSvM8LQzndV0dvgDTlxfjTRWFV+xtG8Yd5wBle3JZW0iU= ARC-Message-Signature: i=1; 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Thu, 11 Apr 2024 17:52:57 -0500 Received: from judy-hp.dhcp.ti.com (judy-hp.dhcp.ti.com [128.247.81.105]) by lelvsmtp6.itg.ti.com (8.15.2/8.15.2) with ESMTP id 43BMqv7Z002381; Thu, 11 Apr 2024 17:52:57 -0500 From: Judith Mendez To: Rob Herring , Krzysztof Kozlowski CC: Nishanth Menon , Vignesh Raghavendra , Tero Kristo , Conor Dooley , , , , Bhavya Kapoor , Dasnavis Sabiya , Udit Kumar Subject: [PATCH 3/7] arm64: dts: ti: k3-am62a: Enable UHS mode support for SD cards Date: Thu, 11 Apr 2024 17:52:53 -0500 Message-ID: <20240411225257.383889-4-jm@ti.com> X-Mailer: git-send-email 2.43.2 In-Reply-To: <20240411225257.383889-1-jm@ti.com> References: <20240411225257.383889-1-jm@ti.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Content-Type: text/plain; charset="utf-8" From: Vignesh Raghavendra Hook up required IO voltage regulators and drop no-1-8-v to support UHS modes on SD cards. Fixes: 5fc6b1b62639 ("arm64: dts: ti: Introduce AM62A7 family of SoCs") Signed-off-by: Vignesh Raghavendra [Judith: Remove no-1-8-v for sdhci2, keep otap-del-sel-legacy=3D0, add fixes tag, reword commit] Signed-off-by: Judith Mendez --- arch/arm64/boot/dts/ti/k3-am62a-main.dtsi | 2 -- arch/arm64/boot/dts/ti/k3-am62a7-sk.dts | 21 +++++++++++++++++++++ 2 files changed, 21 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/ti/k3-am62a-main.dtsi b/arch/arm64/boot/dt= s/ti/k3-am62a-main.dtsi index aa1e057082f08..6652701d3e3b8 100644 --- a/arch/arm64/boot/dts/ti/k3-am62a-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am62a-main.dtsi @@ -573,7 +573,6 @@ sdhci1: mmc@fa00000 { ti,itap-del-sel-sd-hs =3D <0x0>; ti,itap-del-sel-sdr12 =3D <0x0>; ti,itap-del-sel-sdr25 =3D <0x0>; - no-1-8-v; status =3D "disabled"; }; =20 @@ -597,7 +596,6 @@ sdhci2: mmc@fa20000 { ti,itap-del-sel-sd-hs =3D <0x0>; ti,itap-del-sel-sdr12 =3D <0x0>; ti,itap-del-sel-sdr25 =3D <0x0>; - no-1-8-v; status =3D "disabled"; }; =20 diff --git a/arch/arm64/boot/dts/ti/k3-am62a7-sk.dts b/arch/arm64/boot/dts/= ti/k3-am62a7-sk.dts index f241637a5642a..1af5d01c7b94c 100644 --- a/arch/arm64/boot/dts/ti/k3-am62a7-sk.dts +++ b/arch/arm64/boot/dts/ti/k3-am62a7-sk.dts @@ -113,6 +113,20 @@ vcc_3v3_sys: regulator-4 { regulator-boot-on; }; =20 + vddshv_sdio: regulator-5 { + compatible =3D "regulator-gpio"; + regulator-name =3D "vddshv_sdio"; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&vddshv_sdio_pins_default>; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <3300000>; + regulator-boot-on; + vin-supply =3D <&ldo1>; + gpios =3D <&main_gpio0 31 GPIO_ACTIVE_HIGH>; + states =3D <1800000 0x0>, + <3300000 0x1>; + }; + leds { compatible =3D "gpio-leds"; pinctrl-names =3D "default"; @@ -342,6 +356,12 @@ main_gpio1_ioexp_intr_pins_default: main-gpio1-ioexp-i= ntr-default-pins { AM62AX_IOPAD(0x01d4, PIN_INPUT, 7) /* (C15) UART0_RTSn.GPIO1_23 */ >; }; + + vddshv_sdio_pins_default: vddshv-sdio-pins-default { + pinctrl-single,pins =3D < + AM62AX_IOPAD(0x07c, PIN_OUTPUT, 7) /* (M19) GPMC0_CLK.GPIO0_31 */ + >; + }; }; =20 &mcu_pmx0 { @@ -580,6 +600,7 @@ &sdhci1 { /* SD/MMC */ status =3D "okay"; vmmc-supply =3D <&vdd_mmc1>; + vqmmc-supply =3D <&vddshv_sdio>; pinctrl-names =3D "default"; pinctrl-0 =3D <&main_mmc1_pins_default>; disable-wp; --=20 2.43.2 From nobody Sun Feb 8 12:58:32 2026 Received: from fllv0016.ext.ti.com (fllv0016.ext.ti.com [198.47.19.142]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 9FB114D11D; Thu, 11 Apr 2024 22:53:18 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.47.19.142 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1712876000; cv=none; b=GbQ/3RqkX2VXolsGLmabuAq3A5r9/FJtHaV+7OZKHTBtLnde0lR+/6aOjLckhPM1OxMlTgejawXj+1zuMOoEwb/DGM2SwD8dVU8SCUWc2KOoz909Yv+F4jQREjiq+Zu92RwJ3kaU8ETrZ9Ut3HeWqBcKYY4h7Xv4YpGXA7Abdrw= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1712876000; 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Thu, 11 Apr 2024 17:52:57 -0500 Received: from judy-hp.dhcp.ti.com (judy-hp.dhcp.ti.com [128.247.81.105]) by lelvsmtp6.itg.ti.com (8.15.2/8.15.2) with ESMTP id 43BMqv7a002381; Thu, 11 Apr 2024 17:52:57 -0500 From: Judith Mendez To: Rob Herring , Krzysztof Kozlowski CC: Nishanth Menon , Vignesh Raghavendra , Tero Kristo , Conor Dooley , , , , Bhavya Kapoor , Dasnavis Sabiya , Udit Kumar Subject: [PATCH 4/7] arm64: dts: ti: k3-j721s2-main: Enable support for SDR104 speed mode Date: Thu, 11 Apr 2024 17:52:54 -0500 Message-ID: <20240411225257.383889-5-jm@ti.com> X-Mailer: git-send-email 2.43.2 In-Reply-To: <20240411225257.383889-1-jm@ti.com> References: <20240411225257.383889-1-jm@ti.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Content-Type: text/plain; charset="utf-8" From: Bhavya Kapoor According to TRM for J721S2, SDR104 speed mode is supported by the SoC but its capabilities were masked in device tree. Remove sdhci-caps-mask to enable support for SDR104 speed mode for SD card in J721S2 SoC. [+] Refer to : section 12.3.6.1.1 MMCSD Features, in J721S2 TRM - https://www.ti.com/lit/zip/spruj28 Fixes: b8545f9d3a54 ("arm64: dts: ti: Add initial support for J721S2 SoC") Signed-off-by: Bhavya Kapoor Signed-off-by: Vignesh Raghavendra --- arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi | 2 -- 1 file changed, 2 deletions(-) diff --git a/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi b/arch/arm64/boot/d= ts/ti/k3-j721s2-main.dtsi index 3cb06a7e4117f..9ed6949b40e9d 100644 --- a/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi @@ -768,8 +768,6 @@ main_sdhci1: mmc@4fb0000 { ti,clkbuf-sel =3D <0x7>; ti,trm-icp =3D <0x8>; dma-coherent; - /* Masking support for SDR104 capability */ - sdhci-caps-mask =3D <0x00000003 0x00000000>; status =3D "disabled"; }; =20 --=20 2.43.2 From nobody Sun Feb 8 12:58:32 2026 Received: from lelv0142.ext.ti.com (lelv0142.ext.ti.com [198.47.23.249]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A38C812E6C; Thu, 11 Apr 2024 22:53:07 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.47.23.249 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1712875989; cv=none; b=pX54eseZciQgaZGWAsUiTqD6nnl6LyocyOiZssySX1E0lPiN9CcqLshkm4O6+0NVNmFML2nYGPf8CPS1NcCHXQQp968s81OyESa6/CDY5y41S+CgrbGHDxkwgy6lSe+SVY5b498ZLU8POs1f/7gQonFEj5JOBn6GkB5ihZKi2ec= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1712875989; c=relaxed/simple; bh=P/bZqmi5tX/lltQL5h2nrT0q+Hpv7eCt+l1QnEB2mJc=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=e32zQAWrs6UM0Drdf/tbJxV/FgMxAyzvvQ/yJ+YQn+o+lLd50g+pU3bfSq5+thYRdzUeu7U8iuvN3lb2CO4SB7bPM8HGsz9Xp7IWvbi57ifScut5i72nfT7euJ3ngr/9NcHbgNQF9kqXxc1N2xS+68wB0Iqe2MmB//2g2ZFmVtQ= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com; spf=pass smtp.mailfrom=ti.com; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b=IHMcDpS3; arc=none smtp.client-ip=198.47.23.249 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=ti.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b="IHMcDpS3" Received: from lelv0266.itg.ti.com ([10.180.67.225]) by lelv0142.ext.ti.com (8.15.2/8.15.2) with ESMTP id 43BMqwXU106819; Thu, 11 Apr 2024 17:52:58 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1712875978; bh=u6vHxsop2dc7G8tz56tmeLvsOTidrw9pFmeRN0x2ua4=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=IHMcDpS3fW3buueDLD6uV71ScK6RovtUKYr7IKodb/pg6O+GZDnK0uUzwdLLFa7cR 6FahIO5WaLUnGl4RYLTHx9QutJXW4Xba40/6Lh20kdZ6aCLWnzhTM7xVK6W+p0ur7Q mpq4kgjT/Rd4TdZ36hpp1+Uoc8FaT7Oz5owPEpUw= Received: from DLEE106.ent.ti.com (dlee106.ent.ti.com [157.170.170.36]) by lelv0266.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 43BMqwL2083771 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Thu, 11 Apr 2024 17:52:58 -0500 Received: from DLEE112.ent.ti.com (157.170.170.23) by DLEE106.ent.ti.com (157.170.170.36) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23; Thu, 11 Apr 2024 17:52:57 -0500 Received: from lelvsmtp6.itg.ti.com (10.180.75.249) by DLEE112.ent.ti.com (157.170.170.23) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23 via Frontend Transport; Thu, 11 Apr 2024 17:52:57 -0500 Received: from judy-hp.dhcp.ti.com (judy-hp.dhcp.ti.com [128.247.81.105]) by lelvsmtp6.itg.ti.com (8.15.2/8.15.2) with ESMTP id 43BMqv7b002381; Thu, 11 Apr 2024 17:52:57 -0500 From: Judith Mendez To: Rob Herring , Krzysztof Kozlowski CC: Nishanth Menon , Vignesh Raghavendra , Tero Kristo , Conor Dooley , , , , Bhavya Kapoor , Dasnavis Sabiya , Udit Kumar Subject: [PATCH 5/7] arm64: dts: ti: k3-j784s4-main: Enable support for UHS mode Date: Thu, 11 Apr 2024 17:52:55 -0500 Message-ID: <20240411225257.383889-6-jm@ti.com> X-Mailer: git-send-email 2.43.2 In-Reply-To: <20240411225257.383889-1-jm@ti.com> References: <20240411225257.383889-1-jm@ti.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Content-Type: text/plain; charset="utf-8" From: Dasnavis Sabiya Remove sdhci-caps-mask to enable support for SDR104 speed mode for SD card and remove no-1-8-v property so that SD card can work in any UHS-1 high speed mode it can support. Fixes: 4664ebd8346a ("arm64: dts: ti: Add initial support for J784S4 SoC") Signed-off-by: Bhavya Kapoor Signed-off-by: Dasnavis Sabiya Signed-off-by: Vignesh Raghavendra [Judith: Add fixes tag] Signed-off-by: Judith Mendez --- arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi | 2 -- 1 file changed, 2 deletions(-) diff --git a/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi b/arch/arm64/boot/d= ts/ti/k3-j784s4-main.dtsi index d42f25cacf23d..6a4554c6c9c13 100644 --- a/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi @@ -904,8 +904,6 @@ main_sdhci1: mmc@4fb0000 { ti,clkbuf-sel =3D <0x7>; ti,trm-icp =3D <0x8>; dma-coherent; - sdhci-caps-mask =3D <0x00000003 0x00000000>; - no-1-8-v; status =3D "disabled"; }; =20 --=20 2.43.2 From nobody Sun Feb 8 12:58:32 2026 Received: from lelv0142.ext.ti.com (lelv0142.ext.ti.com [198.47.23.249]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 796EB45C10; Thu, 11 Apr 2024 22:53:06 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.47.23.249 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1712875987; cv=none; b=e1Vi9yZ/9s9ON/PQxGKKaJ4PIvHGskXJkPlUtKuzX8uN+9BqAqxBvcP0dGtSMruVSM3t9uVE4srHvPCX+N8whuZKDJWqiq1EvtgUomdOu5+IW1oiIuRzbEyj+6QfWi4m7ow/q5Z5l3OCtOi7Cr/zWibXfge2U+6TREPS2/SG0n4= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1712875987; c=relaxed/simple; bh=W5IOIauvdcqC7Pu61JrL4Nqqv2GxapZeP3kf7mWwtBM=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=quwW+2IwNk6NOPHKKv75GkmgX8qwdb11mF3IxYHQDUfsG2lzoa4zdJaZ4hhm3S1lUa+sPnfN/BaG9LvUeENYtXkhb9zmrpu5K9KAy08QDky0saMpcmDVqEMeqmrUbDceYyiQ1hY1i9mex9t45ZHWRIo/bWEpc23Y8DC0vCGV+gU= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com; spf=pass smtp.mailfrom=ti.com; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b=u1a3iG+8; arc=none smtp.client-ip=198.47.23.249 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=ti.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b="u1a3iG+8" Received: from lelv0266.itg.ti.com ([10.180.67.225]) by lelv0142.ext.ti.com (8.15.2/8.15.2) with ESMTP id 43BMqwO2106827; Thu, 11 Apr 2024 17:52:58 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1712875978; bh=U5vGaNlkeZBsjgOImgjsk8+GhPmZ/Wnc8cLNrjW4OwY=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=u1a3iG+8WMQFLsaUGuF+sny4IT0HYhrWg9PG5zA+jlCxtVThU/KJ0VsVKIoe/Er6o 9lNbmJoNV4coTm6dvDBN1RgPdpPFZhbCfs2xvuhC2f/A8dHdTi9gA05y1/FecJTI98 aNcOIA0w/+R39RC/ScyRJ+zB32per4pVYs026brg= Received: from DLEE108.ent.ti.com (dlee108.ent.ti.com [157.170.170.38]) by lelv0266.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 43BMqwZo083776 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Thu, 11 Apr 2024 17:52:58 -0500 Received: from DLEE105.ent.ti.com (157.170.170.35) by DLEE108.ent.ti.com (157.170.170.38) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23; Thu, 11 Apr 2024 17:52:57 -0500 Received: from lelvsmtp6.itg.ti.com (10.180.75.249) by DLEE105.ent.ti.com (157.170.170.35) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23 via Frontend Transport; Thu, 11 Apr 2024 17:52:57 -0500 Received: from judy-hp.dhcp.ti.com (judy-hp.dhcp.ti.com [128.247.81.105]) by lelvsmtp6.itg.ti.com (8.15.2/8.15.2) with ESMTP id 43BMqv7c002381; Thu, 11 Apr 2024 17:52:57 -0500 From: Judith Mendez To: Rob Herring , Krzysztof Kozlowski CC: Nishanth Menon , Vignesh Raghavendra , Tero Kristo , Conor Dooley , , , , Bhavya Kapoor , Dasnavis Sabiya , Udit Kumar Subject: [PATCH 6/7] arm64: dts: ti: k3-am69-sk: Remove HS400 mode support for eMMC Date: Thu, 11 Apr 2024 17:52:56 -0500 Message-ID: <20240411225257.383889-7-jm@ti.com> X-Mailer: git-send-email 2.43.2 In-Reply-To: <20240411225257.383889-1-jm@ti.com> References: <20240411225257.383889-1-jm@ti.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Content-Type: text/plain; charset="utf-8" From: Dasnavis Sabiya The eMMC fails to enumerate intermittently on HS400 mode. Also observing multiple CQE recovery warnings. Update the sdhci0 node to disable HS400 and set HS200 mode for eMMC node. Signed-off-by: Dasnavis Sabiya Signed-off-by: Vignesh Raghavendra --- arch/arm64/boot/dts/ti/k3-am69-sk.dts | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/boot/dts/ti/k3-am69-sk.dts b/arch/arm64/boot/dts/ti= /k3-am69-sk.dts index 50de2a448a3a6..a677bb9200a35 100644 --- a/arch/arm64/boot/dts/ti/k3-am69-sk.dts +++ b/arch/arm64/boot/dts/ti/k3-am69-sk.dts @@ -906,6 +906,7 @@ &main_sdhci0 { non-removable; ti,driver-strength-ohm =3D <50>; disable-wp; + no-mmc-hs400; }; =20 &main_sdhci1 { --=20 2.43.2 From nobody Sun Feb 8 12:58:32 2026 Received: from lelv0142.ext.ti.com (lelv0142.ext.ti.com [198.47.23.249]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 796AD224FA; Thu, 11 Apr 2024 22:53:06 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.47.23.249 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1712875988; cv=none; b=e0pL41j2x6MUJ5daA8o2OPy6bQ3a34KghNCIUWustnOP+SwvuPFMxJKndq9cIssRnmdm5Tm1JTzUIsZm4bJnw4uljS/svoKlZjrEzxKsgTBfIv2ON69M9Axwvubl3l6WHkTn9FG8zcMP+7C0sqYL+5xialzB9+tsdJlP/EwpbXE= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1712875988; c=relaxed/simple; bh=zvmvF417rrunT9iqHHfUQkubRPufaxCziKLZeyjCEiU=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=A3RZVvK+CoBHE1RnOnOJNwd4pb2GXYFjAcTNoHVgebZ+YY3xp9cugHbAwIkjQ1jL6dCmw1yz00G6XIfRDyE8OhCpSyJUsjupYVfbwYv8VM8PwYo7tnDd9KQ89lMD+/wd3hvO42YxhI5DMQUskMM4B3Xgn29sj+4UvsPoCYLRS9c= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com; spf=pass smtp.mailfrom=ti.com; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b=D0zKLJTs; arc=none smtp.client-ip=198.47.23.249 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=ti.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b="D0zKLJTs" Received: from fllv0034.itg.ti.com ([10.64.40.246]) by lelv0142.ext.ti.com (8.15.2/8.15.2) with ESMTP id 43BMqwIe106823; Thu, 11 Apr 2024 17:52:58 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1712875978; bh=2LfTDKlFS9AeONkXkDfJQ8nmESoidJKOear7mi/CZWg=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=D0zKLJTsLgbiDY0k/nZoElt03uCqZTNTQPqUZ/QWRgiBEpbx/kV7KiOvjzXnbFZrE 91nUFIYd5fGuH53/DYBx6I56duAIrEHcoI5L/ysZSMywK0czdfiEygsBsfI1a/2Dzc mTM7lfnPjgVj06hdwG4Hnts/FuyqLoGw2RFBciDI= Received: from DFLE113.ent.ti.com (dfle113.ent.ti.com [10.64.6.34]) by fllv0034.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 43BMqwqX108003 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Thu, 11 Apr 2024 17:52:58 -0500 Received: from DFLE106.ent.ti.com (10.64.6.27) by DFLE113.ent.ti.com (10.64.6.34) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23; Thu, 11 Apr 2024 17:52:57 -0500 Received: from lelvsmtp6.itg.ti.com (10.180.75.249) by DFLE106.ent.ti.com (10.64.6.27) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23 via Frontend Transport; Thu, 11 Apr 2024 17:52:57 -0500 Received: from judy-hp.dhcp.ti.com (judy-hp.dhcp.ti.com [128.247.81.105]) by lelvsmtp6.itg.ti.com (8.15.2/8.15.2) with ESMTP id 43BMqv7d002381; Thu, 11 Apr 2024 17:52:57 -0500 From: Judith Mendez To: Rob Herring , Krzysztof Kozlowski CC: Nishanth Menon , Vignesh Raghavendra , Tero Kristo , Conor Dooley , , , , Bhavya Kapoor , Dasnavis Sabiya , Udit Kumar Subject: [PATCH 7/7] arm64: dts: ti: k3-j784s4-evm: Remove HS400 mode support for eMMC Date: Thu, 11 Apr 2024 17:52:57 -0500 Message-ID: <20240411225257.383889-8-jm@ti.com> X-Mailer: git-send-email 2.43.2 In-Reply-To: <20240411225257.383889-1-jm@ti.com> References: <20240411225257.383889-1-jm@ti.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Content-Type: text/plain; charset="utf-8" From: Udit Kumar The eMMC fails to enumerate intermittently on HS400 mode. Also observing multiple CQE recovery warnings. Update the sdhci0 node to disable HS400. Cc: Vignesh Raghavendra Cc: Bhavya Kapoor Cc: Siddharth Vadapalli Signed-off-by: Udit Kumar Signed-off-by: Vignesh Raghavendra [Judith: Reword commit] Signed-off-by: Judith Mendez --- arch/arm64/boot/dts/ti/k3-j784s4-evm.dts | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/boot/dts/ti/k3-j784s4-evm.dts b/arch/arm64/boot/dts= /ti/k3-j784s4-evm.dts index 81fd7afac8c57..04a241a91e6b8 100644 --- a/arch/arm64/boot/dts/ti/k3-j784s4-evm.dts +++ b/arch/arm64/boot/dts/ti/k3-j784s4-evm.dts @@ -791,6 +791,7 @@ &main_sdhci0 { non-removable; ti,driver-strength-ohm =3D <50>; disable-wp; + no-mmc-hs400; }; =20 &main_sdhci1 { --=20 2.43.2