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[86.9.131.95]) by smtp.gmail.com with ESMTPSA id df10-20020a5d5b8a000000b003437799a373sm2292400wrb.83.2024.04.11.11.07.08 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 11 Apr 2024 11:07:08 -0700 (PDT) From: Stafford Horne To: LKML Cc: Linux OpenRISC , Stafford Horne , Jonas Bonn , Stefan Kristiansson Subject: [PATCH 1/5] openrisc: traps: Convert printks to pr_ macros Date: Thu, 11 Apr 2024 19:06:28 +0100 Message-ID: <20240411180644.2023991-2-shorne@gmail.com> X-Mailer: git-send-email 2.44.0 In-Reply-To: <20240411180644.2023991-1-shorne@gmail.com> References: <20240411180644.2023991-1-shorne@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The pr_* macros are the convention and my upcoming patches add even more printk's. Use this opportunity to convert the printks in this file to the pr_* macros to avoid patch check warnings. Signed-off-by: Stafford Horne --- arch/openrisc/kernel/traps.c | 88 ++++++++++++++++++------------------ 1 file changed, 44 insertions(+), 44 deletions(-) diff --git a/arch/openrisc/kernel/traps.c b/arch/openrisc/kernel/traps.c index 9370888c9a7e..6d0fee912747 100644 --- a/arch/openrisc/kernel/traps.c +++ b/arch/openrisc/kernel/traps.c @@ -51,16 +51,16 @@ static void print_trace(void *data, unsigned long addr,= int reliable) { const char *loglvl =3D data; =20 - printk("%s[<%p>] %s%pS\n", loglvl, (void *) addr, reliable ? "" : "? ", - (void *) addr); + pr_info("%s[<%p>] %s%pS\n", loglvl, (void *) addr, reliable ? "" : "? ", + (void *) addr); } =20 static void print_data(unsigned long base_addr, unsigned long word, int i) { if (i =3D=3D 0) - printk("(%08lx:)\t%08lx", base_addr + (i * 4), word); + pr_info("(%08lx:)\t%08lx", base_addr + (i * 4), word); else - printk(" %08lx:\t%08lx", base_addr + (i * 4), word); + pr_info(" %08lx:\t%08lx", base_addr + (i * 4), word); } =20 /* displays a short stack trace */ @@ -69,7 +69,7 @@ void show_stack(struct task_struct *task, unsigned long *= esp, const char *loglvl if (esp =3D=3D NULL) esp =3D (unsigned long *)&esp; =20 - printk("%sCall trace:\n", loglvl); + pr_info("%sCall trace:\n", loglvl); unwind_stack((void *)loglvl, esp, print_trace); } =20 @@ -83,57 +83,57 @@ void show_registers(struct pt_regs *regs) if (user_mode(regs)) in_kernel =3D 0; =20 - printk("CPU #: %d\n" - " PC: %08lx SR: %08lx SP: %08lx FPCSR: %08lx\n", - smp_processor_id(), regs->pc, regs->sr, regs->sp, - regs->fpcsr); - printk("GPR00: %08lx GPR01: %08lx GPR02: %08lx GPR03: %08lx\n", - 0L, regs->gpr[1], regs->gpr[2], regs->gpr[3]); - printk("GPR04: %08lx GPR05: %08lx GPR06: %08lx GPR07: %08lx\n", - regs->gpr[4], regs->gpr[5], regs->gpr[6], regs->gpr[7]); - printk("GPR08: %08lx GPR09: %08lx GPR10: %08lx GPR11: %08lx\n", - regs->gpr[8], regs->gpr[9], regs->gpr[10], regs->gpr[11]); - printk("GPR12: %08lx GPR13: %08lx GPR14: %08lx GPR15: %08lx\n", - regs->gpr[12], regs->gpr[13], regs->gpr[14], regs->gpr[15]); - printk("GPR16: %08lx GPR17: %08lx GPR18: %08lx GPR19: %08lx\n", - regs->gpr[16], regs->gpr[17], regs->gpr[18], regs->gpr[19]); - printk("GPR20: %08lx GPR21: %08lx GPR22: %08lx GPR23: %08lx\n", - regs->gpr[20], regs->gpr[21], regs->gpr[22], regs->gpr[23]); - printk("GPR24: %08lx GPR25: %08lx GPR26: %08lx GPR27: %08lx\n", - regs->gpr[24], regs->gpr[25], regs->gpr[26], regs->gpr[27]); - printk("GPR28: %08lx GPR29: %08lx GPR30: %08lx GPR31: %08lx\n", - regs->gpr[28], regs->gpr[29], regs->gpr[30], regs->gpr[31]); - printk(" RES: %08lx oGPR11: %08lx\n", - regs->gpr[11], regs->orig_gpr11); - - printk("Process %s (pid: %d, stackpage=3D%08lx)\n", - current->comm, current->pid, (unsigned long)current); + pr_info("CPU #: %d\n" + " PC: %08lx SR: %08lx SP: %08lx FPCSR: %08lx\n", + smp_processor_id(), regs->pc, regs->sr, regs->sp, + regs->fpcsr); + pr_info("GPR00: %08lx GPR01: %08lx GPR02: %08lx GPR03: %08lx\n", + 0L, regs->gpr[1], regs->gpr[2], regs->gpr[3]); + pr_info("GPR04: %08lx GPR05: %08lx GPR06: %08lx GPR07: %08lx\n", + regs->gpr[4], regs->gpr[5], regs->gpr[6], regs->gpr[7]); + pr_info("GPR08: %08lx GPR09: %08lx GPR10: %08lx GPR11: %08lx\n", + regs->gpr[8], regs->gpr[9], regs->gpr[10], regs->gpr[11]); + pr_info("GPR12: %08lx GPR13: %08lx GPR14: %08lx GPR15: %08lx\n", + regs->gpr[12], regs->gpr[13], regs->gpr[14], regs->gpr[15]); + pr_info("GPR16: %08lx GPR17: %08lx GPR18: %08lx GPR19: %08lx\n", + regs->gpr[16], regs->gpr[17], regs->gpr[18], regs->gpr[19]); + pr_info("GPR20: %08lx GPR21: %08lx GPR22: %08lx GPR23: %08lx\n", + regs->gpr[20], regs->gpr[21], regs->gpr[22], regs->gpr[23]); + pr_info("GPR24: %08lx GPR25: %08lx GPR26: %08lx GPR27: %08lx\n", + regs->gpr[24], regs->gpr[25], regs->gpr[26], regs->gpr[27]); + pr_info("GPR28: %08lx GPR29: %08lx GPR30: %08lx GPR31: %08lx\n", + regs->gpr[28], regs->gpr[29], regs->gpr[30], regs->gpr[31]); + pr_info(" RES: %08lx oGPR11: %08lx\n", + regs->gpr[11], regs->orig_gpr11); + + pr_info("Process %s (pid: %d, stackpage=3D%08lx)\n", + current->comm, current->pid, (unsigned long)current); /* * When in-kernel, we also print out the stack and code at the * time of the fault.. */ if (in_kernel) { =20 - printk("\nStack: "); + pr_info("\nStack: "); show_stack(NULL, (unsigned long *)esp, KERN_EMERG); =20 if (esp < PAGE_OFFSET) goto bad_stack; =20 - printk("\n"); + pr_info("\n"); for (i =3D -8; i < 24; i +=3D 1) { unsigned long word; =20 if (__get_user(word, &((unsigned long *)esp)[i])) { bad_stack: - printk(" Bad Stack value."); + pr_info(" Bad Stack value."); break; } =20 print_data(esp, word, i); } =20 - printk("\nCode: "); + pr_info("\nCode: "); if (regs->pc < PAGE_OFFSET) goto bad; =20 @@ -142,14 +142,14 @@ void show_registers(struct pt_regs *regs) =20 if (__get_user(word, &((unsigned long *)regs->pc)[i])) { bad: - printk(" Bad PC value."); + pr_info(" Bad PC value."); break; } =20 print_data(regs->pc, word, i); } } - printk("\n"); + pr_info("\n"); } =20 /* This is normally the 'Oops' routine */ @@ -157,10 +157,10 @@ void __noreturn die(const char *str, struct pt_regs *= regs, long err) { =20 console_verbose(); - printk("\n%s#: %04lx\n", str, err & 0xffff); + pr_emerg("\n%s#: %04lx\n", str, err & 0xffff); show_registers(regs); #ifdef CONFIG_JUMP_UPON_UNHANDLED_EXCEPTION - printk("\n\nUNHANDLED_EXCEPTION: entering infinite loop\n"); + pr_emerg("\n\nUNHANDLED_EXCEPTION: entering infinite loop\n"); =20 /* shut down interrupts */ local_irq_disable(); @@ -173,8 +173,8 @@ void __noreturn die(const char *str, struct pt_regs *re= gs, long err) =20 asmlinkage void unhandled_exception(struct pt_regs *regs, int ea, int vect= or) { - printk("Unable to handle exception at EA =3D0x%x, vector 0x%x", - ea, vector); + pr_emerg("Unable to handle exception at EA =3D0x%x, vector 0x%x", + ea, vector); die("Oops", regs, 9); } =20 @@ -211,7 +211,7 @@ asmlinkage void do_unaligned_access(struct pt_regs *reg= s, unsigned long address) /* Send a SIGBUS */ force_sig_fault(SIGBUS, BUS_ADRALN, (void __user *)address); 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[86.9.131.95]) by smtp.gmail.com with ESMTPSA id q3-20020adff943000000b00346cc85c821sm1596160wrr.89.2024.04.11.11.07.11 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 11 Apr 2024 11:07:11 -0700 (PDT) From: Stafford Horne To: LKML Cc: Linux OpenRISC , Stafford Horne , Jonas Bonn , Stefan Kristiansson Subject: [PATCH 2/5] openrisc: traps: Remove calls to show_registers before die Date: Thu, 11 Apr 2024 19:06:29 +0100 Message-ID: <20240411180644.2023991-3-shorne@gmail.com> X-Mailer: git-send-email 2.44.0 In-Reply-To: <20240411180644.2023991-1-shorne@gmail.com> References: <20240411180644.2023991-1-shorne@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The die function calls show_registers unconditionally. Remove calls to show_registers before calling die to avoid printing all registers and stack status two times during a crash. This was found when testing kernel trap and floating point exception handling. Signed-off-by: Stafford Horne --- arch/openrisc/kernel/traps.c | 3 --- 1 file changed, 3 deletions(-) diff --git a/arch/openrisc/kernel/traps.c b/arch/openrisc/kernel/traps.c index 6d0fee912747..88fe27e4c10c 100644 --- a/arch/openrisc/kernel/traps.c +++ b/arch/openrisc/kernel/traps.c @@ -212,7 +212,6 @@ asmlinkage void do_unaligned_access(struct pt_regs *reg= s, unsigned long address) force_sig_fault(SIGBUS, BUS_ADRALN, (void __user *)address); } else { pr_emerg("KERNEL: Unaligned Access 0x%.8lx\n", address); - show_registers(regs); die("Die:", regs, address); } =20 @@ -225,7 +224,6 @@ asmlinkage void do_bus_fault(struct pt_regs *regs, unsi= gned long address) force_sig_fault(SIGBUS, BUS_ADRERR, (void __user *)address); } else { /* Kernel mode */ pr_emerg("KERNEL: Bus error (SIGBUS) 0x%.8lx\n", address); - show_registers(regs); die("Die:", regs, address); } } @@ -421,7 +419,6 @@ asmlinkage void do_illegal_instruction(struct pt_regs *= regs, } else { /* Kernel mode */ pr_emerg("KERNEL: Illegal instruction (SIGILL) 0x%.8lx\n", address); - show_registers(regs); die("Die:", regs, address); } } --=20 2.44.0 From nobody Sun Feb 8 20:28:55 2026 Received: from mail-wm1-f51.google.com (mail-wm1-f51.google.com [209.85.128.51]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E7154502B5; Thu, 11 Apr 2024 18:07:16 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.128.51 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1712858838; cv=none; b=b0XKxFScUR/UBWerJsxqXMrLCXFlSJdAWmmfyJYi0CoZ4XDTWeKLU7vicivGs8cTH+ArOgBhMre4bzYCuCEzl6v1x59lu8W2ucfWtvXL56ywriI237P9ad+RWLJ2Ll6HkmiM0Vs0FAHxAoigQI0w0fZMJsvuektOKC/pWSMa1Ok= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1712858838; c=relaxed/simple; bh=VTwDf1eIoFfkhnb1xTaX228Fa2ijGUtozSt1/ABt9iE=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=MO5LJU/OpXAxGY4Hr3U61KHsNpd6/KOpG3FCr+IyGz2CnOAtZ+HudareFPujZ/wVWaBWlwe+Uz89HlDOW71jgzjTODTlUkCwQ+3dNWFLU60r12M9hUMvIkyCv/HwsJRDCvMC4CZtcxJmJ3Hy6EkWeTtlo0KvdZxSCjxfn+HCSgc= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=gSMjw9OM; arc=none smtp.client-ip=209.85.128.51 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="gSMjw9OM" Received: by mail-wm1-f51.google.com with SMTP id 5b1f17b1804b1-41650ee55ffso999755e9.0; Thu, 11 Apr 2024 11:07:16 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1712858835; x=1713463635; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=lVvsMWg3g1l53yb/VOtobt7muDfFc+ZRjL66sH9ZIAM=; b=gSMjw9OMSwPj+MazlFiWovPbbj2ZbPBGMgafT4/TAH/xTgs/FIND9uYmsNgZ0aMSVu 1OxxjmfP1F0dbjpdIUUCzBPISuXOYlU34+SBvTjLfJkCko9+9U6NlBCXCrbuEAcCp4RT AOZE6Fz/VE2rNwTisjCjw1F4Kz043wNkeQRtVRxdqd9SMk0S4GBpzXqRGP8LKCyLaFXo cv00d0zxhpvR4ckVs0FZdzYvNL3uKD1XaHK3lyt7VXJSdoNL8JWd7rnWnIqGukdpcRmf cUs5qd1aBDpPAsXmay8q74jsLCNlRbSeXQYiJboWIAfZ9Eny8TRRyJYQFirIOpjcyCYW tgqQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1712858835; x=1713463635; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=lVvsMWg3g1l53yb/VOtobt7muDfFc+ZRjL66sH9ZIAM=; b=Q8yzji8BbcG/FlA36POQRZGsFwjjbzN2PUnbg+DQ4P6YVzAZH0D5yXJdotCv3K7s+u MQ/3ziwBywOAecCR/fYXTJTQKs44FgI7aLZ8TZpzK8AqyqW/4ntHU/9pQxcHP9LJRnZV F9WbEERSv5IVldXYTRaA2snhx2IHbLioki7jHbxj8O0oZxrVAYRSCnrsPi2ekXDwS7Jj xTN89KgnQ+4a1fpn7r/6zcABYt3l6CHE8e4yMub3h40RYxBgLbpEl4vAup241TfcG9Ay IZBgtWWc3PuoITQXynwqQr84NqtfdHb5sAKI1Me5fvDpPj30a/ce51Gs7SkUCaVORwq5 E/FA== X-Gm-Message-State: AOJu0Yx/1MB0dmszN6PeVKaexFd37vhQRV2TygzwR5INWvejeVxah0aM H6rL6uoQhxUIWeC6c3NFtIe5G/siHmyVbHrfC64T38rvv+9OLkhO8ox19Q== X-Google-Smtp-Source: AGHT+IG6CYcwC8MOg0ahDpnU5pBsLYZFcbAyp4xXvk24Xg2qWT9RZQeJUfD/q1YQYhivwdtB9dHryA== X-Received: by 2002:a05:600c:3547:b0:416:447c:967 with SMTP id i7-20020a05600c354700b00416447c0967mr355208wmq.22.1712858834402; Thu, 11 Apr 2024 11:07:14 -0700 (PDT) Received: from localhost (cpc1-brnt4-2-0-cust862.4-2.cable.virginm.net. [86.9.131.95]) by smtp.gmail.com with ESMTPSA id g13-20020a05600c4ecd00b004148d7b889asm6236802wmq.8.2024.04.11.11.07.13 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 11 Apr 2024 11:07:13 -0700 (PDT) From: Stafford Horne To: LKML Cc: Linux OpenRISC , Stafford Horne , Jonas Bonn , Stefan Kristiansson Subject: [PATCH 3/5] openrisc: traps: Don't send signals to kernel mode threads Date: Thu, 11 Apr 2024 19:06:30 +0100 Message-ID: <20240411180644.2023991-4-shorne@gmail.com> X-Mailer: git-send-email 2.44.0 In-Reply-To: <20240411180644.2023991-1-shorne@gmail.com> References: <20240411180644.2023991-1-shorne@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" OpenRISC exception handling sends signals to user processes on floating point exceptions and trap instructions (for debugging) among others. There is a bug where the trap handling logic may send signals to kernel threads, we should not send these signals to kernel threads, if that happens we treat it as an error. This patch adds conditions to die if the kernel receives these exceptions in kernel mode code. Fixes: 27267655c531 ("openrisc: Support floating point user api") Signed-off-by: Stafford Horne --- arch/openrisc/kernel/traps.c | 48 ++++++++++++++++++++++-------------- 1 file changed, 29 insertions(+), 19 deletions(-) diff --git a/arch/openrisc/kernel/traps.c b/arch/openrisc/kernel/traps.c index 88fe27e4c10c..211ddaa0c5fa 100644 --- a/arch/openrisc/kernel/traps.c +++ b/arch/openrisc/kernel/traps.c @@ -180,29 +180,39 @@ asmlinkage void unhandled_exception(struct pt_regs *r= egs, int ea, int vector) =20 asmlinkage void do_fpe_trap(struct pt_regs *regs, unsigned long address) { - int code =3D FPE_FLTUNK; - unsigned long fpcsr =3D regs->fpcsr; - - if (fpcsr & SPR_FPCSR_IVF) - code =3D FPE_FLTINV; - else if (fpcsr & SPR_FPCSR_OVF) - code =3D FPE_FLTOVF; - else if (fpcsr & SPR_FPCSR_UNF) - code =3D FPE_FLTUND; - else if (fpcsr & SPR_FPCSR_DZF) - code =3D FPE_FLTDIV; - else if (fpcsr & SPR_FPCSR_IXF) - code =3D FPE_FLTRES; - - /* Clear all flags */ - regs->fpcsr &=3D ~SPR_FPCSR_ALLF; - - force_sig_fault(SIGFPE, code, (void __user *)regs->pc); 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[86.9.131.95]) by smtp.gmail.com with ESMTPSA id h18-20020a5d4312000000b003455e5d2569sm2375949wrq.0.2024.04.11.11.07.15 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 11 Apr 2024 11:07:16 -0700 (PDT) From: Stafford Horne To: LKML Cc: Linux OpenRISC , Stafford Horne , Jonas Bonn , Stefan Kristiansson , Oleg Nesterov Subject: [PATCH 4/5] openrisc: Add FPU config Date: Thu, 11 Apr 2024 19:06:31 +0100 Message-ID: <20240411180644.2023991-5-shorne@gmail.com> X-Mailer: git-send-email 2.44.0 In-Reply-To: <20240411180644.2023991-1-shorne@gmail.com> References: <20240411180644.2023991-1-shorne@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Allow disabling FPU related code sequences to save space. Signed-off-by: Stafford Horne --- arch/openrisc/Kconfig | 9 +++++++++ arch/openrisc/kernel/ptrace.c | 6 ++++++ arch/openrisc/kernel/traps.c | 3 ++- 3 files changed, 17 insertions(+), 1 deletion(-) diff --git a/arch/openrisc/Kconfig b/arch/openrisc/Kconfig index 3586cda55bde..69c0258700b2 100644 --- a/arch/openrisc/Kconfig +++ b/arch/openrisc/Kconfig @@ -188,6 +188,15 @@ config SMP =20 If you don't know what to do here, say N. =20 +config FPU + bool "FPU support" + default y + help + Say N here if you want to disable all floating-point related procedures + in the kernel and reduce binary size. + + If you don't know what to do here, say Y. + source "kernel/Kconfig.hz" =20 config OPENRISC_NO_SPR_SR_DSX diff --git a/arch/openrisc/kernel/ptrace.c b/arch/openrisc/kernel/ptrace.c index 1eeac3b62e9d..cf410193095f 100644 --- a/arch/openrisc/kernel/ptrace.c +++ b/arch/openrisc/kernel/ptrace.c @@ -88,6 +88,7 @@ static int genregs_set(struct task_struct *target, return ret; } =20 +#ifdef CONFIG_FPU /* * As OpenRISC shares GPRs and floating point registers we don't need to e= xport * the floating point registers again. So here we only export the fpcsr s= pecial @@ -115,13 +116,16 @@ static int fpregs_set(struct task_struct *target, ®s->fpcsr, 0, 4); return ret; } +#endif =20 /* * Define the register sets available on OpenRISC under Linux */ enum or1k_regset { REGSET_GENERAL, +#ifdef CONFIG_FPU REGSET_FPU, +#endif }; =20 static const struct user_regset or1k_regsets[] =3D { @@ -133,6 +137,7 @@ static const struct user_regset or1k_regsets[] =3D { .regset_get =3D genregs_get, .set =3D genregs_set, }, +#ifdef CONFIG_FPU [REGSET_FPU] =3D { .core_note_type =3D NT_PRFPREG, .n =3D sizeof(struct __or1k_fpu_state) / sizeof(long), @@ -141,6 +146,7 @@ static const struct user_regset or1k_regsets[] =3D { .regset_get =3D fpregs_get, .set =3D fpregs_set, }, +#endif }; =20 static const struct user_regset_view user_or1k_native_view =3D { diff --git a/arch/openrisc/kernel/traps.c b/arch/openrisc/kernel/traps.c index 211ddaa0c5fa..57e0d674eb04 100644 --- a/arch/openrisc/kernel/traps.c +++ b/arch/openrisc/kernel/traps.c @@ -182,6 +182,7 @@ asmlinkage void do_fpe_trap(struct pt_regs *regs, unsig= ned long address) { if (user_mode(regs)) { int code =3D FPE_FLTUNK; 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[86.9.131.95]) by smtp.gmail.com with ESMTPSA id o9-20020a5d6709000000b00343956e8852sm2309447wru.42.2024.04.11.11.07.23 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 11 Apr 2024 11:07:23 -0700 (PDT) From: Stafford Horne To: LKML Cc: Linux OpenRISC , Stafford Horne , Jonas Bonn , Stefan Kristiansson , Oleg Nesterov Subject: [PATCH 5/5] openrisc: Move FPU state out of pt_regs Date: Thu, 11 Apr 2024 19:06:32 +0100 Message-ID: <20240411180644.2023991-6-shorne@gmail.com> X-Mailer: git-send-email 2.44.0 In-Reply-To: <20240411180644.2023991-1-shorne@gmail.com> References: <20240411180644.2023991-1-shorne@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" My original, naive, FPU support patch had the FPCSR register stored during both the *mode switch* and *context switch*. This is wasteful. Also, the original patches did not save the FPU state when handling signals during the system call fast path. We fix this by moving the FPCSR state to thread_struct in task_struct. We also introduce new helper functions save_fpu and restore_fpu which can be used to sync the FPU with thread_struct. These functions are now called when needed: - Setting up and restoring sigcontext when handling signals - Before and after __switch_to during context switches - When handling FPU exceptions - When reading and writing FPU register sets In the future we can further optimize this by doing lazy FPU save and restore. For example, FPU sync is not needed when switching to and from kernel threads (x86 does this). FPU save and restore does not need to be done two times if we have both rescheduling and signal work to do. However, since OpenRISC FPU state is a single register, I leave these optimizations for future consideration. Signed-off-by: Stafford Horne --- arch/openrisc/include/asm/fpu.h | 22 ++++++++++++++++ arch/openrisc/include/asm/processor.h | 1 + arch/openrisc/include/asm/ptrace.h | 3 +-- arch/openrisc/kernel/entry.S | 15 +---------- arch/openrisc/kernel/process.c | 5 ++++ arch/openrisc/kernel/ptrace.c | 12 +++------ arch/openrisc/kernel/signal.c | 36 +++++++++++++++++++++++++-- arch/openrisc/kernel/traps.c | 14 +++++++---- 8 files changed, 76 insertions(+), 32 deletions(-) create mode 100644 arch/openrisc/include/asm/fpu.h diff --git a/arch/openrisc/include/asm/fpu.h b/arch/openrisc/include/asm/fp= u.h new file mode 100644 index 000000000000..57bc44d80d53 --- /dev/null +++ b/arch/openrisc/include/asm/fpu.h @@ -0,0 +1,22 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#ifndef __ASM_OPENRISC_FPU_H +#define __ASM_OPENRISC_FPU_H + +struct task_struct; + +#ifdef CONFIG_FPU +static inline void save_fpu(struct task_struct *task) +{ + task->thread.fpcsr =3D mfspr(SPR_FPCSR); +} + +static inline void restore_fpu(struct task_struct *task) +{ + mtspr(SPR_FPCSR, task->thread.fpcsr); +} +#else +#define save_fpu(tsk) do { } while (0) +#define restore_fpu(tsk) do { } while (0) +#endif + +#endif /* __ASM_OPENRISC_FPU_H */ diff --git a/arch/openrisc/include/asm/processor.h b/arch/openrisc/include/= asm/processor.h index 3b736e74e6ed..e05d1b59e24e 100644 --- a/arch/openrisc/include/asm/processor.h +++ b/arch/openrisc/include/asm/processor.h @@ -44,6 +44,7 @@ struct task_struct; =20 struct thread_struct { + long fpcsr; /* Floating point control status register. */ }; =20 /* diff --git a/arch/openrisc/include/asm/ptrace.h b/arch/openrisc/include/asm= /ptrace.h index 375147ff71fc..1da3e66292e2 100644 --- a/arch/openrisc/include/asm/ptrace.h +++ b/arch/openrisc/include/asm/ptrace.h @@ -59,7 +59,7 @@ struct pt_regs { * -1 for all other exceptions. */ long orig_gpr11; /* For restarting system calls */ - long fpcsr; /* Floating point control status register. */ + long dummy; /* Cheap alignment fix */ long dummy2; /* Cheap alignment fix */ }; =20 @@ -115,6 +115,5 @@ static inline long regs_return_value(struct pt_regs *re= gs) #define PT_GPR31 124 #define PT_PC 128 #define PT_ORIG_GPR11 132 -#define PT_FPCSR 136 =20 #endif /* __ASM_OPENRISC_PTRACE_H */ diff --git a/arch/openrisc/kernel/entry.S b/arch/openrisc/kernel/entry.S index c9f48e750b72..440711d7bf40 100644 --- a/arch/openrisc/kernel/entry.S +++ b/arch/openrisc/kernel/entry.S @@ -106,8 +106,6 @@ l.mtspr r0,r3,SPR_EPCR_BASE ;\ l.lwz r3,PT_SR(r1) ;\ l.mtspr r0,r3,SPR_ESR_BASE ;\ - l.lwz r3,PT_FPCSR(r1) ;\ - l.mtspr r0,r3,SPR_FPCSR ;\ l.lwz r2,PT_GPR2(r1) ;\ l.lwz r3,PT_GPR3(r1) ;\ l.lwz r4,PT_GPR4(r1) ;\ @@ -177,8 +175,6 @@ handler: ;\ /* r30 already save */ ;\ l.sw PT_GPR31(r1),r31 ;\ TRACE_IRQS_OFF_ENTRY ;\ - l.mfspr r30,r0,SPR_FPCSR ;\ - l.sw PT_FPCSR(r1),r30 ;\ /* Store -1 in orig_gpr11 for non-syscall exceptions */ ;\ l.addi r30,r0,-1 ;\ l.sw PT_ORIG_GPR11(r1),r30 @@ -219,8 +215,6 @@ handler: ;\ /* Store -1 in orig_gpr11 for non-syscall exceptions */ ;\ l.addi r30,r0,-1 ;\ l.sw PT_ORIG_GPR11(r1),r30 ;\ - l.mfspr r30,r0,SPR_FPCSR ;\ - l.sw PT_FPCSR(r1),r30 ;\ l.addi r3,r1,0 ;\ /* r4 is exception EA */ ;\ l.addi r5,r0,vector ;\ @@ -852,6 +846,7 @@ _syscall_badsys: =20 EXCEPTION_ENTRY(_fpe_trap_handler) CLEAR_LWA_FLAG(r3) + /* r4: EA of fault (set by EXCEPTION_HANDLE) */ l.jal do_fpe_trap l.addi r3,r1,0 /* pt_regs */ @@ -1100,10 +1095,6 @@ ENTRY(_switch) l.sw PT_GPR28(r1),r28 l.sw PT_GPR30(r1),r30 =20 - /* Store the old FPU state to new pt_regs */ - l.mfspr r29,r0,SPR_FPCSR - l.sw PT_FPCSR(r1),r29 - l.addi r11,r10,0 /* Save old 'current' to 'last' return value*/ =20 /* We use thread_info->ksp for storing the address of the above @@ -1126,10 +1117,6 @@ ENTRY(_switch) l.lwz r29,PT_SP(r1) l.sw TI_KSP(r10),r29 =20 - /* Restore the old value of FPCSR */ - l.lwz r29,PT_FPCSR(r1) - l.mtspr r0,r29,SPR_FPCSR - /* ...and restore the registers, except r11 because the return value * has already been set above. */ diff --git a/arch/openrisc/kernel/process.c b/arch/openrisc/kernel/process.c index 3c27d1c72718..eef99fee2110 100644 --- a/arch/openrisc/kernel/process.c +++ b/arch/openrisc/kernel/process.c @@ -36,6 +36,7 @@ #include =20 #include +#include #include #include #include @@ -244,6 +245,8 @@ struct task_struct *__switch_to(struct task_struct *old, =20 local_irq_save(flags); =20 + save_fpu(current); + /* current_set is an array of saved current pointers * (one for each cpu). we need them at user->kernel transition, * while we save them at kernel->user transition @@ -256,6 +259,8 @@ struct task_struct *__switch_to(struct task_struct *old, current_thread_info_set[smp_processor_id()] =3D new_ti; last =3D (_switch(old_ti, new_ti))->task; =20 + restore_fpu(current); + local_irq_restore(flags); =20 return last; diff --git a/arch/openrisc/kernel/ptrace.c b/arch/openrisc/kernel/ptrace.c index cf410193095f..5091b18eab4c 100644 --- a/arch/openrisc/kernel/ptrace.c +++ b/arch/openrisc/kernel/ptrace.c @@ -98,9 +98,7 @@ static int fpregs_get(struct task_struct *target, const struct user_regset *regset, struct membuf to) { - const struct pt_regs *regs =3D task_pt_regs(target); - - return membuf_store(&to, regs->fpcsr); + return membuf_store(&to, target->thread.fpcsr); } =20 static int fpregs_set(struct task_struct *target, @@ -108,13 +106,9 @@ static int fpregs_set(struct task_struct *target, unsigned int pos, unsigned int count, const void *kbuf, const void __user *ubuf) { - struct pt_regs *regs =3D task_pt_regs(target); - int ret; - /* FPCSR */ - ret =3D user_regset_copyin(&pos, &count, &kbuf, &ubuf, - ®s->fpcsr, 0, 4); - return ret; + return user_regset_copyin(&pos, &count, &kbuf, &ubuf, + &target->thread.fpcsr, 0, 4); } #endif =20 diff --git a/arch/openrisc/kernel/signal.c b/arch/openrisc/kernel/signal.c index e2f21a5d8ad9..c7ab42e2cb7a 100644 --- a/arch/openrisc/kernel/signal.c +++ b/arch/openrisc/kernel/signal.c @@ -23,6 +23,7 @@ #include #include =20 +#include #include #include #include @@ -39,6 +40,37 @@ asmlinkage long _sys_rt_sigreturn(struct pt_regs *regs); asmlinkage int do_work_pending(struct pt_regs *regs, unsigned int thread_f= lags, int syscall); =20 +#ifdef CONFIG_FPU +static long restore_fp_state(struct sigcontext __user *sc) +{ + long err; + + err =3D __copy_from_user(¤t->thread.fpcsr, &sc->fpcsr, sizeof(unsig= ned long)); + if (unlikely(err)) + return err; + + /* Restore the FPU state */ + restore_fpu(current); + + return 0; +} + +static long save_fp_state(struct sigcontext __user *sc) +{ + long err; + + /* Sync the user FPU state so we can copy to sigcontext */ + save_fpu(current); + + err =3D __copy_to_user(&sc->fpcsr, ¤t->thread.fpcsr, sizeof(unsigne= d long)); + + return err; +} +#else +#define save_fp_state(sc) (0) +#define restore_fp_state(sc) (0) +#endif + static int restore_sigcontext(struct pt_regs *regs, struct sigcontext __user *sc) { @@ -55,7 +87,7 @@ static int restore_sigcontext(struct pt_regs *regs, err |=3D __copy_from_user(regs, sc->regs.gpr, 32 * sizeof(unsigned long)); err |=3D __copy_from_user(®s->pc, &sc->regs.pc, sizeof(unsigned long)); err |=3D __copy_from_user(®s->sr, &sc->regs.sr, sizeof(unsigned long)); - err |=3D __copy_from_user(®s->fpcsr, &sc->fpcsr, sizeof(unsigned long)= ); + err |=3D restore_fp_state(sc); =20 /* make sure the SM-bit is cleared so user-mode cannot fool us */ regs->sr &=3D ~SPR_SR_SM; @@ -118,7 +150,7 @@ static int setup_sigcontext(struct pt_regs *regs, struc= t sigcontext __user *sc) err |=3D __copy_to_user(sc->regs.gpr, regs, 32 * sizeof(unsigned long)); err |=3D __copy_to_user(&sc->regs.pc, ®s->pc, sizeof(unsigned long)); err |=3D __copy_to_user(&sc->regs.sr, ®s->sr, sizeof(unsigned long)); - err |=3D __copy_to_user(&sc->fpcsr, ®s->fpcsr, sizeof(unsigned long)); + err |=3D save_fp_state(sc); =20 return err; } diff --git a/arch/openrisc/kernel/traps.c b/arch/openrisc/kernel/traps.c index 57e0d674eb04..c195be9cc9fc 100644 --- a/arch/openrisc/kernel/traps.c +++ b/arch/openrisc/kernel/traps.c @@ -31,6 +31,7 @@ #include =20 #include +#include #include #include #include @@ -84,9 +85,8 @@ void show_registers(struct pt_regs *regs) in_kernel =3D 0; =20 pr_info("CPU #: %d\n" - " PC: %08lx SR: %08lx SP: %08lx FPCSR: %08lx\n", - smp_processor_id(), regs->pc, regs->sr, regs->sp, - regs->fpcsr); + " PC: %08lx SR: %08lx SP: %08lx\n", + smp_processor_id(), regs->pc, regs->sr, regs->sp); pr_info("GPR00: %08lx GPR01: %08lx GPR02: %08lx GPR03: %08lx\n", 0L, regs->gpr[1], regs->gpr[2], regs->gpr[3]); pr_info("GPR04: %08lx GPR05: %08lx GPR06: %08lx GPR07: %08lx\n", @@ -183,7 +183,10 @@ asmlinkage void do_fpe_trap(struct pt_regs *regs, unsi= gned long address) if (user_mode(regs)) { int code =3D FPE_FLTUNK; #ifdef CONFIG_FPU - unsigned long fpcsr =3D regs->fpcsr; + unsigned long fpcsr; + + save_fpu(current); + fpcsr =3D current->thread.fpcsr; =20 if (fpcsr & SPR_FPCSR_IVF) code =3D FPE_FLTINV; @@ -197,7 +200,8 @@ asmlinkage void do_fpe_trap(struct pt_regs *regs, unsig= ned long address) code =3D FPE_FLTRES; =20 /* Clear all flags */ - regs->fpcsr &=3D ~SPR_FPCSR_ALLF; + current->thread.fpcsr &=3D ~SPR_FPCSR_ALLF; + restore_fpu(current); #endif force_sig_fault(SIGFPE, code, (void __user *)regs->pc); } else { --=20 2.44.0