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(unknown [IPv6:240e:358:113e:f100:dc73:854d:832e:8]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (P-384) server-digest SHA384) (Client did not present a certificate) (Authenticated sender: xry111@xry111.site) by xry111.site (Postfix) with ESMTPSA id E080E67232; Thu, 11 Apr 2024 06:48:54 -0400 (EDT) From: Xi Ruoyao To: Dave Hansen , Michael Kelley , Pawan Gupta Cc: Andy Lutomirski , Peter Zijlstra , Thomas Gleixner , Ingo Molnar , Borislav Petkov , "H. Peter Anvin" , x86@kernel.org, linux-kernel@vger.kernel.org, Xi Ruoyao , Sean Christopherson , Andrew Cooper Subject: [PATCH v6] x86/mm: Don't disable INVLPG if "incomplete Global INVLPG flushes" is fixed by microcode or the kernel is running in a hypervisor Date: Thu, 11 Apr 2024 18:48:22 +0800 Message-ID: <20240411104822.6429-1-xry111@xry111.site> X-Mailer: git-send-email 2.44.0 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Per the "Processor Specification Update" documentations referred by the intel-microcode-20240312 release note, this microcode release has fixed the issue for all affected models. So don't disable INVLPG if the microcode is new enough. The precise minimum microcode revision fixing the issue is provided by engineer from Intel. And the erratum says: This erratum does not apply in VMX non-root operation. It applies only when PCIDs are enabled and either in VMX root operation or outside VMX operation. So if the kernel is running in a hypervisor, we are in VMX non-root operation and we should be safe. Cc: Dave Hansen Cc: Michael Kelley Cc: Pawan Gupta Cc: Sean Christopherson Cc: Andrew Cooper Link: https://lore.kernel.org/all/168436059559.404.13934972543631851306.tip= -bot2@tip-bot2/ Link: https://github.com/intel/Intel-Linux-Processor-Microcode-Data-Files/r= eleases/tag/microcode-20240312 Link: https://cdrdv2.intel.com/v1/dl/getContent/740518 # RPL042, rev. 13 Link: https://cdrdv2.intel.com/v1/dl/getContent/682436 # ADL063, rev. 24 Link: https://lore.kernel.org/all/20240325231300.qrltbzf6twm43ftb@desk/ Signed-off-by: Xi Ruoyao --- arch/x86/mm/init.c | 41 +++++++++++++++++++++++++++++------------ 1 file changed, 29 insertions(+), 12 deletions(-) diff --git a/arch/x86/mm/init.c b/arch/x86/mm/init.c index 679893ea5e68..e69d227ea123 100644 --- a/arch/x86/mm/init.c +++ b/arch/x86/mm/init.c @@ -261,33 +261,50 @@ static void __init probe_page_size_mask(void) } } =20 -#define INTEL_MATCH(_model) { .vendor =3D X86_VENDOR_INTEL, \ - .family =3D 6, \ - .model =3D _model, \ - } +#define INTEL_MATCH(_model, _fixed_microcode) \ + { \ + .vendor =3D X86_VENDOR_INTEL, \ + .family =3D 6, \ + .model =3D _model, \ + .driver_data =3D _fixed_microcode, \ + } + /* * INVLPG may not properly flush Global entries - * on these CPUs when PCIDs are enabled. + * on these CPUs when PCIDs are enabled and the + * microcode is not updated to fix the issue. */ static const struct x86_cpu_id invlpg_miss_ids[] =3D { - INTEL_MATCH(INTEL_FAM6_ALDERLAKE ), - INTEL_MATCH(INTEL_FAM6_ALDERLAKE_L ), - INTEL_MATCH(INTEL_FAM6_ATOM_GRACEMONT ), - INTEL_MATCH(INTEL_FAM6_RAPTORLAKE ), - INTEL_MATCH(INTEL_FAM6_RAPTORLAKE_P), - INTEL_MATCH(INTEL_FAM6_RAPTORLAKE_S), + INTEL_MATCH(INTEL_FAM6_ALDERLAKE, 0x2e), + INTEL_MATCH(INTEL_FAM6_ALDERLAKE_L, 0x42c), + INTEL_MATCH(INTEL_FAM6_ATOM_GRACEMONT, 0x11), + INTEL_MATCH(INTEL_FAM6_RAPTORLAKE, 0x118), + INTEL_MATCH(INTEL_FAM6_RAPTORLAKE_P, 0x4117), + INTEL_MATCH(INTEL_FAM6_RAPTORLAKE_S, 0x2e), {} }; =20 static void setup_pcid(void) { + const struct x86_cpu_id *invlpg_miss_match; + if (!IS_ENABLED(CONFIG_X86_64)) return; =20 if (!boot_cpu_has(X86_FEATURE_PCID)) return; =20 - if (x86_match_cpu(invlpg_miss_ids)) { + invlpg_miss_match =3D x86_match_cpu(invlpg_miss_ids); + + /* + * The Intel errata claims: "this erratum does not apply in VMX + * non-root operation. It applies only when PCIDs are enabled + * and either in VMX root operation or outside VMX operation." + * So we are safe if we are surely running in a hypervisor. + */ + if (!boot_cpu_has(X86_FEATURE_HYPERVISOR) && + invlpg_miss_match && + boot_cpu_data.microcode < invlpg_miss_match->driver_data) { pr_info("Incomplete global flushes, disabling PCID"); setup_clear_cpu_cap(X86_FEATURE_PCID); return; --=20 2.44.0