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([82.78.167.8]) by smtp.gmail.com with ESMTPSA id m2-20020a05600c3b0200b004171f151a5csm1679446wms.16.2024.04.10.05.27.21 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 10 Apr 2024 05:27:22 -0700 (PDT) From: Claudiu X-Google-Original-From: Claudiu To: geert+renesas@glider.be, mturquette@baylibre.com, sboyd@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, magnus.damm@gmail.com Cc: linux-renesas-soc@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, claudiu.beznea@tuxon.dev, Claudiu Beznea Subject: [PATCH v3 8/9] clk: renesas: rzg2l-cpg: Add suspend/resume support for power domains Date: Wed, 10 Apr 2024 15:26:56 +0300 Message-Id: <20240410122657.2051132-9-claudiu.beznea.uj@bp.renesas.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20240410122657.2051132-1-claudiu.beznea.uj@bp.renesas.com> References: <20240410122657.2051132-1-claudiu.beznea.uj@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Claudiu Beznea RZ/G3S supports deep sleep states that it can reach with the help of the TF-A. RZ/G3S has a few power domains (e.g. GIC) that need to be always-on while Linux is running. These domains are initialized (and powered on) when clock driver is probed. As the TF-A takes control at the very last(suspend)/first(resume) phase of configuring the deep sleep state, it can do it's own settings on power domains. Thus, to restore the proper Linux state, add rzg2l_cpg_resume() which powers on the always-on domains and rzg2l_cpg_complete() which activates the power down mode for the IPs selected through CPG_PWRDN_IP{1, 2}. Along with it, added the suspend_check member to the RZ/G2L power domain data structure whose purpose is to checks if a domain can be powered off while the system is going to suspend. This is necessary for the serial console domain which needs to be powered on if no_console_suspend is available in bootargs. Signed-off-by: Claudiu Beznea Reviewed-by: Geert Uytterhoeven --- Changes in v3: - populate pd->suspend_check on rzg2l_cpg_attach_dev() for serial console; due to this the rzg2l_pd_suspend_check_console() was moved before rzg2l_cpg_attach_dev() - removed RZG2L_PD_F_CONSOLE define Changes in v2: - none; this patch is new drivers/clk/renesas/rzg2l-cpg.c | 68 ++++++++++++++++++++++++++++++--- 1 file changed, 63 insertions(+), 5 deletions(-) diff --git a/drivers/clk/renesas/rzg2l-cpg.c b/drivers/clk/renesas/rzg2l-cp= g.c index b36700f4a9f5..baf08a8cc3f0 100644 --- a/drivers/clk/renesas/rzg2l-cpg.c +++ b/drivers/clk/renesas/rzg2l-cpg.c @@ -15,6 +15,7 @@ #include #include #include +#include #include #include #include @@ -139,6 +140,7 @@ struct rzg2l_pll5_mux_dsi_div_param { * @num_resets: Number of Module Resets in info->resets[] * @last_dt_core_clk: ID of the last Core Clock exported to DT * @info: Pointer to platform data + * @domains: generic PM domains * @mux_dsi_div_params: pll5 mux and dsi div parameters */ struct rzg2l_cpg_priv { @@ -155,6 +157,8 @@ struct rzg2l_cpg_priv { =20 const struct rzg2l_cpg_info *info; =20 + struct generic_pm_domain **domains; + struct rzg2l_pll5_mux_dsi_div_param mux_dsi_div_params; }; =20 @@ -1570,16 +1574,23 @@ struct rzg2l_cpg_pm_domains { * struct rzg2l_cpg_pd - RZ/G2L power domain data structure * @genpd: generic PM domain * @priv: pointer to CPG private data structure + * @suspend_check: check if domain could be powered off in suspend * @conf: CPG PM domain configuration info * @id: RZ/G2L power domain ID */ struct rzg2l_cpg_pd { struct generic_pm_domain genpd; struct rzg2l_cpg_priv *priv; + int (*suspend_check)(void); struct rzg2l_cpg_pm_domain_conf conf; u16 id; }; =20 +static int rzg2l_pd_suspend_check_console(void) +{ + return console_suspend_enabled ? 0 : -EBUSY; +} + static int rzg2l_cpg_attach_dev(struct generic_pm_domain *domain, struct d= evice *dev) { struct rzg2l_cpg_pd *pd =3D container_of(domain, struct rzg2l_cpg_pd, gen= pd); @@ -1615,6 +1626,10 @@ static int rzg2l_cpg_attach_dev(struct generic_pm_do= main *domain, struct device error); goto fail_put; } + + /* Add suspend check for console. */ + if (np =3D=3D of_stdout) + pd->suspend_check =3D rzg2l_pd_suspend_check_console; } else { of_node_put(clkspec.np); } @@ -1676,6 +1691,13 @@ static int rzg2l_cpg_power_off(struct generic_pm_dom= ain *domain) struct rzg2l_cpg_reg_conf pwrdn =3D pd->conf.pwrdn; struct rzg2l_cpg_priv *priv =3D pd->priv; =20 + if (pd->suspend_check) { + int ret =3D pd->suspend_check(); + + if (ret) + return ret; + } + /* Set MSTOP. */ if (mstop.mask) writel(mstop.mask | (mstop.mask << 16), priv->base + mstop.off); @@ -1687,8 +1709,9 @@ static int rzg2l_cpg_power_off(struct generic_pm_doma= in *domain) return 0; } =20 -static int __init rzg2l_cpg_pd_setup(struct rzg2l_cpg_pd *pd, bool always_= on) +static int __init rzg2l_cpg_pd_setup(struct rzg2l_cpg_pd *pd, u32 flags) { + bool always_on =3D !!(flags & RZG2L_PD_F_ALWAYS_ON); struct dev_power_governor *governor; =20 pd->genpd.flags |=3D GENPD_FLAG_PM_CLK | GENPD_FLAG_ACTIVE_WAKEUP; @@ -1719,7 +1742,7 @@ static int __init rzg2l_cpg_add_clk_domain(struct rzg= 2l_cpg_priv *priv) =20 pd->genpd.name =3D np->name; pd->priv =3D priv; - ret =3D rzg2l_cpg_pd_setup(pd, true); + ret =3D rzg2l_cpg_pd_setup(pd, RZG2L_PD_F_ALWAYS_ON); if (ret) return ret; =20 @@ -1778,13 +1801,13 @@ static int __init rzg2l_cpg_add_pm_domains(struct r= zg2l_cpg_priv *priv) domains->onecell_data.domains =3D domains->domains; domains->onecell_data.num_domains =3D info->num_pm_domains; domains->onecell_data.xlate =3D rzg2l_cpg_pm_domain_xlate; + priv->domains =3D domains->domains; =20 ret =3D devm_add_action_or_reset(dev, rzg2l_cpg_genpd_remove, &domains->o= necell_data); if (ret) return ret; =20 for (unsigned int i =3D 0; i < info->num_pm_domains; i++) { - bool always_on =3D !!(info->pm_domains[i].flags & RZG2L_PD_F_ALWAYS_ON); struct rzg2l_cpg_pd *pd; =20 pd =3D devm_kzalloc(dev, sizeof(*pd), GFP_KERNEL); @@ -1796,11 +1819,11 @@ static int __init rzg2l_cpg_add_pm_domains(struct r= zg2l_cpg_priv *priv) pd->id =3D info->pm_domains[i].id; pd->priv =3D priv; =20 - ret =3D rzg2l_cpg_pd_setup(pd, always_on); + ret =3D rzg2l_cpg_pd_setup(pd, info->pm_domains[i].flags); if (ret) return ret; =20 - if (always_on) { + if (info->pm_domains[i].flags & RZG2L_PD_F_ALWAYS_ON) { ret =3D rzg2l_cpg_power_on(&pd->genpd); if (ret) return ret; @@ -1890,9 +1913,43 @@ static int __init rzg2l_cpg_probe(struct platform_de= vice *pdev) if (error) return error; =20 + dev_set_drvdata(dev, priv); + + return 0; +} + +static int rzg2l_cpg_resume(struct device *dev) +{ + struct rzg2l_cpg_priv *priv =3D dev_get_drvdata(dev); + const struct rzg2l_cpg_info *info =3D priv->info; + + /* Power on always ON domains. */ + for (unsigned int i =3D 0; i < info->num_pm_domains; i++) { + if (info->pm_domains[i].flags & RZG2L_PD_F_ALWAYS_ON) { + int ret =3D rzg2l_cpg_power_on(priv->domains[i]); + + if (ret) + return ret; + } + } + return 0; } =20 +static void rzg2l_cpg_complete(struct device *dev) +{ + struct rzg2l_cpg_priv *priv =3D dev_get_drvdata(dev); + + /* Prepare for power down the BUSes in power down mode. */ + if (priv->info->pm_domain_pwrdn_mstop) + writel(CPG_PWRDN_MSTOP_ENABLE, priv->base + CPG_PWRDN_MSTOP); +} + +static const struct dev_pm_ops rzg2l_cpg_pm_ops =3D { + NOIRQ_SYSTEM_SLEEP_PM_OPS(NULL, rzg2l_cpg_resume) + .complete =3D rzg2l_cpg_complete, +}; + static const struct of_device_id rzg2l_cpg_match[] =3D { #ifdef CONFIG_CLK_R9A07G043 { @@ -1931,6 +1988,7 @@ static struct platform_driver rzg2l_cpg_driver =3D { .driver =3D { .name =3D "rzg2l-cpg", .of_match_table =3D rzg2l_cpg_match, + .pm =3D pm_sleep_ptr(&rzg2l_cpg_pm_ops), }, }; =20 --=20 2.39.2