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([2a01:e0a:999:a3a0:d4a6:5856:3e6c:3dff]) by smtp.gmail.com with ESMTPSA id d6-20020a056000114600b003456c693fa4sm9079086wrx.93.2024.04.10.02.11.20 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 10 Apr 2024 02:11:20 -0700 (PDT) From: =?UTF-8?q?Cl=C3=A9ment=20L=C3=A9ger?= To: Jonathan Corbet , Paul Walmsley , Palmer Dabbelt , Albert Ou , Conor Dooley , Rob Herring , Krzysztof Kozlowski , Anup Patel , Shuah Khan Cc: =?UTF-8?q?Cl=C3=A9ment=20L=C3=A9ger?= , Atish Patra , linux-doc@vger.kernel.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, kvm@vger.kernel.org, kvm-riscv@lists.infradead.org, linux-kselftest@vger.kernel.org Subject: [PATCH 08/10] riscv: hwprobe: export Zcmop ISA extension Date: Wed, 10 Apr 2024 11:11:01 +0200 Message-ID: <20240410091106.749233-9-cleger@rivosinc.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240410091106.749233-1-cleger@rivosinc.com> References: <20240410091106.749233-1-cleger@rivosinc.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Export Zcmop ISA extension through hwprobe. Signed-off-by: Cl=C3=A9ment L=C3=A9ger --- Documentation/arch/riscv/hwprobe.rst | 4 ++++ arch/riscv/include/uapi/asm/hwprobe.h | 1 + arch/riscv/kernel/sys_hwprobe.c | 1 + 3 files changed, 6 insertions(+) diff --git a/Documentation/arch/riscv/hwprobe.rst b/Documentation/arch/risc= v/hwprobe.rst index bf96b4e8ba3b..e3187659a077 100644 --- a/Documentation/arch/riscv/hwprobe.rst +++ b/Documentation/arch/riscv/hwprobe.rst @@ -212,6 +212,10 @@ The following keys are defined: ("Zcf doesn't exist on RV64 as it contains no instructions") of riscv-code-size-reduction. =20 + * :c:macro:`RISCV_HWPROBE_EXT_ZCMOP`: The Zcmop May-Be-Operations extens= ion is + supported as defined in the RISC-V ISA manual starting from commit + c732a4f39a4 ("Zcmop is ratified/1.0"). + * :c:macro:`RISCV_HWPROBE_KEY_CPUPERF_0`: A bitmask that contains performa= nce information about the selected set of processors. =20 diff --git a/arch/riscv/include/uapi/asm/hwprobe.h b/arch/riscv/include/uap= i/asm/hwprobe.h index dd4ad77faf49..d97ac5436447 100644 --- a/arch/riscv/include/uapi/asm/hwprobe.h +++ b/arch/riscv/include/uapi/asm/hwprobe.h @@ -64,6 +64,7 @@ struct riscv_hwprobe { #define RISCV_HWPROBE_EXT_ZCB (1ULL << 38) #define RISCV_HWPROBE_EXT_ZCD (1ULL << 39) #define RISCV_HWPROBE_EXT_ZCF (1ULL << 40) +#define RISCV_HWPROBE_EXT_ZCMOP (1ULL << 41) #define RISCV_HWPROBE_KEY_CPUPERF_0 5 #define RISCV_HWPROBE_MISALIGNED_UNKNOWN (0 << 0) #define RISCV_HWPROBE_MISALIGNED_EMULATED (1 << 0) diff --git a/arch/riscv/kernel/sys_hwprobe.c b/arch/riscv/kernel/sys_hwprob= e.c index 2ffa0fe5101e..9457231bd1c0 100644 --- a/arch/riscv/kernel/sys_hwprobe.c +++ b/arch/riscv/kernel/sys_hwprobe.c @@ -114,6 +114,7 @@ static void hwprobe_isa_ext0(struct riscv_hwprobe *pair, EXT_KEY(ZIMOP); EXT_KEY(ZCA); EXT_KEY(ZCB); + EXT_KEY(ZCMOP); =20 if (has_vector()) { EXT_KEY(ZVBB); --=20 2.43.0