From nobody Mon Feb 9 05:42:14 2026 Received: from smtpbgbr2.qq.com (smtpbgbr2.qq.com [54.207.22.56]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 022C62A8D0 for ; Wed, 10 Apr 2024 06:36:03 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=54.207.22.56 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1712730967; cv=none; b=Uw/2RgUzkKaN46twoH7CNWLG4kDSGw8dVAYdLPPX4/BcTat9fCdz9Vt9/fEfxJH/37Lgy7LbG2DwqZ0FDyppNkebsSiPp2YHE/2iDgi/8h0XCP/n53NlL2LFMMyFHUbT4yCOkSx7cBAwbkqieKgljHZIII16K4V4ByqkRgNJN/A= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1712730967; c=relaxed/simple; bh=5a+hJQQnLHHlog8fcMeQ0f8merXIfj/GMH3ul0Vfc20=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=Rz8Nw+0pSuq+tVKljvWvnl8A5qcdlvY9eVp9Eiu/RnD7incYYR70MXQ8/LQkL829IiZ16lQFFSpVdEW9sgHhb02UJDOahagQACPl2sGPCZcX5xb31m23aCcWA3RP5eBpned3vqyNDZIGLkEzBCI4cXMhsuvoAuCWP3Z93rWbdec= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=shingroup.cn; spf=pass smtp.mailfrom=shingroup.cn; arc=none smtp.client-ip=54.207.22.56 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=shingroup.cn Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=shingroup.cn X-QQ-mid: bizesmtp86t1712730886thpdkm0m X-QQ-Originating-IP: qpU6BkNfrlioxOZjNw8VTqRLhm3mvtT81kiLaWcj8Pg= Received: from HX01040082.powercore.com.cn ( [14.19.197.107]) by bizesmtp.qq.com (ESMTP) with id ; Wed, 10 Apr 2024 14:34:40 +0800 (CST) X-QQ-SSF: 01400000000000B09000000A0000000 X-QQ-FEAT: D5krnlQGVfJp7iXspNT0lTkPO8Udu5eTrn+UALAwa/e8Lqb/4MhOd1lEyMSHy N2wPq8W5p30FX8llAgW8imG47we+3g3Fo1yo5HgyW8M96H3F3ssWJkxTcy0OXRdB/vr9gmr mS0DLqFxtycu0CCFDmzd5ebDVl8a7Q/j4+H7qkanPQtPljkyYqK7Rfoe0tc0PQ4i3poBSLX d6ZPK9kUkqa4lwD0ThclcQOYw3TLid8PukXqye3Q9I2G4NPG6w3PCTcmc/QDw5Nx4hWAZPz gwxcP4Ww3uFikpG15UjY+P1A/xSBCNBueYSVr3c05t7kWDIYAu/nbf/M7azDrA6nDB0Y3Xx 0vSeCMGyTj0JTmqcRfzfp4NgTMcr2A/b/wNEmF8kB3hf8jcbfOdK5dz0eZcQ6Uy6dm7eTj4 pdGl7diJ0kTw42z4sOHctFwwmw/MCakR X-QQ-GoodBg: 2 X-BIZMAIL-ID: 17986055640822494182 From: Jinglin Wen To: palmer@dabbelt.com Cc: paul.walmsley@sifive.com, aou@eecs.berkeley.edu, gregkh@linuxfoundation.org, atishp@rivosinc.com, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, Jinglin Wen Subject: [PATCH 1/3] riscv: Support for early console. Date: Wed, 10 Apr 2024 14:34:30 +0800 Message-Id: <20240410063432.23058-2-jinglin.wen@shingroup.cn> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20240410063432.23058-1-jinglin.wen@shingroup.cn> References: <20240410063432.23058-1-jinglin.wen@shingroup.cn> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-QQ-SENDSIZE: 520 Feedback-ID: bizesmtp:shingroup.cn:qybglogicsvrgz:qybglogicsvrgz5a-2 Content-Type: text/plain; charset="utf-8" This feature is mainly used for debugging during the early startup process. Currently, the implementation of this function is based on the sbi interface. By setting the CONFIG_RISCV_EARLY_CONSOLE option, this function can be enabled, which subsequently sets the log level to CONSOLE_LOGLEVEL_MOTORMOUT. Signed-off-by: Jinglin Wen --- arch/riscv/include/asm/early_console.h | 23 ++++++ arch/riscv/kernel/Makefile | 1 + arch/riscv/kernel/early_console.c | 108 +++++++++++++++++++++++++ arch/riscv/kernel/setup.c | 2 + 4 files changed, 134 insertions(+) create mode 100644 arch/riscv/include/asm/early_console.h create mode 100644 arch/riscv/kernel/early_console.c diff --git a/arch/riscv/include/asm/early_console.h b/arch/riscv/include/as= m/early_console.h new file mode 100644 index 000000000000..0683a42e9207 --- /dev/null +++ b/arch/riscv/include/asm/early_console.h @@ -0,0 +1,23 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#ifndef _ASM_EARLY_CONSOLE_H +#define _ASM_EARLY_CONSOLE_H +#ifdef __KERNEL__ + +#include +#include + +void __init early_console_init(void); + +/* early_console libs */ +void early_console_puts(const char *s); +int early_console_write(const char *s, int n); +void early_console_printf(const char *fmt, ...); +void early_console_progress(char *s, unsigned short hex); + +#ifdef CONFIG_RISCV_EARLY_CONSOLE_SBI +void __init hvc_sbi_early_init(void (**putc)(char c)); +#endif /* CONFIG_HVC_RISCV_SBI */ + +#endif /* __KERNEL__ */ +#endif /* _ASM_EARLY_CONSOLE_H */ diff --git a/arch/riscv/kernel/Makefile b/arch/riscv/kernel/Makefile index 81d94a8ee10f..ef037e3762f1 100644 --- a/arch/riscv/kernel/Makefile +++ b/arch/riscv/kernel/Makefile @@ -48,6 +48,7 @@ obj-y +=3D ptrace.o obj-y +=3D reset.o obj-y +=3D return_address.o obj-y +=3D setup.o +obj-y +=3D early_console.o obj-y +=3D signal.o obj-y +=3D syscall_table.o obj-y +=3D sys_riscv.o diff --git a/arch/riscv/kernel/early_console.c b/arch/riscv/kernel/early_co= nsole.c new file mode 100644 index 000000000000..64f3a5705413 --- /dev/null +++ b/arch/riscv/kernel/early_console.c @@ -0,0 +1,108 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Early console support for RISCV + */ + +#include +#include +#include +#include +#include + +/* interface for early console output characters */ +void (*riscv_early_console_putc)(char c); + +void early_console_puts(const char *s) +{ + if (riscv_early_console_putc) { + char c; + + if (s && *s !=3D '\0') { + while ((c =3D *s++) !=3D '\0') + riscv_early_console_putc(c); + } + } +} + +int early_console_write(const char *s, int n) +{ + int remain =3D n; + char c; + + if (!riscv_early_console_putc) + return 0; + + if (s && *s !=3D '\0') { + while (((c =3D *s++) !=3D '\0') && (remain-- > 0)) + riscv_early_console_putc(c); + } + + return n - remain; +} + +#define EARLY_CONSOLE_BUFSIZE 256 +void early_console_printf(const char *fmt, ...) +{ + if (riscv_early_console_putc) { + char buf[EARLY_CONSOLE_BUFSIZE]; + va_list args; + + va_start(args, fmt); + vsnprintf(buf, EARLY_CONSOLE_BUFSIZE, fmt, args); + early_console_puts(buf); + va_end(args); + } +} + +void __init early_console_progress(char *s, unsigned short hex) +{ + early_console_puts(s); + early_console_puts("\n"); +} + +/* + * Console based on early console + */ +static void riscv_early_console_write(struct console *con, const char *s, + unsigned int n) +{ + early_console_write(s, n); +} + +static struct console riscv_early_console =3D { + .name =3D "riscv_early_con", + .write =3D riscv_early_console_write, + .flags =3D CON_PRINTBUFFER | CON_ENABLED | CON_BOOT | CON_ANYTIME, + .index =3D 0, +}; + +static void __init register_early_console(void) +{ + if (!riscv_early_console_putc) + return; + + add_preferred_console("riscv_early_con", 0, NULL); + register_console(&riscv_early_console); +} + +/* + * This is called after sbi_init. + */ +void __init early_console_init(void) +{ + /* + * Set riscv_early_console_putc. + * If there are other output interfaces, you can add corresponding code + * to initialize riscv_early_console_putc. + */ +#if defined(CONFIG_RISCV_EARLY_CONSOLE_SBI) + /* using the sbi */ + hvc_sbi_early_init(&riscv_early_console_putc); +#else + /* using other */ +#endif + + console_loglevel =3D CONSOLE_LOGLEVEL_MOTORMOUTH; + register_early_console(); +} + diff --git a/arch/riscv/kernel/setup.c b/arch/riscv/kernel/setup.c index 4f73c0ae44b2..1b48630f0861 100644 --- a/arch/riscv/kernel/setup.c +++ b/arch/riscv/kernel/setup.c @@ -36,6 +36,7 @@ #include #include #include +#include =20 #include "head.h" =20 @@ -255,6 +256,7 @@ void __init setup_arch(char **cmdline_p) =20 early_ioremap_setup(); sbi_init(); + early_console_init(); jump_label_init(); parse_early_param(); =20 --=20 2.25.1 From nobody Mon Feb 9 05:42:14 2026 Received: from smtpbgau2.qq.com (smtpbgau2.qq.com [54.206.34.216]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 30AD01427B for ; Wed, 10 Apr 2024 06:36:07 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=54.206.34.216 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1712730971; cv=none; b=UUeDOtSmPBJ0Pgj3o0HEQj/R3GWONMOvSD3yFZAn6Zvkj9f/Dgia13yFVJHnrUW2hXmDiZjxpWX44/9Jzl3PHLiL69J310SFFgZHGk+e7NkG1757vhNlVpVn3DVw7yErEZB8aDhoUn747bjaupjgBrY3q2upQk65uBePLwb9cSY= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1712730971; c=relaxed/simple; bh=Bswf8GGz9nhrCHVYWM9I5EX2nibhIgOoLY2Rrl6ouss=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; 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charset="utf-8" Use the SBI interface as the early console output interface for the RISC-V platform. Signed-off-by: Jinglin Wen --- drivers/tty/hvc/Kconfig | 12 ++++++++++++ drivers/tty/hvc/hvc_riscv_sbi.c | 29 +++++++++++++++++++++++++++++ 2 files changed, 41 insertions(+) diff --git a/drivers/tty/hvc/Kconfig b/drivers/tty/hvc/Kconfig index c2a4e88b328f..48658d2b700c 100644 --- a/drivers/tty/hvc/Kconfig +++ b/drivers/tty/hvc/Kconfig @@ -118,6 +118,18 @@ config HVC_RISCV_SBI =20 If you don't know what do to here, say N. =20 +config RISCV_EARLY_CONSOLE_SBI + bool "Use SBI as the interface for RISC-V early console" + depends on RISCV + help + Choose 'Y' to use the SBI interface as the early console + output interface for the RISC-V platform. + + This configuration is a temporary setup for debugging + purposes during the boot process to address issues as + early as possible. It should not be enabled in production + kernel. + config HVCS tristate "IBM Hypervisor Virtual Console Server support" depends on PPC_PSERIES && HVC_CONSOLE diff --git a/drivers/tty/hvc/hvc_riscv_sbi.c b/drivers/tty/hvc/hvc_riscv_sb= i.c index cede8a572594..6686dcf62853 100644 --- a/drivers/tty/hvc/hvc_riscv_sbi.c +++ b/drivers/tty/hvc/hvc_riscv_sbi.c @@ -12,6 +12,7 @@ #include =20 #include +#include =20 #include "hvc_console.h" =20 @@ -81,3 +82,31 @@ static int __init hvc_sbi_init(void) return 0; } device_initcall(hvc_sbi_init); + +#ifdef CONFIG_RISCV_EARLY_CONSOLE_SBI +static ssize_t (*sbi_early_putc_common)(uint32_t vtermno, const u8 *buf, s= ize_t count); + +static void sbi_early_putc(char c) +{ + unsigned int termno =3D 0; + int count =3D -1; + + if (c =3D=3D '\n') + sbi_early_putc('\r'); + + do { + count =3D sbi_early_putc_common(termno, &c, 1); + } while (count =3D=3D 0 || count =3D=3D -EAGAIN); +} + +void __init hvc_sbi_early_init(void (**putc)(char c)) +{ + if (sbi_debug_console_available) + sbi_early_putc_common =3D hvc_sbi_dbcn_tty_put; + else if (IS_ENABLED(CONFIG_RISCV_SBI_V01)) + sbi_early_putc_common =3D hvc_sbi_tty_put; + + if (sbi_early_putc_common) + *putc =3D sbi_early_putc; +} +#endif --=20 2.25.1 From nobody Mon Feb 9 05:42:14 2026 Received: from smtpbgsg2.qq.com (smtpbgsg2.qq.com [54.254.200.128]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 055663F8FB for ; Wed, 10 Apr 2024 06:36:23 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=54.254.200.128 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1712730987; cv=none; b=pNd8/VENSJ1XeLE5KEKXkGyQLY/jYh8as09FatrSfcuYGumOQunqaDIcBAAbOqMBIabIzdxB5B/ZfXcKqUUx80RmM5/uQ8Y9ECdT64GFPEo63bMl1W7uEZj63cpydmqrd5DQigBvUWfj7YZqFyL782+dqkiPqgBQRdjq/OfBfes= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1712730987; c=relaxed/simple; bh=xs83s6oIEPW4cMhg8wwW1AMRm0+CYAxYP4GtGXNydqk=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=kXQFquEK4TSrqBwXi2eNwSsV0FjgMW5xT77F0AQW1hgLKoIJCSIx9yApOP/86rumelO8cO02UXcZ399LEDcXWn85CBeqG2qLxlkyHrgcqqc8bzbJfiuVbNw8VAJ6j/MKoFX58WeHclG0qBx7EKOf+pPnHVmk313Tmi7sx3HroG4= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=shingroup.cn; spf=pass smtp.mailfrom=shingroup.cn; arc=none smtp.client-ip=54.254.200.128 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=shingroup.cn Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=shingroup.cn X-QQ-mid: bizesmtp86t1712730902t5w2xg72 X-QQ-Originating-IP: 11WQUV0r5zeVO1AoN22iVtolLSL58diAT6MAVG6NtKQ= Received: from HX01040082.powercore.com.cn ( [14.19.197.107]) by bizesmtp.qq.com (ESMTP) with id ; Wed, 10 Apr 2024 14:34:58 +0800 (CST) X-QQ-SSF: 01400000000000B09000000A0000000 X-QQ-FEAT: 5x8Sgf4S6/ibmGyV3WobG9KCGSh3CfJOt5MS70mBYmRNDkCu/CLpXhQakp5Oe foHkHFQ1Xb62EDUYBvSRqWRKlrXc7moIGe8iNUnjxQKslMyV8YQCBcaGCOiKN72aLhnkb9s qNBcKElaSgGw8eK1Nbg9TW54oX0kJKLmJ8SyGcJiZc7LN/WMbDkysH3TowkGKuVqHU6AJf1 TYjI62P5c24MuSiQtir9YxixB4NvUopOkYEibXf8t3Lt0uc0GN87tZogJaE3W1IdwghmFxk hhxcKuRf8YDztHPEySvI6UzYdBhu4PwrfPMQ4CCuDkJtK0XQKTnFDDQtDD8ypNIj5YhN0mH 9WhpuUyxrla5J1CssyEBPGPLczjMHHJFTsvpxDbDMOwE687rH6VyqHNv4N19U5fyff5++lE P0eZmeeSJvRVNpBLaMYAgGZSpm8ogdtr X-QQ-GoodBg: 2 X-BIZMAIL-ID: 4090882819559728776 From: Jinglin Wen To: palmer@dabbelt.com Cc: paul.walmsley@sifive.com, aou@eecs.berkeley.edu, gregkh@linuxfoundation.org, atishp@rivosinc.com, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, Jinglin Wen Subject: [PATCH 3/3] riscv: Add information for MAINTAINERS Date: Wed, 10 Apr 2024 14:34:32 +0800 Message-Id: <20240410063432.23058-4-jinglin.wen@shingroup.cn> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20240410063432.23058-1-jinglin.wen@shingroup.cn> References: <20240410063432.23058-1-jinglin.wen@shingroup.cn> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-QQ-SENDSIZE: 520 Feedback-ID: bizesmtp:shingroup.cn:qybglogicsvrgz:qybglogicsvrgz5a-2 Content-Type: text/plain; charset="utf-8" Add the description of the RISC-V early console to MAINTAINERS. Signed-off-by: Jinglin Wen --- MAINTAINERS | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index aa3b947fb080..bdc013ac4e75 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -18936,6 +18936,12 @@ F: arch/riscv/ N: riscv K: riscv =20 +RISC-V EARLY CONSOLE SUPPORT +M: Jinglin Wen +S: Supported +F: arch/riscv/include/asm/early_console.h +F: arch/riscv/kernel/early_console.c + RISC-V MICROCHIP FPGA SUPPORT M: Conor Dooley M: Daire McNamara --=20 2.25.1