From nobody Mon Feb 9 10:50:23 2026 Received: from szxga05-in.huawei.com (szxga05-in.huawei.com [45.249.212.191]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 02E661C0DF7 for ; Wed, 10 Apr 2024 02:41:38 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=45.249.212.191 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1712716901; cv=none; b=DkCKKG+AhGkLjqHE6Z+04GM9cw+x/RkQKkiC2B4M6t17lkoKKHiEQEZjR1WEI6sYmUzNDqFJET+Hn86WykZIylu2O8WT3PM2gdMAw4vYc6MNfGtlczKRy3TTb2miGboGZ1feH/FH2dZleB3AIYZyhhyB+dpMSAGO4w2WQxgr1W8= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1712716901; c=relaxed/simple; bh=JP4edOYcvTr2nOSePK/AZ4E/aJzYBM/Vm8VtB3E6TfE=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=QmruOM8eYA/SGIjJVXAP48l1j0PVS3ZFhL5JyEP8WliaSFxMBkNXDWlHVnNCaN+eZLOL94ykcKJX1UOPEjLmwAfMdfzLl7PuDRIqQ0HXRSH1MHbH8FbT7aiIlhFANnPQoKu36FyEYSsdktwXA7MVKaQeZmhrd/RiExGRmoRnmPw= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=huawei.com; spf=pass smtp.mailfrom=huawei.com; arc=none smtp.client-ip=45.249.212.191 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=huawei.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=huawei.com Received: from mail.maildlp.com (unknown [172.19.163.44]) by szxga05-in.huawei.com (SkyGuard) with ESMTP id 4VDnBV6gS9z1GGgj; Wed, 10 Apr 2024 10:40:50 +0800 (CST) Received: from kwepemm600014.china.huawei.com (unknown [7.193.23.54]) by mail.maildlp.com (Postfix) with ESMTPS id A0EAE14010C; Wed, 10 Apr 2024 10:41:36 +0800 (CST) Received: from Linux-SUSE12SP5.huawei.com (10.67.136.233) by kwepemm600014.china.huawei.com (7.193.23.54) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.1.2507.35; Wed, 10 Apr 2024 10:41:36 +0800 From: zhuqiuer To: CC: , , , , , , , , Subject: [PATCH v2] ARM: Add a memory clobber to the fmrx instruction Date: Wed, 10 Apr 2024 10:41:26 +0800 Message-ID: <20240410024126.21589-2-zhuqiuer1@huawei.com> X-Mailer: git-send-email 2.12.3 In-Reply-To: <20240410024126.21589-1-zhuqiuer1@huawei.com> References: <20240409164641.GC3219862@dev-arch.thelio-3990X> <20240410024126.21589-1-zhuqiuer1@huawei.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: dggems705-chm.china.huawei.com (10.3.19.182) To kwepemm600014.china.huawei.com (7.193.23.54) Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The instruction fmrx is used throughout the kernel, where it is sometimes expected to be skipped by incrementing the program counter, such as in vfpmodule.c:vfp_init(). Therefore, the instruction should not be reordered when it is not intended. Adding a barrier() instruction before and after this call cannot prevent reordering by the compiler, as the fmrx instruction is constrained by '=3Dr', meaning it works on the general register but not on memory. To ensure the order of the instruction after compiling, adding a memory clobber is necessary. Below is the code snippet disassembled from the method: vfpmodule.c:vfp_init(), compiled by LLVM. Before the patching: xxxxx: xxxxx bl c010c688 xxxxx: xxxxx mov r0, r4 xxxxx: xxxxx bl c010c6e4 ... xxxxx: xxxxx bl c0791c8c xxxxx: xxxxx movw r5, #23132 ; 0x5a5c xxxxx: xxxxx vmrs r4, fpsid <- this is the fmrx instruction After the patching: xxxxx: xxxxx bl c010c688 xxxxx: xxxxx mov r0, r4 xxxxx: xxxxx vmrs r5, fpsid <- this is the fmrx instruction xxxxx: xxxxx bl c010c6e4 Signed-off-by: zhuqiuer Reviewed-by: Ard Biesheuvel Reviewed-by: Nathan Chancellor --- arch/arm/vfp/vfpinstr.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm/vfp/vfpinstr.h b/arch/arm/vfp/vfpinstr.h index 3c7938fd40aa..ae2c9b9b7701 100644 --- a/arch/arm/vfp/vfpinstr.h +++ b/arch/arm/vfp/vfpinstr.h @@ -68,14 +68,14 @@ u32 __v; \ asm(".fpu vfpv2\n" \ "vmrs %0, " #_vfp_ \ - : "=3Dr" (__v) : : "cc"); \ + : "=3Dr" (__v) : : "memory", "cc"); \ __v; \ }) =20 #define fmxr(_vfp_,_var_) \ asm(".fpu vfpv2\n" \ "vmsr " #_vfp_ ", %0" \ - : : "r" (_var_) : "cc") + : : "r" (_var_) : "memory", "cc") =20 #else =20 --=20 2.12.3