From nobody Sun Feb 8 04:11:44 2026 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.20]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 2645A29CF2 for ; Wed, 10 Apr 2024 02:10:32 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.20 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1712715033; cv=none; b=XuoswkI+zTu2rsD26fVap/dnHTpRAaqupTpc9q8UEQkn/5EP+SpOcRGVVo2EW4KhkauJaLoNyLWcLxda48Ey7c+IvhqLUdLSAfpY0TLTvkM/MBcS6mOwzalj/+nyOP1vikF4+SuJzvpPDUp1mRC3gdZN7o/oY1yHLgLrrMC7tNY= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1712715033; c=relaxed/simple; bh=8uOaaxm9hTyzO9Aw/q0vgU9R2IfJCzDzjSxHWJxDukU=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=QBdx8tl3JFPd2Afad4xsB0e9HrJh3Yvg0wDi8h3v5l9edq5/do9196oLBPCLQuU9NFD3P3bz1YCwBiEOIDaV8flxHkNIn+vUHYg14zEAGG/5CLLPFLFKrGOTdYDDcMKHIBur/9t8OPMh+dZDb8zEs1DHBMamcPD15zTcBFteNZA= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com; spf=none smtp.mailfrom=linux.intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=inInR1bC; arc=none smtp.client-ip=198.175.65.20 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; spf=none smtp.mailfrom=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="inInR1bC" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1712715033; x=1744251033; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=8uOaaxm9hTyzO9Aw/q0vgU9R2IfJCzDzjSxHWJxDukU=; b=inInR1bCWJryw+TC94CvYQ1B4rp/jGOPw2dygTWuouSIduxFXQwZkW+z gHQFyErMt5lfIElkZPiMR1pP9AS2jlfQ9dP2m+FwWqKVggg50UzkXJnWJ Z0Q8WN++ry8C3ItxQZJTPG1z1IWWUU86xQsQDgTHR8koxXyy+AJWPQ/XM i2dpHVUphocC8okqUASTEBEPGYLwKHWs5+L67pSYkknIz/JFtkjK3vbG/ 2OUQ/jayh6oQtIosUoZLiPh+IGz2ffYpzkAmVR5ij821Bsbq/v6NZgy1j jZPxyz8VsgK4cEIMtFtnvQ5EqYGi4lf7qoQjecYKvUFqaghodixjyDAyD Q==; X-CSE-ConnectionGUID: gzJPafmKRBuQwNHB5RnkkA== X-CSE-MsgGUID: 2LVECzpmRuOy7mETo0SDhw== X-IronPort-AV: E=McAfee;i="6600,9927,11039"; a="7918612" X-IronPort-AV: E=Sophos;i="6.07,190,1708416000"; d="scan'208";a="7918612" Received: from fmviesa007.fm.intel.com ([10.60.135.147]) by orvoesa112.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 09 Apr 2024 19:10:30 -0700 X-CSE-ConnectionGUID: 5ff/sxeVT2eCB/5ogfr3Wg== X-CSE-MsgGUID: iasNmo9gScia7A0L1BKg7Q== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.07,190,1708416000"; d="scan'208";a="20478936" Received: from unknown (HELO allen-box.sh.intel.com) ([10.239.159.127]) by fmviesa007.fm.intel.com with ESMTP; 09 Apr 2024 19:10:26 -0700 From: Lu Baolu To: Joerg Roedel , Will Deacon , Robin Murphy , Kevin Tian , Jason Gunthorpe Cc: Tina Zhang , Yi Liu , iommu@lists.linux.dev, linux-kernel@vger.kernel.org, Lu Baolu Subject: [PATCH v2 10/12] iommu/vt-d: Retire intel_svm_dev Date: Wed, 10 Apr 2024 10:08:42 +0800 Message-Id: <20240410020844.253535-11-baolu.lu@linux.intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240410020844.253535-1-baolu.lu@linux.intel.com> References: <20240410020844.253535-1-baolu.lu@linux.intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The intel_svm_dev data structure used in the sva implementation for the Intel IOMMU driver stores information about a device attached to an SVA domain. It is a duplicate of dev_pasid_info that serves the same purpose. Replace intel_svm_dev with dev_pasid_info and clean up the use of intel_svm_dev. Signed-off-by: Lu Baolu --- drivers/iommu/intel/iommu.h | 15 +---- drivers/iommu/intel/iommu.c | 30 ++++----- drivers/iommu/intel/svm.c | 131 +++++++++++------------------------- 3 files changed, 55 insertions(+), 121 deletions(-) diff --git a/drivers/iommu/intel/iommu.h b/drivers/iommu/intel/iommu.h index 5a42d6ee9119..90611ec08a7c 100644 --- a/drivers/iommu/intel/iommu.h +++ b/drivers/iommu/intel/iommu.h @@ -650,6 +650,7 @@ struct dmar_domain { struct list_head s2_link; }; }; + struct intel_svm *svm; =20 struct iommu_domain domain; /* generic domain data structure for iommu core */ @@ -1144,23 +1145,13 @@ int intel_svm_finish_prq(struct intel_iommu *iommu); void intel_svm_page_response(struct device *dev, struct iopf_fault *evt, struct iommu_page_response *msg); struct iommu_domain *intel_svm_domain_alloc(void); -void intel_svm_remove_dev_pasid(struct device *dev, ioasid_t pasid); +void intel_svm_remove_dev_pasid(struct iommu_domain *domain); void intel_drain_pasid_prq(struct device *dev, u32 pasid); =20 -struct intel_svm_dev { - struct list_head list; - struct rcu_head rcu; - struct device *dev; - struct intel_iommu *iommu; - u16 did; - u16 sid, qdep; -}; - struct intel_svm { struct mmu_notifier notifier; struct mm_struct *mm; u32 pasid; - struct list_head devs; struct dmar_domain *domain; }; #else @@ -1171,7 +1162,7 @@ static inline struct iommu_domain *intel_svm_domain_a= lloc(void) return NULL; } =20 -static inline void intel_svm_remove_dev_pasid(struct device *dev, ioasid_t= pasid) +static inline void intel_svm_remove_dev_pasid(struct iommu_domain *domain) { } #endif diff --git a/drivers/iommu/intel/iommu.c b/drivers/iommu/intel/iommu.c index 586b6a6afc23..d7f205cd0aac 100644 --- a/drivers/iommu/intel/iommu.c +++ b/drivers/iommu/intel/iommu.c @@ -4377,18 +4377,6 @@ static void intel_iommu_remove_dev_pasid(struct devi= ce *dev, ioasid_t pasid) goto out_tear_down; dmar_domain =3D to_dmar_domain(domain); =20 - /* - * The SVA implementation needs to handle its own stuffs like the mm - * notification. Before consolidating that code into iommu core, let - * the intel sva code handle it. - */ - if (domain->type =3D=3D IOMMU_DOMAIN_SVA) { - intel_svm_remove_dev_pasid(dev, pasid); - cache_tag_unassign_domain(dmar_domain, - FLPT_DEFAULT_DID, dev, pasid); - goto out_tear_down; - } - spin_lock_irqsave(&dmar_domain->lock, flags); list_for_each_entry(curr, &dmar_domain->dev_pasids, link_domain) { if (curr->dev =3D=3D dev && curr->pasid =3D=3D pasid) { @@ -4400,10 +4388,20 @@ static void intel_iommu_remove_dev_pasid(struct dev= ice *dev, ioasid_t pasid) WARN_ON_ONCE(!dev_pasid); spin_unlock_irqrestore(&dmar_domain->lock, flags); =20 - did =3D domain_id_iommu(dmar_domain, iommu); - cache_tag_unassign_domain(dmar_domain, did, dev, pasid); - domain_detach_iommu(dmar_domain, iommu); - intel_iommu_debugfs_remove_dev_pasid(dev_pasid); + /* + * The SVA implementation needs to handle its own stuffs like the mm + * notification. Before consolidating that code into iommu core, let + * the intel sva code handle it. + */ + if (domain->type =3D=3D IOMMU_DOMAIN_SVA) { + cache_tag_unassign_domain(dmar_domain, FLPT_DEFAULT_DID, dev, pasid); + intel_svm_remove_dev_pasid(domain); + } else { + did =3D domain_id_iommu(dmar_domain, iommu); + cache_tag_unassign_domain(dmar_domain, did, dev, pasid); + domain_detach_iommu(dmar_domain, iommu); + intel_iommu_debugfs_remove_dev_pasid(dev_pasid); + } kfree(dev_pasid); out_tear_down: intel_pasid_tear_down_entry(iommu, dev, pasid, false); diff --git a/drivers/iommu/intel/svm.c b/drivers/iommu/intel/svm.c index 751fab476fa2..0b767d16fb71 100644 --- a/drivers/iommu/intel/svm.c +++ b/drivers/iommu/intel/svm.c @@ -43,23 +43,6 @@ static void *pasid_private_find(ioasid_t pasid) return xa_load(&pasid_private_array, pasid); } =20 -static struct intel_svm_dev * -svm_lookup_device_by_dev(struct intel_svm *svm, struct device *dev) -{ - struct intel_svm_dev *sdev =3D NULL, *t; - - rcu_read_lock(); - list_for_each_entry_rcu(t, &svm->devs, list) { - if (t->dev =3D=3D dev) { - sdev =3D t; - break; - } - } - rcu_read_unlock(); - - return sdev; -} - int intel_svm_enable_prq(struct intel_iommu *iommu) { struct iopf_queue *iopfq; @@ -187,7 +170,10 @@ static void intel_arch_invalidate_secondary_tlbs(struc= t mmu_notifier *mn, static void intel_mm_release(struct mmu_notifier *mn, struct mm_struct *mm) { struct intel_svm *svm =3D container_of(mn, struct intel_svm, notifier); - struct intel_svm_dev *sdev; + struct dmar_domain *domain =3D svm->domain; + struct dev_pasid_info *dev_pasid; + struct device_domain_info *info; + unsigned long flags; =20 /* This might end up being called from exit_mmap(), *before* the page * tables are cleared. And __mmu_notifier_release() will delete us from @@ -201,11 +187,13 @@ static void intel_mm_release(struct mmu_notifier *mn,= struct mm_struct *mm) * page) so that we end up taking a fault that the hardware really * *has* to handle gracefully without affecting other processes. */ - rcu_read_lock(); - list_for_each_entry_rcu(sdev, &svm->devs, list) - intel_pasid_tear_down_entry(sdev->iommu, sdev->dev, - svm->pasid, true); - rcu_read_unlock(); + spin_lock_irqsave(&domain->lock, flags); + list_for_each_entry(dev_pasid, &domain->dev_pasids, link_domain) { + info =3D dev_iommu_priv_get(dev_pasid->dev); + intel_pasid_tear_down_entry(info->iommu, dev_pasid->dev, + dev_pasid->pasid, true); + } + spin_unlock_irqrestore(&domain->lock, flags); =20 } =20 @@ -214,47 +202,17 @@ static const struct mmu_notifier_ops intel_mmuops =3D= { .arch_invalidate_secondary_tlbs =3D intel_arch_invalidate_secondary_tlbs, }; =20 -static int pasid_to_svm_sdev(struct device *dev, unsigned int pasid, - struct intel_svm **rsvm, - struct intel_svm_dev **rsdev) -{ - struct intel_svm_dev *sdev =3D NULL; - struct intel_svm *svm; - - if (pasid =3D=3D IOMMU_PASID_INVALID || pasid >=3D PASID_MAX) - return -EINVAL; - - svm =3D pasid_private_find(pasid); - if (IS_ERR(svm)) - return PTR_ERR(svm); - - if (!svm) - goto out; - - /* - * If we found svm for the PASID, there must be at least one device - * bond. - */ - if (WARN_ON(list_empty(&svm->devs))) - return -EINVAL; - sdev =3D svm_lookup_device_by_dev(svm, dev); - -out: - *rsvm =3D svm; - *rsdev =3D sdev; - - return 0; -} - static int intel_svm_set_dev_pasid(struct iommu_domain *domain, struct device *dev, ioasid_t pasid) { struct device_domain_info *info =3D dev_iommu_priv_get(dev); + struct dmar_domain *dmar_domain =3D to_dmar_domain(domain); struct intel_iommu *iommu =3D info->iommu; struct mm_struct *mm =3D domain->mm; - struct intel_svm_dev *sdev; + struct dev_pasid_info *dev_pasid; struct intel_svm *svm; unsigned long sflags; + unsigned long flags; int ret =3D 0; =20 svm =3D pasid_private_find(pasid); @@ -265,7 +223,6 @@ static int intel_svm_set_dev_pasid(struct iommu_domain = *domain, =20 svm->pasid =3D pasid; svm->mm =3D mm; - INIT_LIST_HEAD_RCU(&svm->devs); =20 svm->notifier.ops =3D &intel_mmuops; svm->domain =3D to_dmar_domain(domain); @@ -283,26 +240,19 @@ static int intel_svm_set_dev_pasid(struct iommu_domai= n *domain, } } =20 - sdev =3D kzalloc(sizeof(*sdev), GFP_KERNEL); - if (!sdev) { - ret =3D -ENOMEM; + dmar_domain->svm =3D svm; + + dev_pasid =3D kzalloc(sizeof(*dev_pasid), GFP_KERNEL); + if (!dev_pasid) goto free_svm; - } =20 - sdev->dev =3D dev; - sdev->iommu =3D iommu; - sdev->did =3D FLPT_DEFAULT_DID; - sdev->sid =3D PCI_DEVID(info->bus, info->devfn); - if (info->ats_enabled) { - sdev->qdep =3D info->ats_qdep; - if (sdev->qdep >=3D QI_DEV_EIOTLB_MAX_INVS) - sdev->qdep =3D 0; - } + dev_pasid->dev =3D dev; + dev_pasid->pasid =3D pasid; =20 ret =3D cache_tag_assign_domain(to_dmar_domain(domain), FLPT_DEFAULT_DID, dev, pasid); if (ret) - goto free_sdev; + goto free_dev_pasid; =20 /* Setup the pasid table: */ sflags =3D cpu_feature_enabled(X86_FEATURE_LA57) ? PASID_FLAG_FL5LP : 0; @@ -311,17 +261,19 @@ static int intel_svm_set_dev_pasid(struct iommu_domai= n *domain, if (ret) goto unassign_tag; =20 - list_add_rcu(&sdev->list, &svm->devs); + spin_lock_irqsave(&dmar_domain->lock, flags); + list_add(&dev_pasid->link_domain, &dmar_domain->dev_pasids); + spin_unlock_irqrestore(&dmar_domain->lock, flags); =20 return 0; =20 unassign_tag: cache_tag_unassign_domain(to_dmar_domain(domain), FLPT_DEFAULT_DID, dev, pasid); -free_sdev: - kfree(sdev); +free_dev_pasid: + kfree(dev_pasid); free_svm: - if (list_empty(&svm->devs)) { + if (list_empty(&dmar_domain->dev_pasids)) { mmu_notifier_unregister(&svm->notifier, mm); pasid_private_remove(pasid); kfree(svm); @@ -330,26 +282,17 @@ static int intel_svm_set_dev_pasid(struct iommu_domai= n *domain, return ret; } =20 -void intel_svm_remove_dev_pasid(struct device *dev, u32 pasid) +void intel_svm_remove_dev_pasid(struct iommu_domain *domain) { - struct intel_svm_dev *sdev; - struct intel_svm *svm; - struct mm_struct *mm; + struct dmar_domain *dmar_domain =3D to_dmar_domain(domain); + struct intel_svm *svm =3D dmar_domain->svm; + struct mm_struct *mm =3D domain->mm; =20 - if (pasid_to_svm_sdev(dev, pasid, &svm, &sdev)) - return; - mm =3D svm->mm; - - if (sdev) { - list_del_rcu(&sdev->list); - kfree_rcu(sdev, rcu); - - if (list_empty(&svm->devs)) { - if (svm->notifier.ops) - mmu_notifier_unregister(&svm->notifier, mm); - pasid_private_remove(svm->pasid); - kfree(svm); - } + if (list_empty(&dmar_domain->dev_pasids)) { + if (svm->notifier.ops) + mmu_notifier_unregister(&svm->notifier, mm); + pasid_private_remove(svm->pasid); + kfree(svm); } } =20 @@ -737,8 +680,10 @@ struct iommu_domain *intel_svm_domain_alloc(void) return NULL; domain->domain.ops =3D &intel_svm_domain_ops; domain->use_first_level =3D true; + INIT_LIST_HEAD(&domain->dev_pasids); INIT_LIST_HEAD(&domain->cache_tags); spin_lock_init(&domain->cache_lock); + spin_lock_init(&domain->lock); =20 return &domain->domain; } --=20 2.34.1